enum class MachineCombinerPattern
Description
These are instruction patterns matched by the machine combiner pass.
Declared at: llvm/include/llvm/CodeGen/MachineCombinerPattern.h:20
Enumerators
| Name | Value | Comment |
|---|---|---|
| REASSOC_AX_BY | 0 | |
| REASSOC_AX_YB | 1 | |
| REASSOC_XA_BY | 2 | |
| REASSOC_XA_YB | 3 | |
| REASSOC_XY_AMM_BMM | 4 | |
| REASSOC_XMM_AMM_BMM | 5 | |
| REASSOC_XY_BCA | 6 | |
| REASSOC_XY_BAC | 7 | |
| SUBADD_OP1 | 8 | |
| SUBADD_OP2 | 9 | |
| MULADDW_OP1 | 10 | |
| MULADDW_OP2 | 11 | |
| MULSUBW_OP1 | 12 | |
| MULSUBW_OP2 | 13 | |
| MULADDWI_OP1 | 14 | |
| MULSUBWI_OP1 | 15 | |
| MULADDX_OP1 | 16 | |
| MULADDX_OP2 | 17 | |
| MULSUBX_OP1 | 18 | |
| MULSUBX_OP2 | 19 | |
| MULADDXI_OP1 | 20 | |
| MULSUBXI_OP1 | 21 | |
| MULADDv8i8_OP1 | 22 | |
| MULADDv8i8_OP2 | 23 | |
| MULADDv16i8_OP1 | 24 | |
| MULADDv16i8_OP2 | 25 | |
| MULADDv4i16_OP1 | 26 | |
| MULADDv4i16_OP2 | 27 | |
| MULADDv8i16_OP1 | 28 | |
| MULADDv8i16_OP2 | 29 | |
| MULADDv2i32_OP1 | 30 | |
| MULADDv2i32_OP2 | 31 | |
| MULADDv4i32_OP1 | 32 | |
| MULADDv4i32_OP2 | 33 | |
| MULSUBv8i8_OP1 | 34 | |
| MULSUBv8i8_OP2 | 35 | |
| MULSUBv16i8_OP1 | 36 | |
| MULSUBv16i8_OP2 | 37 | |
| MULSUBv4i16_OP1 | 38 | |
| MULSUBv4i16_OP2 | 39 | |
| MULSUBv8i16_OP1 | 40 | |
| MULSUBv8i16_OP2 | 41 | |
| MULSUBv2i32_OP1 | 42 | |
| MULSUBv2i32_OP2 | 43 | |
| MULSUBv4i32_OP1 | 44 | |
| MULSUBv4i32_OP2 | 45 | |
| MULADDv4i16_indexed_OP1 | 46 | |
| MULADDv4i16_indexed_OP2 | 47 | |
| MULADDv8i16_indexed_OP1 | 48 | |
| MULADDv8i16_indexed_OP2 | 49 | |
| MULADDv2i32_indexed_OP1 | 50 | |
| MULADDv2i32_indexed_OP2 | 51 | |
| MULADDv4i32_indexed_OP1 | 52 | |
| MULADDv4i32_indexed_OP2 | 53 | |
| MULSUBv4i16_indexed_OP1 | 54 | |
| MULSUBv4i16_indexed_OP2 | 55 | |
| MULSUBv8i16_indexed_OP1 | 56 | |
| MULSUBv8i16_indexed_OP2 | 57 | |
| MULSUBv2i32_indexed_OP1 | 58 | |
| MULSUBv2i32_indexed_OP2 | 59 | |
| MULSUBv4i32_indexed_OP1 | 60 | |
| MULSUBv4i32_indexed_OP2 | 61 | |
| FMULADDH_OP1 | 62 | |
| FMULADDH_OP2 | 63 | |
| FMULSUBH_OP1 | 64 | |
| FMULSUBH_OP2 | 65 | |
| FMULADDS_OP1 | 66 | |
| FMULADDS_OP2 | 67 | |
| FMULSUBS_OP1 | 68 | |
| FMULSUBS_OP2 | 69 | |
| FMULADDD_OP1 | 70 | |
| FMULADDD_OP2 | 71 | |
| FMULSUBD_OP1 | 72 | |
| FMULSUBD_OP2 | 73 | |
| FNMULSUBH_OP1 | 74 | |
| FNMULSUBS_OP1 | 75 | |
| FNMULSUBD_OP1 | 76 | |
| FMLAv1i32_indexed_OP1 | 77 | |
| FMLAv1i32_indexed_OP2 | 78 | |
| FMLAv1i64_indexed_OP1 | 79 | |
| FMLAv1i64_indexed_OP2 | 80 | |
| FMLAv4f16_OP1 | 81 | |
| FMLAv4f16_OP2 | 82 | |
| FMLAv8f16_OP1 | 83 | |
| FMLAv8f16_OP2 | 84 | |
| FMLAv2f32_OP2 | 85 | |
| FMLAv2f32_OP1 | 86 | |
| FMLAv2f64_OP1 | 87 | |
| FMLAv2f64_OP2 | 88 | |
| FMLAv4i16_indexed_OP1 | 89 | |
| FMLAv4i16_indexed_OP2 | 90 | |
| FMLAv8i16_indexed_OP1 | 91 | |
| FMLAv8i16_indexed_OP2 | 92 | |
| FMLAv2i32_indexed_OP1 | 93 | |
| FMLAv2i32_indexed_OP2 | 94 | |
| FMLAv2i64_indexed_OP1 | 95 | |
| FMLAv2i64_indexed_OP2 | 96 | |
| FMLAv4f32_OP1 | 97 | |
| FMLAv4f32_OP2 | 98 | |
| FMLAv4i32_indexed_OP1 | 99 | |
| FMLAv4i32_indexed_OP2 | 100 | |
| FMLSv1i32_indexed_OP2 | 101 | |
| FMLSv1i64_indexed_OP2 | 102 | |
| FMLSv4f16_OP1 | 103 | |
| FMLSv4f16_OP2 | 104 | |
| FMLSv8f16_OP1 | 105 | |
| FMLSv8f16_OP2 | 106 | |
| FMLSv2f32_OP1 | 107 | |
| FMLSv2f32_OP2 | 108 | |
| FMLSv2f64_OP1 | 109 | |
| FMLSv2f64_OP2 | 110 | |
| FMLSv4i16_indexed_OP1 | 111 | |
| FMLSv4i16_indexed_OP2 | 112 | |
| FMLSv8i16_indexed_OP1 | 113 | |
| FMLSv8i16_indexed_OP2 | 114 | |
| FMLSv2i32_indexed_OP1 | 115 | |
| FMLSv2i32_indexed_OP2 | 116 | |
| FMLSv2i64_indexed_OP1 | 117 | |
| FMLSv2i64_indexed_OP2 | 118 | |
| FMLSv4f32_OP1 | 119 | |
| FMLSv4f32_OP2 | 120 | |
| FMLSv4i32_indexed_OP1 | 121 | |
| FMLSv4i32_indexed_OP2 | 122 | |
| FMULv2i32_indexed_OP1 | 123 | |
| FMULv2i32_indexed_OP2 | 124 | |
| FMULv2i64_indexed_OP1 | 125 | |
| FMULv2i64_indexed_OP2 | 126 | |
| FMULv4i16_indexed_OP1 | 127 | |
| FMULv4i16_indexed_OP2 | 128 | |
| FMULv4i32_indexed_OP1 | 129 | |
| FMULv4i32_indexed_OP2 | 130 | |
| FMULv8i16_indexed_OP1 | 131 | |
| FMULv8i16_indexed_OP2 | 132 |