class MCInstrDesc

Declaration

class MCInstrDesc { /* full declaration omitted */ };

Description

Describe properties that are true of each instruction in the target description file. This captures information about side effects, register use and many other things. There is one instance of this struct for each target instruction class, and the MachineInstr class points to this struct directly to describe itself.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:197

Member Variables

public unsigned short Opcode
public unsigned short NumOperands
public unsigned char NumDefs
public unsigned char Size
public unsigned short SchedClass
public uint64_t Flags
public uint64_t TSFlags
public const llvm::MCPhysReg* ImplicitUses
public const llvm::MCPhysReg* ImplicitDefs
public const llvm::MCOperandInfo* OpInfo

Method Overview

Methods

bool canFoldAsLoad() const

Description

Return true for instructions that can be folded as memory operands in other instructions. The most common use for this is instructions that are simple loads from memory that don't modify the loaded value in any way, but it can also be used for instructions that can be expressed as constant-pool loads, such as V_SETALLONES on x86, to allow them to be folded when it is beneficial. This should only be set on instructions that return a value in their only virtual register definition.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:366

int findFirstPredOperandIdx() const

Description

Find the index of the first operand in the operand list that is used to represent the predicate. It returns -1 if none is found.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:627

uint64_t getFlags() const

Description

Return flags of this instruction.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:248

const llvm::MCPhysReg* getImplicitDefs() const

Description

Return a list of registers that are potentially written by any instance of this machine instruction. For example, on X86, many instructions implicitly set the flags register. In this case, they are marked as setting the FLAGS. Likewise, many instructions always deposit their result in a physical register. For example, the X86 divide instruction always deposits the quotient and remainder in the EAX/EDX registers. For that instruction, this will return a list containing the EAX/EDX/EFLAGS registers. This method returns null if the instruction has no implicit defs.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:587

const llvm::MCPhysReg* getImplicitUses() const

Description

Return a list of registers that are potentially read by any instance of this machine instruction. For example, on X86, the "adc" instruction adds two register operands and adds the carry bit in from the flags register. In this case, the instruction is marked as implicitly reading the flags. Likewise, the variable shift instruction on X86 is marked as implicitly reading the 'CL' register, which it always does. This method returns null if the instruction has no implicit uses.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:565

unsigned int getNumDefs() const

Description

Return the number of MachineOperands that are register definitions. Register definitions always occur at the start of the machine operand list. This is the number of "outs" in the .td file, and does not include implicit defs.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:245

unsigned int getNumImplicitDefs() const

Description

Return the number of implicit defs this instruct has.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:590

unsigned int getNumImplicitUses() const

Description

Return the number of implicit uses this instruction has.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:568

unsigned int getNumOperands() const

Description

Return the number of declared MachineOperands for this MachineInstruction. Note that variadic (isVariadic() returns true) instructions may have additional operands at the end of the list, and note that the machine instruction may include implicit register def/uses as well.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:230

unsigned int getOpcode() const

Description

Return the opcode number for this descriptor.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:223

int getOperandConstraint(
    unsigned int OpNum,
    MCOI::OperandConstraint Constraint) const

Description

Returns the value of the specified operand constraint if it is present. Returns -1 if it is not present.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:212

Parameters

unsigned int OpNum
MCOI::OperandConstraint Constraint

unsigned int getSchedClass() const

Description

Return the scheduling class for this instruction. The scheduling class is an index into the InstrItineraryData table. This returns zero if there is no known scheduling information for the instruction.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:618

unsigned int getSize() const

Description

Return the number of bytes in the encoding of this instruction, or zero if the encoding size cannot be known from the opcode.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:622

bool hasDefOfPhysReg(
    const llvm::MCInst& MI,
    unsigned int Reg,
    const llvm::MCRegisterInfo& RI) const

Description

Return true if this instruction defines the specified physical register, either explicitly or implicitly.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:638

Parameters

const llvm::MCInst& MI
unsigned int Reg
const llvm::MCRegisterInfo& RI

bool hasDelaySlot() const

Description

Returns true if the specified instruction has a delay slot which must be filled by the code generator.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:357

bool hasExtraDefRegAllocReq() const

Description

Returns true if this instruction def operands have special register allocation requirements that are not captured by the operand register classes. e.g. ARM::LDRD's two def registers must be an even / odd pair, ARM::LDM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for definitions of instructions with this flag.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:553

bool hasExtraSrcRegAllocReq() const

Description

Returns true if this instruction source operands have special register allocation requirements that are not captured by the operand register classes. e.g. ARM::STRD's two source registers must be an even / odd pair, ARM::STM registers have to be in ascending order. Post-register allocation passes should not attempt to change allocations for sources of instructions with this flag.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:543

bool hasImplicitDefOfPhysReg(
    unsigned int Reg,
    const llvm::MCRegisterInfo* MRI =
        nullptr) const

Description

Return true if this instruction implicitly defines the specified physical register.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:611

Parameters

unsigned int Reg
const llvm::MCRegisterInfo* MRI = nullptr

bool hasImplicitUseOfPhysReg(
    unsigned int Reg) const

Description

Return true if this instruction implicitly uses the specified physical register.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:601

Parameters

unsigned int Reg

bool hasOptionalDef() const

Description

Set if this instruction has an optional definition, e.g. ARM instructions which can set condition code if 's' bit is set.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:262

bool hasPostISelHook() const

Description

Return true if this instruction requires *adjustment* after instruction selection by calling a target hook. For example, this can be used to fill in ARM 's' optional operand depending on whether the conditional flag register is used.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:514

bool hasUnmodeledSideEffects() const

Description

Return true if this instruction has side effects that are not modeled by other flags. This does not return true for instructions whose effects are captured by: 1. Their operand list and implicit definition/use list. Register use/def info is explicit for instructions. 2. Memory accesses. Use mayLoad/mayStore. 3. Calling, branching, returning: use isCall/isReturn/isBranch. Examples of side effects would be modifying 'invisible' machine state like a control register, flushing a cache, modifying a register invisible to LLVM, etc.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:460

bool isAdd() const

Description

Return true if the instruction is an add instruction.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:276

bool isAsCheapAsAMove() const

Description

Returns true if this instruction has the same cost (or less) than a move instruction. This is useful during certain types of optimizations (e.g., remat during two-address conversion or machine licm) where we would like to remat or hoist the instruction, but not if it costs more than moving the instruction into the appropriate register. Note, we are not marking copies from and to the same register class with this flag. This method could be called by interface TargetInstrInfo::isAsCheapAsAMove for different subtargets.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:535

bool isAuthenticated() const

Description

Return true if this instruction authenticates a pointer (e.g. LDRAx/BRAx from ARMv8.3, which perform loads/branches with authentication). An authenticated instruction may fail in an ABI-defined manner when operating on an invalid signed pointer.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:424

bool isBarrier() const

Description

Returns true if the specified instruction stops control flow from executing the instruction immediately following it. Examples include unconditional branches and return instructions.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:290

bool isBitcast() const

Description

Return true if this instruction is a bitcast instruction.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:345

bool isBranch() const

Description

Returns true if this is a conditional, unconditional, or indirect branch. Predicates below can be used to discriminate between these cases, and the TargetInstrInfo::analyzeBranch method can be used to get more information.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:304

bool isCall() const

Description

Return true if the instruction is a call.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:285

bool isCommutable() const

Description

Return true if this may be a 2- or 3-address instruction (of the form "X = op Y, Z, ..."), which produces the same result if Y and Z are exchanged. If this flag is set, then the TargetInstrInfo::commuteInstruction method may be used to hack on the instruction. Note that this flag may be set on instructions that are only commutable sometimes. In these cases, the call to commuteInstruction will fail. Also note that some instructions require non-trivial modification to commute them.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:478

bool isCompare() const

Description

Return true if this instruction is a comparison.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:338

bool isConditionalBranch() const

Description

Return true if this is a branch which may fall through to the next instruction or may transfer control flow to some other block. The TargetInstrInfo::analyzeBranch method can be used to get more information about this branch.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:314

bool isConvergent() const

Description

Return true if this instruction is convergent. Convergent instructions may not be made control-dependent on any additional values.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:412

bool isConvertibleTo3Addr() const

Description

Return true if this is a 2-address instruction which can be changed into a 3-address instruction if needed. Doing this transformation can be profitable in the register allocator, because it means that the instruction can use a 2-address form if possible, but degrade into a less efficient form if the source and dest register cannot be assigned to the same register. For example, this allows the x86 backend to turn a "shl reg, 3" instruction into an LEA instruction, which is the same speed as the shift but has bigger code size. If this returns true, then the target must implement the TargetInstrInfo::convertToThreeAddress method for this instruction, which is allowed to fail if the transformation isn't valid for this specific instruction (e.g. shl reg, 4 on x86).

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:494

bool isExtractSubregLike() const

Description

Return true if this instruction behaves the same way as the generic EXTRACT_SUBREG instructions. E.g., on ARM, rX, rY VMOVRRD dZ is equivalent to two EXTRACT_SUBREG: rX = EXTRACT_SUBREG dZ, ssub_0 rY = EXTRACT_SUBREG dZ, ssub_1 Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getExtractSubregLikeInputs has to be override accordingly.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:391

bool isIndirectBranch() const

Description

Return true if this is an indirect branch, such as a branch through a register.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:308

bool isInsertSubregLike() const

Description

Return true if this instruction behaves the same way as the generic INSERT_SUBREG instructions. E.g., on ARM, dX = VSETLNi32 dY, rZ, Imm is equivalent to a INSERT_SUBREG: dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm) Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getInsertSubregLikeInputs has to be override accordingly.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:405

bool isMetaInstruction() const

Description

Return true if this is a meta instruction that doesn't produce any output in the form of executable instructions.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:270

bool isMoveImmediate() const

Description

Return true if this instruction is a move immediate (including conditional moves) instruction.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:342

bool isMoveReg() const

Description

Return true if the instruction is a register to register move.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:282

bool isNotDuplicable() const

Description

Return true if this instruction cannot be safely duplicated. For example, if the instruction has a unique labels attached to it, duplicating it would cause multiple definition errors.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:353

bool isPreISelOpcode() const

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:252

Returns

true if this instruction is emitted before instruction selection and should be legalized/regbankselected/selected.

bool isPredicable() const

Description

Return true if this instruction has a predicate operand that controls execution. It may be set to 'always', or may be set to other values. There are various methods in TargetInstrInfo that can be used to control and modify the predicate in this instruction.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:335

bool isPseudo() const

Description

Return true if this is a pseudo instruction that doesn't correspond to a real machine instruction.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:266

bool isRegSequenceLike() const

Description

Return true if this instruction behaves the same way as the generic REG_SEQUENCE instructions. E.g., on ARM, dX VMOVDRR rY, rZ is equivalent to dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1. Note that for the optimizers to be able to take advantage of this property, TargetInstrInfo::getRegSequenceLikeInputs has to be override accordingly.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:378

bool isRematerializable() const

Description

Returns true if this instruction is a candidate for remat. This flag is only used in TargetInstrInfo method isTriviallyRematerializable. If this flag is set, the isReallyTriviallyReMaterializable() or isReallyTriviallyReMaterializableGeneric methods are called to verify the instruction is really rematable.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:522

bool isReturn() const

Description

Return true if the instruction is a return.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:273

bool isSelect() const

Description

Return true if this is a select instruction.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:348

bool isTerminator() const

Description

Returns true if this instruction part of the terminator for a basic block. Typically this is things like return and branch instructions. Various passes use this to insert code into the bottom of a basic block, but before control flow occurs.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:298

bool isTrap() const

Description

Return true if this instruction is a trap.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:279

bool isUnconditionalBranch() const

Description

Return true if this is a branch which always transfers control flow to some other block. The TargetInstrInfo::analyzeBranch method can be used to get more information about this branch.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:322

bool isVariadic() const

Description

Return true if this instruction can have a variable number of operands. In this case, the variable operands will be after the normal operands but before the implicit definitions and uses (if any are present).

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:258

bool mayAffectControlFlow(
    const llvm::MCInst& MI,
    const llvm::MCRegisterInfo& RI) const

Description

Return true if this is a branch or an instruction which directly writes to the program counter. Considered 'may' affect rather than 'does' affect as things like predication are not taken into account.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:329

Parameters

const llvm::MCInst& MI
const llvm::MCRegisterInfo& RI

bool mayLoad() const

Description

Return true if this instruction could possibly read memory. Instructions with this flag set are not necessarily simple load instructions, they may load a value and modify it, for example.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:435

bool mayRaiseFPException() const

Description

Return true if this instruction may raise a floating-point exception.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:444

bool mayStore() const

Description

Return true if this instruction could possibly modify memory. Instructions with this flag set are not necessarily simple store instructions, they may store a modified value based on their operands, or may not actually modify anything, for example.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:441

llvm::MCInstrDesc::const_opInfo_iterator
opInfo_begin() const

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:234

llvm::MCInstrDesc::const_opInfo_iterator
opInfo_end() const

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:235

iterator_range<
    llvm::MCInstrDesc::const_opInfo_iterator>
operands() const

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:237

bool usesCustomInsertionHook() const

Description

Return true if this instruction requires custom insertion support when the DAG scheduler is inserting it into a machine basic block. If this is true for the instruction, it basically means that it is a pseudo instruction used at SelectionDAG time that is expanded out into magic code by the target when MachineInstrs are formed. If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method is used to insert this into the MachineBasicBlock.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:506

bool variadicOpsAreDefs() const

Description

Return true if variadic operands of this instruction are definitions.

Declared at: llvm/include/llvm/MC/MCInstrDesc.h:415