struct X86GenMCSubtargetInfo

Declaration

struct X86GenMCSubtargetInfo : public MCSubtargetInfo { /* full declaration omitted */ };

Description

Generic base class for all target subtargets.

Declared at: build/lib/Target/X86/X86GenSubtargetInfo.inc:31184

Inherits from: MCSubtargetInfo

Member Variables

Method Overview

• public X86GenMCSubtargetInfo(const llvm::Triple & TT, llvm::StringRef CPU, llvm::StringRef TuneCPU, llvm::StringRef FS, ArrayRef<llvm::SubtargetFeatureKV> PF, ArrayRef<llvm::SubtargetSubTypeKV> PD, const llvm::MCWriteProcResEntry * WPR, const llvm::MCWriteLatencyEntry * WL, const llvm::MCReadAdvanceEntry * RA, const llvm::InstrStage * IS, const unsigned int * OC, const unsigned int * FP)
• public unsigned int resolveVariantSchedClass(unsigned int SchedClass, const llvm::MCInst * MI, const llvm::MCInstrInfo * MCII, unsigned int CPUID) const

Inherited from MCSubtargetInfo:

• public ApplyFeatureFlag
• public ClearFeatureBitsTransitively
• protected InitMCProcessorInfo
• public SetFeatureBitsTransitively
• public ToggleFeature
• public ToggleFeature
• public ToggleFeature
• public checkFeatures
• public enableWritePrefetching
• public getCPU
• public getCacheAssociativity
• public getCacheLineSize
• public getCacheLineSize
• public getCacheSize
• public getFeatureBits
• public getFeatureString
• public getHwMode
• public getInstrItineraryForCPU
• public getMaxPrefetchIterationsAhead
• public getMinPrefetchStride
• public getPrefetchDistance
• public getReadAdvanceCycles
• public getReadAdvanceEntries
• public getSchedModel
• public getSchedModelForCPU
• public getTargetTriple
• public getTuneCPU
• public getWriteLatencyEntry
• public getWriteProcResBegin
• public getWriteProcResEnd
• public hasFeature
• public initInstrItins
• public isCPUStringValid
• public resolveVariantSchedClass
• public setDefaultFeatures
• public setFeatureBits

Methods

¶X86GenMCSubtargetInfo(
    const llvm::Triple& TT,
    llvm::StringRef CPU,
    llvm::StringRef TuneCPU,
    llvm::StringRef FS,
    ArrayRef<llvm::SubtargetFeatureKV> PF,
    ArrayRef<llvm::SubtargetSubTypeKV> PD,
    const llvm::MCWriteProcResEntry* WPR,
    const llvm::MCWriteLatencyEntry* WL,
    const llvm::MCReadAdvanceEntry* RA,
    const llvm::InstrStage* IS,
    const unsigned int* OC,
    const unsigned int* FP)

Declared at: build/lib/Target/X86/X86GenSubtargetInfo.inc:31185

Parameters

const llvm::Triple& TT

llvm::StringRef CPU

llvm::StringRef TuneCPU

llvm::StringRef FS

ArrayRef<llvm::SubtargetFeatureKV> PF

ArrayRef<llvm::SubtargetSubTypeKV> PD

const llvm::MCWriteProcResEntry* WPR

const llvm::MCWriteLatencyEntry* WL

const llvm::MCReadAdvanceEntry* RA

const llvm::InstrStage* IS

const unsigned int* OC

const unsigned int* FP

¶unsigned int resolveVariantSchedClass(
    unsigned int SchedClass,
    const llvm::MCInst* MI,
    const llvm::MCInstrInfo* MCII,
    unsigned int CPUID) const

Description

Resolve a variant scheduling class for the given MCInst and CPU.

Declared at: build/lib/Target/X86/X86GenSubtargetInfo.inc:31196

Parameters

unsigned int SchedClass

const llvm::MCInst* MI

const llvm::MCInstrInfo* MCII

unsigned int CPUID