ΒΆllvm::ScheduleDAGSDNodes* createVLIWDAGScheduler(
llvm::SelectionDAGISel* IS,
CodeGenOpt::Level OptLevel)
llvm::ScheduleDAGSDNodes* createVLIWDAGScheduler(
llvm::SelectionDAGISel* IS,
CodeGenOpt::Level OptLevel)
Description
createVLIWDAGScheduler - Scheduler for VLIW targets. This creates top down DFA driven list scheduler with clustering heuristic to control register pressure.
Declared at: llvm/include/llvm/CodeGen/SchedulerRegistry.h:93
Parameters
- llvm::SelectionDAGISel* IS
- CodeGenOpt::Level OptLevel