class ScheduleDAGMI

Declaration

class ScheduleDAGMI : public ScheduleDAGInstrs { /* full declaration omitted */ };

Description

ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions according to the given MachineSchedStrategy without much extra book-keeping. This is the common functionality between PreRA and PostRA MachineScheduler.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:273

Inherits from: ScheduleDAGInstrs

Member Variables

protected llvm::AAResults* AA
protected llvm::LiveIntervals* LIS
protected std::unique_ptr<MachineSchedStrategy> SchedImpl
protected std::vector<std::unique_ptr<ScheduleDAGMutation>> Mutations
Ordered list of DAG postprocessing steps.
protected MachineBasicBlock::iterator CurrentTop
The top of the unscheduled zone.
protected MachineBasicBlock::iterator CurrentBottom
The bottom of the unscheduled zone.
protected const llvm::SUnit* NextClusterPred = nullptr
Record the next node in a scheduled cluster.
protected const llvm::SUnit* NextClusterSucc = nullptr

Inherited from ScheduleDAGInstrs:

protected MLI
protected MFI
protected SchedModel
protected RemoveKillFlags
protected CanHandleTerminators = false
protected TrackLaneMasks = false
protected BB
protected RegionBegin
protected RegionEnd
protected NumRegionInstrs
protected MISUnitMap
protected Defs
protected Uses
protected CurrentVRegDefs
protected CurrentVRegUses
protected AAForDep = nullptr
protected BarrierChain = nullptr
protected UnknownValue
protected Topo
protected DbgValues
protected FirstDbgValue = nullptr
protected LiveRegs

Inherited from ScheduleDAG:

public TM
public TII
public TRI
public MF
public MRI
public SUnits
public EntrySU
public ExitSU
public StressSched

Method Overview

Inherited from ScheduleDAGInstrs:

Inherited from ScheduleDAG:

Methods

ScheduleDAGMI(
    llvm::MachineSchedContext* C,
    std::unique_ptr<MachineSchedStrategy> S,
    bool RemoveKillFlags)

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:299

Parameters

llvm::MachineSchedContext* C
std::unique_ptr<MachineSchedStrategy> S
bool RemoveKillFlags

void addMutation(
    std::unique_ptr<ScheduleDAGMutation> Mutation)

Description

Add a postprocessing step to the DAG builder. Mutations are applied in the order that they are added after normal DAG building and before MachineSchedStrategy initialization. ScheduleDAGMI takes ownership of the Mutation object.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:325

Parameters

std::unique_ptr<ScheduleDAGMutation> Mutation

MachineBasicBlock::iterator bottom() const

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:331

bool checkSchedLimit()

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:379

bool doMBBSchedRegionsTopDown() const

Description

If this method returns true, handling of the scheduling regions themselves (in case of a scheduling boundary in MBB) will be done beginning with the topmost region of MBB.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:310

void dumpSchedule() const

Description

dump the scheduled Sequence.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:376

void enterRegion(
    llvm::MachineBasicBlock* bb,
    MachineBasicBlock::iterator begin,
    MachineBasicBlock::iterator end,
    unsigned int regioninstrs)

Description

Implement the ScheduleDAGInstrs interface for handling the next scheduling region. This covers all instructions in a block, while schedule() may only cover a subset.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:336

Parameters

llvm::MachineBasicBlock* bb
MachineBasicBlock::iterator begin
MachineBasicBlock::iterator end
unsigned int regioninstrs

void findRootsAndBiasEdges(
    SmallVectorImpl<llvm::SUnit*>& TopRoots,
    SmallVectorImpl<llvm::SUnit*>& BotRoots)

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:381

Parameters

SmallVectorImpl<llvm::SUnit*>& TopRoots
SmallVectorImpl<llvm::SUnit*>& BotRoots

void finishBlock()

Description

Cleans up after scheduling in the given block.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:346

llvm::LiveIntervals* getLIS() const

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:315

const llvm::SUnit* getNextClusterPred() const

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:352

const llvm::SUnit* getNextClusterSucc() const

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:354

virtual bool hasVRegLiveness() const

Description

Return true if this DAG supports VReg liveness and RegPressure.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:318

void initQueues(ArrayRef<llvm::SUnit*> TopRoots,
                ArrayRef<llvm::SUnit*> BotRoots)

Description

Release ExitSU predecessors and setup scheduler queues.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:367

Parameters

ArrayRef<llvm::SUnit*> TopRoots
ArrayRef<llvm::SUnit*> BotRoots

void moveInstruction(
    llvm::MachineInstr* MI,
    MachineBasicBlock::iterator InsertPos)

Description

Change the position of an instruction within the basic block and update live ranges and region boundary iterators.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:350

Parameters

llvm::MachineInstr* MI
MachineBasicBlock::iterator InsertPos

void placeDebugValues()

Description

Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:373

void postprocessDAG()

Description

Apply each ScheduleDAGMutation step in order. This allows different instances of ScheduleDAGMI to perform custom DAG postprocessing.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:364

void releasePred(llvm::SUnit* SU,
                 llvm::SDep* PredEdge)

Description

ReleasePred - Decrement the NumSuccsLeft count of a predecessor. When NumSuccsLeft reaches zero, release the predecessor node. FIXME: Adjust PredSU height based on MinLatency.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:386

Parameters

llvm::SUnit* SU
llvm::SDep* PredEdge

void releasePredecessors(llvm::SUnit* SU)

Description

releasePredecessors - Call releasePred on each of SU's predecessors.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:387

Parameters

llvm::SUnit* SU

void releaseSucc(llvm::SUnit* SU,
                 llvm::SDep* SuccEdge)

Description

ReleaseSucc - Decrement the NumPredsLeft count of a successor. When NumPredsLeft reaches zero, release the successor node. FIXME: Adjust SuccSU height based on MinLatency.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:384

Parameters

llvm::SUnit* SU
llvm::SDep* SuccEdge

void releaseSuccessors(llvm::SUnit* SU)

Description

releaseSuccessors - Call releaseSucc on each of SU's successors.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:385

Parameters

llvm::SUnit* SU

void schedule()

Description

Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:343

void startBlock(llvm::MachineBasicBlock* bb)

Description

Prepares to perform scheduling in the given block.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:345

Parameters

llvm::MachineBasicBlock* bb

MachineBasicBlock::iterator top() const

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:330

void updateQueues(llvm::SUnit* SU, bool IsTopNode)

Description

Update scheduler DAG and queues after scheduling an instruction.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:370

Parameters

llvm::SUnit* SU
bool IsTopNode

void viewGraph()

Description

Out-of-line implementation with no arguments is handy for gdb.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:357

void viewGraph(const llvm::Twine& Name,
               const llvm::Twine& Title)

Description

viewGraph - Pop up a ghostview window with the reachable parts of the DAG rendered using 'dot'.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:356

Parameters

const llvm::Twine& Name
const llvm::Twine& Title

~ScheduleDAGMI()

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:305