class TargetPassConfig

Declaration

class TargetPassConfig : public ImmutablePass { /* full declaration omitted */ };

Description

Target-Independent Code Generator Pass Configuration Options. This is an ImmutablePass solely for the purpose of exposing CodeGen options to the internals of other CodeGen passes.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:84

Inherits from: ImmutablePass

Member Variables

private llvm::legacy::PassManagerBase* PM = nullptr

private llvm::AnalysisID StartBefore = nullptr

private llvm::AnalysisID StartAfter = nullptr

private llvm::AnalysisID StopBefore = nullptr

private llvm::AnalysisID StopAfter = nullptr

private unsigned int StartBeforeInstanceNum = 0

private unsigned int StartBeforeCount = 0

private unsigned int StartAfterInstanceNum = 0

private unsigned int StartAfterCount = 0

private unsigned int StopBeforeInstanceNum = 0

private unsigned int StopBeforeCount = 0

private unsigned int StopAfterInstanceNum = 0

private unsigned int StopAfterCount = 0

private bool Started = true

private bool Stopped = false

private bool AddingMachinePasses = false

private bool DebugifyIsSafe = true

protected llvm::LLVMTargetMachine* TM

protected llvm::PassConfigImpl* Impl = nullptr

protected bool Initialized = false

protected bool DisableVerify = false

protected bool EnableTailMerge = true

Default setting for -enable-tail-merge on this target.

protected bool RequireCodeGenSCCOrder = false

Require processing of functions such that callees are generated before callers.

public static char ID

Method Overview

• public TargetPassConfig(llvm::LLVMTargetMachine & TM, llvm::legacy::PassManagerBase & pm)
• public TargetPassConfig()
• protected virtual void addBlockPlacement()
• public void addCheckDebugPass()
• public virtual void addCodeGenPrepare()
• protected bool addCoreISelPasses()
• public void addDebugifyPass()
• protected virtual void addFastRegAlloc()
• protected virtual bool addGCPasses()
• public virtual bool addGlobalInstructionSelect()
• protected virtual bool addILPOpts()
• public virtual void addIRPasses()
• public virtual bool addIRTranslator()
• public bool addISelPasses()
• public virtual void addISelPrepare()
• public virtual bool addInstSelector()
• public virtual bool addLegalizeMachineIR()
• protected virtual void addMachineLateOptimization()
• public virtual void addMachinePasses()
• public void addMachinePostPasses(const std::string & Banner)
• public void addMachinePrePasses(bool AllowDebugify = true)
• protected virtual void addMachineSSAOptimization()
• protected virtual void addOptimizedRegAlloc()
• protected void addPass(llvm::Pass * P)
• protected llvm::AnalysisID addPass(llvm::AnalysisID PassID)
• public void addPassesToHandleExceptions()
• protected virtual bool addPostFastRegAllocRewrite()
• protected virtual void addPostRegAlloc()
• protected virtual void addPostRewrite()
• protected virtual void addPreEmitPass()
• protected virtual void addPreEmitPass2()
• public virtual void addPreGlobalInstructionSelect()
• protected virtual bool addPreISel()
• public virtual void addPreLegalizeMachineIR()
• protected virtual void addPreRegAlloc()
• public virtual void addPreRegBankSelect()
• protected virtual bool addPreRewrite()
• protected virtual void addPreSched2()
• public void addPrintPass(const std::string & Banner)
• protected virtual bool addRegAssignAndRewriteFast()
• protected virtual bool addRegAssignAndRewriteOptimized()
• public virtual bool addRegBankSelect()
• public void addStripDebugPass()
• public void addVerifyPass(const std::string & Banner)
• public virtual llvm::ScheduleDAGInstrs * createMachineScheduler(llvm::MachineSchedContext * C) const
• public virtual llvm::ScheduleDAGInstrs * createPostMachineScheduler(llvm::MachineSchedContext * C) const
• protected virtual llvm::FunctionPass * createRegAllocPass(bool Optimized)
• protected virtual llvm::FunctionPass * createTargetRegisterAllocator(bool Optimized)
• public void disablePass(llvm::AnalysisID PassID)
• public void enablePass(llvm::AnalysisID PassID)
• public virtual std::unique_ptr<CSEConfigBase> getCSEConfig() const
• public bool getEnableTailMerge() const
• public static std::string getLimitedCodeGenPipelineReason(const char * Separator = "/")
• public CodeGenOpt::Level getOptLevel() const
• public bool getOptimizeRegAlloc() const
• public llvm::IdentifyingPassPtr getPassSubstitution(llvm::AnalysisID StandardID) const
• public template <typename TMC>TMC & getTM() const
• public static bool hasLimitedCodeGenPipeline()
• public void insertPass(llvm::AnalysisID TargetPassID, llvm::IdentifyingPassPtr InsertedPassID)
• protected bool isCustomizedRegAlloc()
• public virtual bool isGISelCSEEnabled() const
• public bool isGlobalISelAbortEnabled() const
• public bool isPassSubstitutedOrOverridden(llvm::AnalysisID ID) const
• public void printAndVerify(const std::string & Banner)
• public virtual bool reportDiagnosticWhenGlobalISelFallback() const
• public bool requiresCodeGenSCCOrder() const
• public void setDisableVerify(bool Disable)
• public void setEnableTailMerge(bool Enable)
• public void setInitialized()
• protected void setOpt(bool & Opt, bool Val)
• public void setRequiresCodeGenSCCOrder(bool Enable = true)
• private void setStartStopPasses()
• public void substitutePass(llvm::AnalysisID StandardID, llvm::IdentifyingPassPtr TargetID)
• public bool usingDefaultRegAlloc() const
• public static bool willCompleteCodeGenPipeline()
• public ~TargetPassConfig()

Inherited from ImmutablePass:

• public getAsImmutablePass
• public initializePass
• public runOnModule

Inherited from ModulePass:

• public assignPassManager
• public createPrinterPass
• public getPotentialPassManagerType
• public runOnModule
• protected skipModule

Inherited from Pass:

• public assignPassManager
• public createPass
• public createPrinterPass
• public doFinalization
• public doInitialization
• public dump
• public dumpPassStructure
• public getAdjustedAnalysisPointer
• public getAnalysis
• public getAnalysis
• public getAnalysisID
• public getAnalysisID
• public getAnalysisIfAvailable
• public getAnalysisUsage
• public getAsImmutablePass
• public getAsPMDataManager
• public getPassID
• public getPassKind
• public getPassName
• public getPotentialPassManagerType
• public getResolver
• public lookupPassInfo
• public lookupPassInfo
• public mustPreserveAnalysisID
• public preparePassManager
• public print
• public releaseMemory
• public setResolver
• public verifyAnalysis

Methods

¶TargetPassConfig(
    llvm::LLVMTargetMachine& TM,
    llvm::legacy::PassManagerBase& pm)

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:142

Parameters

llvm::LLVMTargetMachine& TM

llvm::legacy::PassManagerBase& pm

¶TargetPassConfig()

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:144

¶virtual void addBlockPlacement()

Description

Add standard basic block placement passes.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:435

¶void addCheckDebugPass()

Description

Add a pass to check synthesized debug info for MIR.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:317

¶virtual void addCodeGenPrepare()

Description

Add pass to prepare the LLVM IR for code generation. This should be done before exception handling preparation passes.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:231

¶bool addCoreISelPasses()

Description

Add the actual instruction selection passes. This does not include preparation passes on IR.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:139

¶void addDebugifyPass()

Description

Add a pass to add synthesized debug info to the MIR.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:311

¶virtual void addFastRegAlloc()

Description

addFastRegAlloc - Add the minimum set of target-independent passes that are required for fast register allocation.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:388

¶virtual bool addGCPasses()

Description

addGCPasses - Add late codegen passes that analyze code for garbage collection. This should return true if GC info should be printed after these passes.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:432

¶virtual bool addGlobalInstructionSelect()

Description

This method should install a (global) instruction selector pass, which converts possibly generic instructions to fully target-specific instructions, thereby constraining all generic virtual registers to register classes.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:272

¶virtual bool addILPOpts()

Description

Add passes that optimize instruction level parallelism for out-of-order targets. These passes are run while the machine code is still in SSA form, so they can use MachineTraceMetrics to control their heuristics. All passes added here should preserve the MachineDominatorTree, MachineLoopInfo, and MachineTraceMetrics analyses.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:374

¶virtual void addIRPasses()

Description

Add common target configurable passes that perform LLVM IR to IR transforms following machine independent optimization.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:224

¶virtual bool addIRTranslator()

Description

This method should install an IR translator pass, which converts from LLVM code to machine instructions with possibly generic opcodes.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:245

¶bool addISelPasses()

Description

High level function that adds all passes necessary to go from llvm IR representation to the MI representation. Adds IR based lowering and target specific optimization passes and finally the core instruction selection passes.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:220

Returns

true if an error occurred, false otherwise.

¶virtual void addISelPrepare()

Description

Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:235

¶virtual bool addInstSelector()

Description

addInstSelector - This method should install an instruction selector pass, which converts from LLVM code to machine instructions.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:239

¶virtual bool addLegalizeMachineIR()

Description

This method should install a legalize pass, which converts the instruction sequence into one that can be selected by the target.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:253

¶virtual void addMachineLateOptimization()

Description

Add passes that optimize machine instructions after register allocation.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:423

¶virtual void addMachinePasses()

Description

Add the complete, standard set of LLVM CodeGen passes. Fully developed targets will not generally override this.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:276

¶void addMachinePostPasses(
    const std::string& Banner)

Description

Add standard passes after a pass that has just been added. For example, the MachineVerifier if it is enabled.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:325

Parameters

const std::string& Banner

¶void addMachinePrePasses(
    bool AllowDebugify = true)

Description

Add standard passes before a pass that's about to be added. For example, the DebugifyMachineModulePass if it is enabled.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:321

Parameters

bool AllowDebugify = true

¶virtual void addMachineSSAOptimization()

Description

addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:366

¶virtual void addOptimizedRegAlloc()

Description

addOptimizedRegAlloc - Add passes related to register allocation. LLVMTargetMachine provides standard regalloc passes for most targets.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:392

¶void addPass(llvm::Pass* P)

Description

Add a pass to the PassManager if that pass is supposed to be run, as determined by the StartAfter and StopAfter options. Takes ownership of the pass.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:458

Parameters

llvm::Pass* P

¶llvm::AnalysisID addPass(llvm::AnalysisID PassID)

Description

Add a CodeGen pass at this point in the pipeline after checking overrides. Return the pass that was added, or zero if no pass was added.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:453

Parameters

llvm::AnalysisID PassID

¶void addPassesToHandleExceptions()

Description

Add passes to lower exception handling for the code generator.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:227

¶virtual bool addPostFastRegAllocRewrite()

Description

addPostFastRegAllocRewrite - Add passes to the optimized register allocation pipeline after fast register allocation is complete.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:412

¶virtual void addPostRegAlloc()

Description

This method may be implemented by targets that want to run passes after register allocation pass pipeline but before prolog-epilog insertion.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:420

¶virtual void addPostRewrite()

Description

Add passes to be run immediately after virtual registers are rewritten to physical registers.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:416

¶virtual void addPreEmitPass()

Description

This pass may be implemented by targets that want to run passes immediately before machine code is emitted.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:439

¶virtual void addPreEmitPass2()

Description

Targets may add passes immediately before machine code is emitted in this callback. This is called even later than `addPreEmitPass`.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:446

¶virtual void addPreGlobalInstructionSelect()

Description

This method may be implemented by targets that want to run passes immediately before the (global) instruction selection.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:266

¶virtual bool addPreISel()

Description

addPreISelPasses - This method should add any "last minute" LLVM->LLVM passes (which are run just before instruction selector).

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:360

¶virtual void addPreLegalizeMachineIR()

Description

This method may be implemented by targets that want to run passes immediately before legalization.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:249

¶virtual void addPreRegAlloc()

Description

This method may be implemented by targets that want to run passes immediately before register allocation.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:380

¶virtual void addPreRegBankSelect()

Description

This method may be implemented by targets that want to run passes immediately before the register bank selection.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:257

¶virtual bool addPreRewrite()

Description

addPreRewrite - Add passes to the optimized register allocation pipeline after register allocation is complete, but before virtual registers are rewritten to physical registers. These passes must preserve VirtRegMap and LiveIntervals, and when running after RABasic or RAGreedy, they should take advantage of LiveRegMatrix. When these passes run, VirtRegMap contains legal physreg assignments for all virtual registers. Note if the target overloads addRegAssignAndRewriteOptimized, this may not be honored. This is also not generally used for the the fast variant, where the allocation and rewriting are done in one pass.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:406

¶virtual void addPreSched2()

Description

This method may be implemented by targets that want to run passes after prolog-epilog insertion and before the second instruction scheduling pass.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:427

¶void addPrintPass(const std::string& Banner)

Description

Add a pass to print the machine function if printing is enabled.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:304

Parameters

const std::string& Banner

¶virtual bool addRegAssignAndRewriteFast()

Description

Add core register allocator passes which do the actual register assignment and rewriting.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:466

Returns

true if any passes were added.

¶virtual bool addRegAssignAndRewriteOptimized()

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:467

¶virtual bool addRegBankSelect()

Description

This method should install a register bank selector pass, which assigns register banks to virtual registers without a register class or register banks.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:262

¶void addStripDebugPass()

Description

Add a pass to remove debug info from the MIR.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:314

¶void addVerifyPass(const std::string& Banner)

Description

Add a pass to perform basic verification of the machine function if verification is enabled.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:308

Parameters

const std::string& Banner

¶virtual llvm::ScheduleDAGInstrs*
createMachineScheduler(
    llvm::MachineSchedContext* C) const

Description

Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this function and target at the current optimization level. This can also be used to plug a new MachineSchedStrategy into an instance of the standard ScheduleDAGMI: return new ScheduleDAGMI(C, std::make_unique <MyStrategy >(C), /*RemoveKillFlags=*/false) Return NULL to select the default (generic) machine scheduler.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:288

Parameters

llvm::MachineSchedContext* C

¶virtual llvm::ScheduleDAGInstrs*
createPostMachineScheduler(
    llvm::MachineSchedContext* C) const

Description

Similar to createMachineScheduler but used when postRA machine scheduling is enabled.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:295

Parameters

llvm::MachineSchedContext* C

¶virtual llvm::FunctionPass* createRegAllocPass(
    bool Optimized)

Description

addMachinePasses helper to create the target-selected or overriden regalloc pass.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:462

Parameters

bool Optimized

¶virtual llvm::FunctionPass*
createTargetRegisterAllocator(bool Optimized)

Description

createTargetRegisterAllocator - Create the register allocator pass for this target at the current optimization level.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:384

Parameters

bool Optimized

¶void disablePass(llvm::AnalysisID PassID)

Description

Allow the target to disable a specific standard pass by default.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:196

Parameters

llvm::AnalysisID PassID

¶void enablePass(llvm::AnalysisID PassID)

Description

Allow the target to enable a specific standard pass by default.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:193

Parameters

llvm::AnalysisID PassID

¶virtual std::unique_ptr<CSEConfigBase>
getCSEConfig() const

Description

Returns the CSEConfig object to use for the current optimization level.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:342

¶bool getEnableTailMerge() const

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:176

¶static std::string
getLimitedCodeGenPipelineReason(
    const char* Separator = "/")

Description

If hasLimitedCodeGenPipeline is true, this method returns a string with the name of the options, separated by \p Separator that caused this pipeline to be limited.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:172

Parameters

const char* Separator = "/"

¶CodeGenOpt::Level getOptLevel() const

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:158

¶bool getOptimizeRegAlloc() const

Description

Return true if the optimized regalloc pipeline is enabled.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:209

¶llvm::IdentifyingPassPtr getPassSubstitution(
    llvm::AnalysisID StandardID) const

Description

Return the pass substituted for StandardID by the target. If no substitution exists, return StandardID.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:202

Parameters

llvm::AnalysisID StandardID

¶template <typename TMC>
TMC& getTM() const

Description

Get the right type of TargetMachine for this target.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:151

Templates

TMC

¶static bool hasLimitedCodeGenPipeline()

Description

Returns true if one of the `-start-after`, `-start-before`, `-stop-after` or `-stop-before` options is set.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:162

¶void insertPass(
    llvm::AnalysisID TargetPassID,
    llvm::IdentifyingPassPtr InsertedPassID)

Description

Insert InsertedPassID pass after TargetPassID pass.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:190

Parameters

llvm::AnalysisID TargetPassID

llvm::IdentifyingPassPtr InsertedPassID

¶bool isCustomizedRegAlloc()

Description

Return true if register allocator is specified by -regalloc=override.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:349

¶virtual bool isGISelCSEEnabled() const

Description

Check whether continuous CSE should be enabled in GISel passes. By default, it's enabled for non O0 levels.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:339

¶bool isGlobalISelAbortEnabled() const

Description

Check whether or not GlobalISel should abort on error. When this is disabled, GlobalISel will fall back on SDISel instead of erroring out.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:330

¶bool isPassSubstitutedOrOverridden(
    llvm::AnalysisID ID) const

Description

Return true if the pass has been substituted by the target or overridden on the command line.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:206

Parameters

llvm::AnalysisID ID

¶void printAndVerify(const std::string& Banner)

Description

printAndVerify - Add a pass to dump then verify the machine function, if those steps are enabled.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:301

Parameters

const std::string& Banner

¶virtual bool
reportDiagnosticWhenGlobalISelFallback() const

Description

Check whether or not a diagnostic should be emitted when GlobalISel uses the fallback path. In other words, it will emit a diagnostic when GlobalISel failed and isGlobalISelAbortEnabled is false.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:335

¶bool requiresCodeGenSCCOrder() const

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:179

¶void setDisableVerify(bool Disable)

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:174

Parameters

bool Disable

¶void setEnableTailMerge(bool Enable)

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:177

Parameters

bool Enable

¶void setInitialized()

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:156

¶void setOpt(bool& Opt, bool Val)

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:346

Parameters

bool& Opt

bool Val

¶void setRequiresCodeGenSCCOrder(
    bool Enable = true)

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:180

Parameters

bool Enable = true

¶void setStartStopPasses()

Description

Set the StartAfter, StartBefore and StopAfter passes to allow running only a portion of the normal code-gen pass sequence. If the StartAfter and StartBefore pass ID is zero, then compilation will begin at the normal point; otherwise, clear the Started flag to indicate that passes should not be added until the starting pass is seen. If the Stop pass ID is zero, then compilation will continue to the end. This function expects that at least one of the StartAfter or the StartBefore pass IDs is null.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:119

¶void substitutePass(
    llvm::AnalysisID StandardID,
    llvm::IdentifyingPassPtr TargetID)

Description

Allow the target to override a specific pass without overriding the pass pipeline. When passes are added to the standard pipeline at the point where StandardID is expected, add TargetID in its place.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:187

Parameters

llvm::AnalysisID StandardID

llvm::IdentifyingPassPtr TargetID

¶bool usingDefaultRegAlloc() const

Description

Return true if the default global register allocator is in use and has not be overriden on the command line with '-regalloc=...'

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:213

¶static bool willCompleteCodeGenPipeline()

Description

Returns true if none of the `-stop-before` and `-stop-after` options is set.

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:166

¶~TargetPassConfig()

Declared at: llvm/include/llvm/CodeGen/TargetPassConfig.h:146