class LLVMTargetMachine

Declaration

class LLVMTargetMachine : public TargetMachine { /* full declaration omitted */ };

Description

This class describes a target machine that is implemented with the LLVM target-independent code generator.

Declared at: llvm/include/llvm/Target/TargetMachine.h:414

Inherits from: TargetMachine

Member Variables

Inherited from TargetMachine:

protected TheTarget

protected DL

protected TargetTriple

protected TargetCPU

protected TargetFS

protected RM = Reloc::Static

protected CMModel = CodeModel::Small

protected OptLevel = CodeGenOpt::Default

protected AsmInfo

protected MRI

protected MII

protected STI

protected RequireStructuredCFG

protected O0WantsFastISel

protected PGOOption = None

public DefaultOptions

public Options

public static DefaultSjLjDataSize = 32

Method Overview

• protected LLVMTargetMachine(const llvm::Target & T, llvm::StringRef DataLayoutString, const llvm::Triple & TT, llvm::StringRef CPU, llvm::StringRef FS, const llvm::TargetOptions & Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL)
• public bool addAsmPrinter(llvm::legacy::PassManagerBase & PM, llvm::raw_pwrite_stream & Out, llvm::raw_pwrite_stream * DwoOut, llvm::CodeGenFileType FileType, llvm::MCContext & Context)
• public bool addPassesToEmitFile(llvm::legacy::PassManagerBase & PM, llvm::raw_pwrite_stream & Out, llvm::raw_pwrite_stream * DwoOut, llvm::CodeGenFileType FileType, bool DisableVerify = true, llvm::MachineModuleInfoWrapperPass * MMIWP = nullptr)
• public bool addPassesToEmitMC(llvm::legacy::PassManagerBase & PM, llvm::MCContext *& Ctx, llvm::raw_pwrite_stream & Out, bool DisableVerify = true)
• public virtual llvm::Error buildCodeGenPipeline(llvm::ModulePassManager &, llvm::MachineFunctionPassManager &, llvm::MachineFunctionAnalysisManager &, llvm::raw_pwrite_stream &, llvm::raw_pwrite_stream *, llvm::CodeGenFileType, llvm::CGPassBuilderOption, llvm::PassInstrumentationCallbacks *)
• public Expected<std::unique_ptr<MCStreamer>> createMCStreamer(llvm::raw_pwrite_stream & Out, llvm::raw_pwrite_stream * DwoOut, llvm::CodeGenFileType FileType, llvm::MCContext & Ctx)
• public virtual llvm::TargetPassConfig * createPassConfig(llvm::legacy::PassManagerBase & PM)
• public virtual std::pair<StringRef, bool> getPassNameFromLegacyName(llvm::StringRef)
• public llvm::TargetTransformInfo getTargetTransformInfo(const llvm::Function & F) const
• protected void initAsmInfo()
• public virtual bool isMachineVerifierClean() const
• public virtual int unqualifiedInlineAsmVariant() const
• public virtual bool useIPRA() const
• public virtual bool usesPhysRegsForValues() const

Inherited from TargetMachine:

• public addPassesToEmitFile
• public addPassesToEmitMC
• public adjustPassManager
• public convertFuncInfoToYAML
• public createDataLayout
• public createDefaultFuncInfoYAML
• public getAIXExtendedAltivecABI
• public getAddressSpaceForPseudoSourceKind
• public getAllocaPointerSize
• public getAssumedAddrSpace
• public getBBSectionsFuncListBuf
• public getBBSectionsType
• public getCodeModel
• public getDataSections
• public getFunctionSections
• public getIgnoreXCOFFVisibility
• public getIntrinsicInfo
• public getMCAsmInfo
• public getMCInstrInfo
• public getMCRegisterInfo
• public getMCSubtargetInfo
• public getNameWithPrefix
• public getO0WantsFastISel
• public getObjFileLowering
• public getOptLevel
• public getPGOOption
• public getPointerSize
• public getPointerSizeInBits
• public getPredicatedAddrSpace
• public getProgramPointerSize
• public getRelocationModel
• public getSjLjDataSize
• public getSubtarget
• public getSubtargetImpl
• public getSymbol
• public getTLSModel
• public getTarget
• public getTargetCPU
• public getTargetFeatureString
• public getTargetIRAnalysis
• public getTargetTransformInfo
• public getTargetTriple
• public getUniqueBasicBlockSectionNames
• public getUniqueSectionNames
• public getXCOFFTracebackTable
• public isCompatibleDataLayout
• public isNoopAddrSpaceCast
• public isPositionIndependent
• public parseBinutilsVersion
• public parseMachineFunctionInfo
• public registerDefaultAliasAnalyses
• public registerPassBuilderCallbacks
• public requiresStructuredCFG
• public resetTargetOptions
• public setCFIFixup
• public setCodeModel
• public setFastISel
• public setGlobalISel
• public setGlobalISelAbort
• public setMachineOutliner
• public setO0WantsFastISel
• public setOptLevel
• public setPGOOption
• public setRequiresStructuredCFG
• public setSupportsDebugEntryValues
• public setSupportsDefaultOutlining
• public setTargetFeatureString
• public shouldAssumeDSOLocal
• public targetSchedulesPostRAScheduling
• public useEmulatedTLS

Methods

¶LLVMTargetMachine(
    const llvm::Target& T,
    llvm::StringRef DataLayoutString,
    const llvm::Triple& TT,
    llvm::StringRef CPU,
    llvm::StringRef FS,
    const llvm::TargetOptions& Options,
    Reloc::Model RM,
    CodeModel::Model CM,
    CodeGenOpt::Level OL)

Declared at: llvm/include/llvm/Target/TargetMachine.h:416

Parameters

const llvm::Target& T

llvm::StringRef DataLayoutString

const llvm::Triple& TT

llvm::StringRef CPU

llvm::StringRef FS

const llvm::TargetOptions& Options

Reloc::Model RM

CodeModel::Model CM

CodeGenOpt::Level OL

¶bool addAsmPrinter(
    llvm::legacy::PassManagerBase& PM,
    llvm::raw_pwrite_stream& Out,
    llvm::raw_pwrite_stream* DwoOut,
    llvm::CodeGenFileType FileType,
    llvm::MCContext& Context)

Description

Adds an AsmPrinter pass to the pipeline that prints assembly or machine code from the MI representation.

Declared at: llvm/include/llvm/Target/TargetMachine.h:475

Parameters

llvm::legacy::PassManagerBase& PM

llvm::raw_pwrite_stream& Out

llvm::raw_pwrite_stream* DwoOut

llvm::CodeGenFileType FileType

llvm::MCContext& Context

¶bool addPassesToEmitFile(
    llvm::legacy::PassManagerBase& PM,
    llvm::raw_pwrite_stream& Out,
    llvm::raw_pwrite_stream* DwoOut,
    llvm::CodeGenFileType FileType,
    bool DisableVerify = true,
    llvm::MachineModuleInfoWrapperPass* MMIWP =
        nullptr)

Description

Add passes to the specified pass manager to get the specified file emitted. Typically this will involve several steps of code generation.\p MMIWP is an optional parameter that, if set to non-nullptr, will be used to set the MachineModuloInfo for this PM.

Declared at: llvm/include/llvm/Target/TargetMachine.h:439

Parameters

llvm::legacy::PassManagerBase& PM

llvm::raw_pwrite_stream& Out

llvm::raw_pwrite_stream* DwoOut

llvm::CodeGenFileType FileType

bool DisableVerify = true

llvm::MachineModuleInfoWrapperPass* MMIWP = nullptr

¶bool addPassesToEmitMC(
    llvm::legacy::PassManagerBase& PM,
    llvm::MCContext*& Ctx,
    llvm::raw_pwrite_stream& Out,
    bool DisableVerify = true)

Description

Add passes to the specified pass manager to get machine code emitted with the MCJIT. This method returns true if machine code is not supported. It fills the MCContext Ctx pointer which can be used to build custom MCStreamer.

Declared at: llvm/include/llvm/Target/TargetMachine.h:463

Parameters

llvm::legacy::PassManagerBase& PM

llvm::MCContext*& Ctx

llvm::raw_pwrite_stream& Out

bool DisableVerify = true

¶virtual llvm::Error buildCodeGenPipeline(
    llvm::ModulePassManager&,
    llvm::MachineFunctionPassManager&,
    llvm::MachineFunctionAnalysisManager&,
    llvm::raw_pwrite_stream&,
    llvm::raw_pwrite_stream*,
    llvm::CodeGenFileType,
    llvm::CGPassBuilderOption,
    llvm::PassInstrumentationCallbacks*)

Declared at: llvm/include/llvm/Target/TargetMachine.h:444

Parameters

llvm::ModulePassManager&

llvm::MachineFunctionPassManager&

llvm::MachineFunctionAnalysisManager&

llvm::raw_pwrite_stream&

llvm::raw_pwrite_stream*

llvm::CodeGenFileType

llvm::CGPassBuilderOption

llvm::PassInstrumentationCallbacks*

¶Expected<std::unique_ptr<MCStreamer>>
createMCStreamer(llvm::raw_pwrite_stream& Out,
                 llvm::raw_pwrite_stream* DwoOut,
                 llvm::CodeGenFileType FileType,
                 llvm::MCContext& Ctx)

Declared at: llvm/include/llvm/Target/TargetMachine.h:480

Parameters

llvm::raw_pwrite_stream& Out

llvm::raw_pwrite_stream* DwoOut

llvm::CodeGenFileType FileType

llvm::MCContext& Ctx

¶virtual llvm::TargetPassConfig* createPassConfig(
    llvm::legacy::PassManagerBase& PM)

Description

Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of CodeGen passes.

Declared at: llvm/include/llvm/Target/TargetMachine.h:432

Parameters

llvm::legacy::PassManagerBase& PM

¶virtual std::pair<StringRef, bool>
getPassNameFromLegacyName(llvm::StringRef)

Declared at: llvm/include/llvm/Target/TargetMachine.h:454

Parameters

llvm::StringRef

¶llvm::TargetTransformInfo getTargetTransformInfo(
    const llvm::Function& F) const

Description

Get a TargetTransformInfo implementation for the target. The TTI returned uses the common code generator to answer queries about the IR.

Declared at: llvm/include/llvm/Target/TargetMachine.h:428

Parameters

const llvm::Function& F

¶void initAsmInfo()

Declared at: llvm/include/llvm/Target/TargetMachine.h:421

¶virtual bool isMachineVerifierClean() const

Description

Returns true if the target is expected to pass all machine verifier checks. This is a stopgap measure to fix targets one by one. We will remove this at some point and always enable the verifier when EXPENSIVE_CHECKS is enabled.

Declared at: llvm/include/llvm/Target/TargetMachine.h:471

¶virtual int unqualifiedInlineAsmVariant() const

Description

The default variant to use in unqualified `asm` instructions. If this returns 0, `asm "$(foo$|bar$)"` will evaluate to `asm "foo"`.

Declared at: llvm/include/llvm/Target/TargetMachine.h:499

¶virtual bool useIPRA() const

Description

True if the target wants to use interprocedural register allocation by default. The -enable-ipra flag can be used to override this.

Declared at: llvm/include/llvm/Target/TargetMachine.h:493

¶virtual bool usesPhysRegsForValues() const

Description

True if the target uses physical regs (as nearly all targets do). False for stack machines such as WebAssembly and other virtual-register machines. If true, all vregs must be allocated before PEI. If false, then callee-save register spilling and scavenging are not needed or used. If false, implicitly defined registers will still be assumed to be physical registers, except that variadic defs will be allocated vregs.

Declared at: llvm/include/llvm/Target/TargetMachine.h:489