class X86MCInstrAnalysis

Declaration

class X86MCInstrAnalysis : public MCInstrAnalysis { /* full declaration omitted */ };

Declared at: llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp:488

Inherits from: MCInstrAnalysis

Member Variables

Inherited from MCInstrAnalysis:

protected Info

Method Overview

  • private X86MCInstrAnalysis(const llvm::X86_MC::X86MCInstrAnalysis &)
  • public X86MCInstrAnalysis(const llvm::MCInstrInfo * MCII)
  • public bool clearsSuperRegisters(const llvm::MCRegisterInfo & MRI, const llvm::MCInst & Inst, llvm::APInt & Mask) const
  • public bool evaluateBranch(const llvm::MCInst & Inst, uint64_t Addr, uint64_t Size, uint64_t & Target) const
  • public Optional<uint64_t> evaluateMemoryOperandAddress(const llvm::MCInst & Inst, const llvm::MCSubtargetInfo * STI, uint64_t Addr, uint64_t Size) const
  • public std::vector<std::pair<uint64_t, uint64_t>> findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents, uint64_t GotSectionVA, const llvm::Triple & TargetTriple) const
  • public Optional<uint64_t> getMemoryOperandRelocationOffset(const llvm::MCInst & Inst, uint64_t Size) const
  • public bool isDependencyBreaking(const llvm::MCInst & MI, llvm::APInt & Mask, unsigned int ProcessorID) const
  • public bool isOptimizableRegisterMove(const llvm::MCInst & MI, unsigned int ProcessorID) const
  • public bool isZeroIdiom(const llvm::MCInst & MI, llvm::APInt & Mask, unsigned int ProcessorID) const
  • private virtual ~X86MCInstrAnalysis()

Inherited from MCInstrAnalysis:

Methods

X86MCInstrAnalysis(
    const llvm::X86_MC::X86MCInstrAnalysis&)

Declared at: llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp:489

Parameters

const llvm::X86_MC::X86MCInstrAnalysis& 

X86MCInstrAnalysis(const llvm::MCInstrInfo* MCII)

Declared at: llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp:494

Parameters

const llvm::MCInstrInfo* MCII

bool clearsSuperRegisters(
    const llvm::MCRegisterInfo& MRI,
    const llvm::MCInst& Inst,
    llvm::APInt& Mask) const

Description

Returns true if at least one of the register writes performed by Example: on X86-64, a write to EAX implicitly clears the upper half of RAX. Also (still on x86) an XMM write perfomed by an AVX 128-bit instruction implicitly clears the upper portion of the correspondent YMM register. This method also updates an APInt which is used as mask of register writes. There is one bit for every explicit/implicit write performed by the instruction. If a write implicitly clears its super-registers, then the corresponding bit is set (vic. the corresponding bit is cleared). The first bits in the APint are related to explicit writes. The remaining bits are related to implicit writes. The sequence of writes follows the machine operand sequence. For implicit writes, the sequence is defined by the MCInstrDesc. The assumption is that the bit-width of the APInt is correctly set by the caller. The default implementation conservatively assumes that none of the writes clears the upper portion of a super-register.

Declared at: llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp:499

Parameters

const llvm::MCRegisterInfo& MRI
const llvm::MCInst& Inst
implicitly clears the upper portion of all super-registers.
llvm::APInt& Mask

bool evaluateBranch(const llvm::MCInst& Inst,
                    uint64_t Addr,
                    uint64_t Size,
                    uint64_t& Target) const

Description

Given a branch instruction try to get the address the branch targets. Return true on success, and the address in Target.

Declared at: llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp:506

Parameters

const llvm::MCInst& Inst
uint64_t Addr
uint64_t Size
uint64_t& Target

Optional<uint64_t> evaluateMemoryOperandAddress(
    const llvm::MCInst& Inst,
    const llvm::MCSubtargetInfo* STI,
    uint64_t Addr,
    uint64_t Size) const

Description

Given an instruction tries to get the address of a memory operand. Returns the address on success.

Declared at: llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp:508

Parameters

const llvm::MCInst& Inst
const llvm::MCSubtargetInfo* STI
uint64_t Addr
uint64_t Size

std::vector<std::pair<uint64_t, uint64_t>>
findPltEntries(
    uint64_t PltSectionVA,
    ArrayRef<uint8_t> PltContents,
    uint64_t GotSectionVA,
    const llvm::Triple& TargetTriple) const

Description

Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.

Declared at: llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp:502

Parameters

uint64_t PltSectionVA
ArrayRef<uint8_t> PltContents
uint64_t GotSectionVA
const llvm::Triple& TargetTriple

Optional<uint64_t>
getMemoryOperandRelocationOffset(
    const llvm::MCInst& Inst,
    uint64_t Size) const

Description

Given an instruction with a memory operand that could require relocation, returns the offset within the instruction of that relocation.

Declared at: llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp:513

Parameters

const llvm::MCInst& Inst
uint64_t Size

bool isDependencyBreaking(
    const llvm::MCInst& MI,
    llvm::APInt& Mask,
    unsigned int ProcessorID) const

Description

Returns true if MI is a dependency breaking instruction for the subtarget associated with CPUID . The value computed by a dependency breaking instruction is not dependent on the inputs. An example of dependency breaking instruction on X86 is `XOR %eax, %eax`. If MI is a dependency breaking instruction for subtarget CPUID, then Mask can be inspected to identify independent operands. Essentially, each bit of the mask corresponds to an input operand. Explicit operands are laid out first in the mask; implicit operands follow explicit operands. Bits are set for operands that are independent. Note that the number of bits in Mask may not be equivalent to the sum of explicit and implicit operands in MI. Operands that don't have a corresponding bit in Mask are assumed "not independente". The only exception is for when Mask is all zeroes. That means: explicit input operands of MI are independent.

Declared at: build/lib/Target/X86/X86GenSubtargetInfo.inc:33799

Parameters

const llvm::MCInst& MI
llvm::APInt& Mask
unsigned int ProcessorID

bool isOptimizableRegisterMove(
    const llvm::MCInst& MI,
    unsigned int ProcessorID) const

Description

Returns true if MI is a candidate for move elimination. Different subtargets may apply different constraints to optimizable register moves. For example, on most X86 subtargets, a candidate for move elimination cannot specify the same register for both source and destination.

Declared at: build/lib/Target/X86/X86GenSubtargetInfo.inc:33800

Parameters

const llvm::MCInst& MI
unsigned int ProcessorID

bool isZeroIdiom(const llvm::MCInst& MI,
                 llvm::APInt& Mask,
                 unsigned int ProcessorID) const

Description

Returns true if MI is a dependency breaking zero-idiom for the given subtarget. Mask is used to identify input operands that have their dependency broken. Each bit of the mask is associated with a specific input operand. Bits associated with explicit input operands are laid out first in the mask; implicit operands come after explicit operands. Dependencies are broken only for operands that have their corresponding bit set. Operands that have their bit cleared, or that don't have a corresponding bit in the mask don't have their dependency broken. Note that Mask may not be big enough to describe all operands. The assumption for operands that don't have a correspondent bit in the mask is that those are still data dependent. The only exception to the rule is for when Mask has all zeroes. A zero mask means: dependencies are broken for all explicit register operands.

Declared at: build/lib/Target/X86/X86GenSubtargetInfo.inc:33798

Parameters

const llvm::MCInst& MI
llvm::APInt& Mask
unsigned int ProcessorID

virtual ~X86MCInstrAnalysis()

Declared at: llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp:491