class PostGenericScheduler

Declaration

class PostGenericScheduler : public GenericSchedulerBase { /* full declaration omitted */ };

Description

PostGenericScheduler - Interface to the scheduling algorithm used by ScheduleDAGMI. Callbacks from ScheduleDAGMI: initPolicy -> initialize(DAG) -> registerRoots -> pickNode ...

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:1036

Inherits from: GenericSchedulerBase

Member Variables

protected llvm::ScheduleDAGMI* DAG = nullptr
protected llvm::SchedBoundary Top
protected SmallVector<llvm::SUnit*, 8> BotRoots

Inherited from GenericSchedulerBase:

protected Context
protected SchedModel = nullptr
protected TRI = nullptr
protected Rem

Method Overview

Inherited from GenericSchedulerBase:

Inherited from MachineSchedStrategy:

Methods

PostGenericScheduler(
    const llvm::MachineSchedContext* C)

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:1043

Parameters

const llvm::MachineSchedContext* C

void initPolicy(MachineBasicBlock::iterator Begin,
                MachineBasicBlock::iterator End,
                unsigned int NumRegionInstrs)

Description

Optionally override the per-region scheduling policy.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:1048

Parameters

MachineBasicBlock::iterator Begin
MachineBasicBlock::iterator End
unsigned int NumRegionInstrs

void initialize(llvm::ScheduleDAGMI* Dag)

Description

Initialize the strategy after building the DAG for a new region.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:1057

Parameters

llvm::ScheduleDAGMI* Dag

llvm::SUnit* pickNode(bool& IsTopNode)

Description

Pick the next node to schedule.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:1061

Parameters

bool& IsTopNode

void pickNodeFromQueue(
    llvm::GenericSchedulerBase::SchedCandidate&
        Cand)

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:1083

Parameters

llvm::GenericSchedulerBase::SchedCandidate& Cand

void registerRoots()

Description

Notify this strategy that all roots have been released (including those that depend on EntrySU or ExitSU).

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:1059

void releaseBottomNode(llvm::SUnit* SU)

Description

When all successor dependencies have been resolved, free this node for bottom-up scheduling.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:1076

Parameters

llvm::SUnit* SU

void releaseTopNode(llvm::SUnit* SU)

Description

When all predecessor dependencies have been resolved, free this node for top-down scheduling.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:1069

Parameters

llvm::SUnit* SU

void schedNode(llvm::SUnit* SU, bool IsTopNode)

Description

Called after ScheduleDAGMI has scheduled an instruction and updated scheduled/remaining flags in the DAG nodes.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:1067

Parameters

llvm::SUnit* SU
bool IsTopNode

void scheduleTree(unsigned int SubtreeID)

Description

Scheduler callback to notify that a new subtree is scheduled.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:1063

Parameters

unsigned int SubtreeID

bool shouldTrackPressure() const

Description

PostRA scheduling does not track pressure.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:1055

virtual bool tryCandidate(
    llvm::GenericSchedulerBase::SchedCandidate&
        Cand,
    llvm::GenericSchedulerBase::SchedCandidate&
        TryCand)

Description

Apply a set of heuristics to a new candidate for PostRA scheduling.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:1081

Parameters

llvm::GenericSchedulerBase::SchedCandidate& Cand
provides the policy and current best candidate.
llvm::GenericSchedulerBase::SchedCandidate& TryCand
refers to the next SUnit candidate, otherwise uninitialized.

Returns

\c true if TryCand is better than Cand (Reason is NOT NoCand)

~PostGenericScheduler()

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:1046