class TargetTransformInfo

Declaration

class TargetTransformInfo { /* full declaration omitted */ };

Description

This pass provides access to the codegen interfaces that are needed for IR-level transformations.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:171

Member Variables

private std::unique_ptr<Concept> TTIImpl

Method Overview

public bool LSRWithInstrQueries() const
public TargetTransformInfo(llvm::TargetTransformInfo && Arg)
public template <typename T> TargetTransformInfo(T Impl)
public TargetTransformInfo(const llvm::DataLayout & DL)
public unsigned int adjustInliningThreshold(const llvm::CallBase * CB) const
public bool allowsMisalignedMemoryAccesses(llvm::LLVMContext & Context, unsigned int BitWidth, unsigned int AddressSpace = 0, llvm::Align Alignment = llvm::Align(1), bool * Fast = nullptr) const
public bool areInlineCompatible(const llvm::Function * Caller, const llvm::Function * Callee) const
public bool areTypesABICompatible(const llvm::Function * Caller, const llvm::Function * Callee, const ArrayRef<llvm::Type *> & Types) const
public bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned int AS) const
public bool canMacroFuseCmp() const
public bool canSaveCmp(llvm::Loop * L, llvm::BranchInst ** BI, llvm::ScalarEvolution * SE, llvm::LoopInfo * LI, llvm::DominatorTree * DT, llvm::AssumptionCache * AC, llvm::TargetLibraryInfo * LibInfo) const
public bool collectFlatAddressOperands(SmallVectorImpl<int> & OpIndexes, Intrinsic::ID IID) const
public llvm::PredicationStyle emitGetActiveLaneMask() const
public bool enableAggressiveInterleaving(bool LoopHasReductions) const
public bool enableInterleavedAccessVectorization() const
public bool enableMaskedInterleavedAccessVectorization() const
public llvm::TargetTransformInfo::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
public bool enableOrderedReductions() const
public bool enableScalableVectorization() const
public bool enableWritePrefetching() const
public bool forceScalarizeMaskedGather(llvm::VectorType * Type, llvm::Align Alignment) const
public bool forceScalarizeMaskedScatter(llvm::VectorType * Type, llvm::Align Alignment) const
public llvm::InstructionCost getAddressComputationCost(llvm::Type * Ty, llvm::ScalarEvolution * SE = nullptr, const llvm::SCEV * Ptr = nullptr) const
public llvm::InstructionCost getArithmeticInstrCost(unsigned int Opcode, llvm::Type * Ty, TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput, llvm::TargetTransformInfo::OperandValueKind Opd1Info = OK_AnyValue, llvm::TargetTransformInfo::OperandValueKind Opd2Info = OK_AnyValue, llvm::TargetTransformInfo::OperandValueProperties Opd1PropInfo = OP_None, llvm::TargetTransformInfo::OperandValueProperties Opd2PropInfo = OP_None, ArrayRef<const llvm::Value *> Args = llvm::ArrayRef<const llvm::Value *>(), const llvm::Instruction * CxtI = nullptr) const
public llvm::InstructionCost getArithmeticReductionCost(unsigned int Opcode, llvm::VectorType * Ty, Optional<llvm::FastMathFlags> FMF, TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput) const
public unsigned int getAssumedAddrSpace(const llvm::Value * V) const
public unsigned int getAtomicMemIntrinsicMaxElementSize() const
public llvm::InstructionCost getCFInstrCost(unsigned int Opcode, TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_SizeAndLatency, const llvm::Instruction * I = nullptr) const
public Optional<unsigned int> getCacheAssociativity(llvm::TargetTransformInfo::CacheLevel Level) const
public unsigned int getCacheLineSize() const
public Optional<unsigned int> getCacheSize(llvm::TargetTransformInfo::CacheLevel Level) const
public llvm::InstructionCost getCallInstrCost(llvm::Function * F, llvm::Type * RetTy, ArrayRef<llvm::Type *> Tys, TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_SizeAndLatency) const
public static llvm::TargetTransformInfo::CastContextHint getCastContextHint(const llvm::Instruction * I)
public llvm::InstructionCost getCastInstrCost(unsigned int Opcode, llvm::Type * Dst, llvm::Type * Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_SizeAndLatency, const llvm::Instruction * I = nullptr) const
public llvm::InstructionCost getCmpSelInstrCost(unsigned int Opcode, llvm::Type * ValTy, llvm::Type * CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput, const llvm::Instruction * I = nullptr) const
public llvm::InstructionCost getCostOfKeepingLiveOverCall(ArrayRef<llvm::Type *> Tys) const
public unsigned int getEstimatedNumberOfCaseClusters(const llvm::SwitchInst & SI, unsigned int & JTSize, llvm::ProfileSummaryInfo * PSI, llvm::BlockFrequencyInfo * BFI) const
public llvm::InstructionCost getExtendedAddReductionCost(bool IsMLA, bool IsUnsigned, llvm::Type * ResTy, llvm::VectorType * Ty, TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput) const
public llvm::InstructionCost getExtractWithExtendCost(unsigned int Opcode, llvm::Type * Dst, llvm::VectorType * VecTy, unsigned int Index = -1) const
public llvm::InstructionCost getFPOpCost(llvm::Type * Ty) const
public unsigned int getFlatAddressSpace() const
public llvm::InstructionCost getGEPCost(llvm::Type * PointeeType, const llvm::Value * Ptr, ArrayRef<const llvm::Value *> Operands, llvm::TargetTransformInfo::TargetCostKind CostKind = TCK_SizeAndLatency) const
public unsigned int getGISelRematGlobalCost() const
public llvm::InstructionCost getGatherScatterOpCost(unsigned int Opcode, llvm::Type * DataTy, const llvm::Value * Ptr, bool VariableMask, llvm::Align Alignment, TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput, const llvm::Instruction * I = nullptr) const
public int getInlinerVectorBonusPercent() const
public unsigned int getInliningThresholdMultiplier() const
public llvm::InstructionCost getInstructionCost(const llvm::Instruction * I, enum TargetCostKind kind) const
private llvm::InstructionCost getInstructionLatency(const llvm::Instruction * I) const
private llvm::InstructionCost getInstructionThroughput(const llvm::Instruction * I) const
public llvm::InstructionCost getIntImmCodeSizeCost(unsigned int Opc, unsigned int Idx, const llvm::APInt & Imm, llvm::Type * Ty) const
public llvm::InstructionCost getIntImmCost(const llvm::APInt & Imm, llvm::Type * Ty, llvm::TargetTransformInfo::TargetCostKind CostKind) const
public llvm::InstructionCost getIntImmCostInst(unsigned int Opc, unsigned int Idx, const llvm::APInt & Imm, llvm::Type * Ty, llvm::TargetTransformInfo::TargetCostKind CostKind, llvm::Instruction * Inst = nullptr) const
public llvm::InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned int Idx, const llvm::APInt & Imm, llvm::Type * Ty, llvm::TargetTransformInfo::TargetCostKind CostKind) const
public llvm::InstructionCost getInterleavedMemoryOpCost(unsigned int Opcode, llvm::Type * VecTy, unsigned int Factor, ArrayRef<unsigned int> Indices, llvm::Align Alignment, unsigned int AddressSpace, TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput, bool UseMaskForCond = false, bool UseMaskForGaps = false) const
public llvm::InstructionCost getIntrinsicInstrCost(const llvm::IntrinsicCostAttributes & ICA, TTI::TargetCostKind CostKind) const
public unsigned int getLoadStoreVecRegBitWidth(unsigned int AddrSpace) const
public unsigned int getLoadVectorFactor(unsigned int VF, unsigned int LoadSize, unsigned int ChainSizeInBytes, llvm::VectorType * VecTy) const
public llvm::InstructionCost getMaskedMemoryOpCost(unsigned int Opcode, llvm::Type * Src, llvm::Align Alignment, unsigned int AddressSpace, TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput) const
public unsigned int getMaxInterleaveFactor(unsigned int VF) const
public unsigned int getMaxPrefetchIterationsAhead() const
public Optional<unsigned int> getMaxVScale() const
public unsigned int getMaximumVF(unsigned int ElemWidth, unsigned int Opcode) const
public llvm::InstructionCost getMemcpyCost(const llvm::Instruction * I) const
public llvm::Type * getMemcpyLoopLoweringType(llvm::LLVMContext & Context, llvm::Value * Length, unsigned int SrcAddrSpace, unsigned int DestAddrSpace, unsigned int SrcAlign, unsigned int DestAlign, Optional<uint32_t> AtomicElementSize = None) const
public void getMemcpyLoopResidualLoweringType(SmallVectorImpl<llvm::Type *> & OpsOut, llvm::LLVMContext & Context, unsigned int RemainingBytes, unsigned int SrcAddrSpace, unsigned int DestAddrSpace, unsigned int SrcAlign, unsigned int DestAlign, Optional<uint32_t> AtomicCpySize = None) const
public llvm::InstructionCost getMemoryOpCost(unsigned int Opcode, llvm::Type * Src, llvm::Align Alignment, unsigned int AddressSpace, TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput, const llvm::Instruction * I = nullptr) const
public llvm::InstructionCost getMinMaxReductionCost(llvm::VectorType * Ty, llvm::VectorType * CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput) const
public unsigned int getMinPrefetchStride(unsigned int NumMemAccesses, unsigned int NumStridedMemAccesses, unsigned int NumPrefetches, bool HasCall) const
public unsigned int getMinTripCountTailFoldingThreshold() const
public unsigned int getMinVectorRegisterBitWidth() const
public llvm::ElementCount getMinimumVF(unsigned int ElemWidth, bool IsScalable) const
public unsigned int getNumberOfParts(llvm::Type * Tp) const
public unsigned int getNumberOfRegisters(unsigned int ClassID) const
public static llvm::TargetTransformInfo::OperandValueKind getOperandInfo(const llvm::Value * V, llvm::TargetTransformInfo::OperandValueProperties & OpProps)
public llvm::InstructionCost getOperandsScalarizationOverhead(ArrayRef<const llvm::Value *> Args, ArrayRef<llvm::Type *> Tys) const
public llvm::Value * getOrCreateResultFromMemIntrinsic(llvm::IntrinsicInst * Inst, llvm::Type * ExpectedType) const
public void getPeelingPreferences(llvm::Loop * L, llvm::ScalarEvolution & SE, llvm::TargetTransformInfo::PeelingPreferences & PP) const
public llvm::TargetTransformInfo::PopcntSupportKind getPopcntSupport(unsigned int IntTyWidthInBit) const
public std::pair<const Value *, unsigned int> getPredicatedAddrSpace(const llvm::Value * V) const
public llvm::BranchProbability getPredictableBranchThreshold() const
public llvm::TargetTransformInfo::AddressingModeKind getPreferredAddressingMode(const llvm::Loop * L, llvm::ScalarEvolution * SE) const
public unsigned int getPrefetchDistance() const
public unsigned int getRegUsageForType(llvm::Type * Ty) const
public llvm::TypeSize getRegisterBitWidth(llvm::TargetTransformInfo::RegisterKind K) const
public unsigned int getRegisterClassForType(bool Vector, llvm::Type * Ty = nullptr) const
public const char * getRegisterClassName(unsigned int ClassID) const
public llvm::InstructionCost getReplicationShuffleCost(llvm::Type * EltTy, int ReplicationFactor, int VF, const llvm::APInt & DemandedDstElts, TTI::TargetCostKind CostKind)
public llvm::InstructionCost getScalarizationOverhead(llvm::VectorType * Ty, const llvm::APInt & DemandedElts, bool Insert, bool Extract) const
public llvm::InstructionCost getScalingFactorCost(llvm::Type * Ty, llvm::GlobalValue * BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned int AddrSpace = 0) const
public llvm::InstructionCost getShuffleCost(llvm::TargetTransformInfo::ShuffleKind Kind, llvm::VectorType * Tp, ArrayRef<int> Mask = None, int Index = 0, llvm::VectorType * SubTp = nullptr, ArrayRef<const llvm::Value *> Args = None) const
public unsigned int getStoreMinimumVF(unsigned int VF, llvm::Type * ScalarMemTy, llvm::Type * ScalarValTy) const
public unsigned int getStoreVectorFactor(unsigned int VF, unsigned int StoreSize, unsigned int ChainSizeInBytes, llvm::VectorType * VecTy) const
public bool getTgtMemIntrinsic(llvm::IntrinsicInst * Inst, llvm::MemIntrinsicInfo & Info) const
public void getUnrollingPreferences(llvm::Loop * L, llvm::ScalarEvolution &, llvm::TargetTransformInfo::UnrollingPreferences & UP, llvm::OptimizationRemarkEmitter * ORE) const
public llvm::InstructionCost getUserCost(const llvm::User * U, ArrayRef<const llvm::Value *> Operands, llvm::TargetTransformInfo::TargetCostKind CostKind) const
public llvm::InstructionCost getUserCost(const llvm::User * U, llvm::TargetTransformInfo::TargetCostKind CostKind) const
public llvm::TargetTransformInfo::VPLegalization getVPLegalizationStrategy(const llvm::VPIntrinsic & PI) const
public llvm::InstructionCost getVPMemoryOpCost(unsigned int Opcode, llvm::Type * Src, llvm::Align Alignment, unsigned int AddressSpace, TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput, const llvm::Instruction * I = nullptr) const
public Optional<unsigned int> getVScaleForTuning() const
public llvm::InstructionCost getVectorInstrCost(unsigned int Opcode, llvm::Type * Val, unsigned int Index = -1) const
public bool hasActiveVectorLength(unsigned int Opcode, llvm::Type * DataType, llvm::Align Alignment) const
public bool hasBranchDivergence() const
public bool hasDivRemOp(llvm::Type * DataType, bool IsSigned) const
public bool hasVolatileVariant(llvm::Instruction * I, unsigned int AddrSpace) const
public bool haveFastSqrt(llvm::Type * Ty) const
public Optional<llvm::Instruction *> instCombineIntrinsic(llvm::InstCombiner & IC, llvm::IntrinsicInst & II) const
public bool invalidate(llvm::Function &, const llvm::PreservedAnalyses &, FunctionAnalysisManager::Invalidator &)
public bool isAlwaysUniform(const llvm::Value * V) const
public bool isElementTypeLegalForScalableVector(llvm::Type * Ty) const
public bool isFCmpOrdCheaperThanFCmpZero(llvm::Type * Ty) const
public bool isFPVectorizationPotentiallyUnsafe() const
public bool isHardwareLoopProfitable(llvm::Loop * L, llvm::ScalarEvolution & SE, llvm::AssumptionCache & AC, llvm::TargetLibraryInfo * LibInfo, llvm::HardwareLoopInfo & HWLoopInfo) const
public bool isIndexedLoadLegal(enum MemIndexedMode Mode, llvm::Type * Ty) const
public bool isIndexedStoreLegal(enum MemIndexedMode Mode, llvm::Type * Ty) const
public bool isLSRCostLess(const TargetTransformInfo::LSRCost & C1, const TargetTransformInfo::LSRCost & C2) const
public bool isLegalAddImmediate(int64_t Imm) const
public bool isLegalAddressingMode(llvm::Type * Ty, llvm::GlobalValue * BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned int AddrSpace = 0, llvm::Instruction * I = nullptr) const
public bool isLegalAltInstr(llvm::VectorType * VecTy, unsigned int Opcode0, unsigned int Opcode1, const llvm::SmallBitVector & OpcodeMask) const
public bool isLegalBroadcastLoad(llvm::Type * ElementTy, llvm::ElementCount NumElements) const
public bool isLegalICmpImmediate(int64_t Imm) const
public bool isLegalMaskedCompressStore(llvm::Type * DataType) const
public bool isLegalMaskedExpandLoad(llvm::Type * DataType) const
public bool isLegalMaskedGather(llvm::Type * DataType, llvm::Align Alignment) const
public bool isLegalMaskedLoad(llvm::Type * DataType, llvm::Align Alignment) const
public bool isLegalMaskedScatter(llvm::Type * DataType, llvm::Align Alignment) const
public bool isLegalMaskedStore(llvm::Type * DataType, llvm::Align Alignment) const
public bool isLegalNTLoad(llvm::Type * DataType, llvm::Align Alignment) const
public bool isLegalNTStore(llvm::Type * DataType, llvm::Align Alignment) const
public bool isLegalToVectorizeLoad(llvm::LoadInst * LI) const
public bool isLegalToVectorizeLoadChain(unsigned int ChainSizeInBytes, llvm::Align Alignment, unsigned int AddrSpace) const
public bool isLegalToVectorizeReduction(const llvm::RecurrenceDescriptor & RdxDesc, llvm::ElementCount VF) const
public bool isLegalToVectorizeStore(llvm::StoreInst * SI) const
public bool isLegalToVectorizeStoreChain(unsigned int ChainSizeInBytes, llvm::Align Alignment, unsigned int AddrSpace) const
public bool isLoweredToCall(const llvm::Function * F) const
public bool isNoopAddrSpaceCast(unsigned int FromAS, unsigned int ToAS) const
public bool isNumRegsMajorCostOfLSR() const
public bool isProfitableLSRChainElement(llvm::Instruction * I) const
public bool isProfitableToHoist(llvm::Instruction * I) const
public bool isSourceOfDivergence(const llvm::Value * V) const
public bool isTruncateFree(llvm::Type * Ty1, llvm::Type * Ty2) const
public bool isTypeLegal(llvm::Type * Ty) const
public bool preferInLoopReduction(unsigned int Opcode, llvm::Type * Ty, llvm::TargetTransformInfo::ReductionFlags Flags) const
public bool preferPredicateOverEpilogue(llvm::Loop * L, llvm::LoopInfo * LI, llvm::ScalarEvolution & SE, llvm::AssumptionCache & AC, llvm::TargetLibraryInfo * TLI, llvm::DominatorTree * DT, llvm::LoopVectorizationLegality * LVL) const
public bool preferPredicatedReductionSelect(unsigned int Opcode, llvm::Type * Ty, llvm::TargetTransformInfo::ReductionFlags Flags) const
public bool prefersVectorizedAddressing() const
public static bool requiresOrderedReduction(Optional<llvm::FastMathFlags> FMF)
public llvm::Value * rewriteIntrinsicWithAddressSpace(llvm::IntrinsicInst * II, llvm::Value * OldV, llvm::Value * NewV) const
public bool shouldBuildLookupTables() const
public bool shouldBuildLookupTablesForConstant(llvm::Constant * C) const
public bool shouldBuildRelLookupTables() const
public bool shouldConsiderAddressTypePromotion(const llvm::Instruction & I, bool & AllowPromotionWithoutCommonHeader) const
public bool shouldExpandReduction(const llvm::IntrinsicInst * II) const
public bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
public Optional<llvm::Value *> simplifyDemandedUseBitsIntrinsic(llvm::InstCombiner & IC, llvm::IntrinsicInst & II, llvm::APInt DemandedMask, llvm::KnownBits & Known, bool & KnownBitsComputed) const
public Optional<llvm::Value *> simplifyDemandedVectorEltsIntrinsic(llvm::InstCombiner & IC, llvm::IntrinsicInst & II, llvm::APInt DemandedElts, llvm::APInt & UndefElts, llvm::APInt & UndefElts2, llvm::APInt & UndefElts3, std::function<void (Instruction *, unsigned int, APInt, APInt &)> SimplifyAndSetOp) const
public bool supportsEfficientVectorElementLoadStore() const
public bool supportsScalableVectors() const
public bool supportsTailCalls() const
public bool useAA() const
public bool useColdCCForColdCall(llvm::Function & F) const
public bool useGPUDivergenceAnalysis() const
public ~TargetTransformInfo()

Methods

¶bool LSRWithInstrQueries() const

Description

Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAddressingMode(). This is needed on SystemZ, where e.g. a memcpy can only have a 12 bit unsigned immediate offset and no index register.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:734

¶TargetTransformInfo(
    llvm::TargetTransformInfo&& Arg)

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:188

Parameters

llvm::TargetTransformInfo&& Arg

¶template <typename T>
TargetTransformInfo(T Impl)

Description

Construct a TTI object using a type implementing the \c Concept API below. This is used by targets to construct a TTI wrapping their target-specific implementation that encodes appropriate costs for their target.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:178

Templates

T

Parameters

T Impl

¶TargetTransformInfo(const llvm::DataLayout& DL)

Description

Construct a baseline TTI object using a minimal implementation of the \c Concept API below. The TTI implementation will reflect the information in the DataLayout provided if non-null.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:185

Parameters

const llvm::DataLayout& DL

¶unsigned int adjustInliningThreshold(
    const llvm::CallBase* CB) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:285

Parameters

const llvm::CallBase* CB

Returns

A value to be added to the inlining threshold.

¶bool allowsMisalignedMemoryAccesses(
    llvm::LLVMContext& Context,
    unsigned int BitWidth,
    unsigned int AddressSpace = 0,
    llvm::Align Alignment = llvm::Align(1),
    bool* Fast = nullptr) const

Description

Determine if the target supports unaligned memory accesses.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:840

Parameters

llvm::LLVMContext& Context
unsigned int BitWidth
unsigned int AddressSpace = 0
llvm::Align Alignment = llvm::Align(1)
bool* Fast = nullptr

¶bool areInlineCompatible(
    const llvm::Function* Caller,
    const llvm::Function* Callee) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1345

Parameters

const llvm::Function* Caller
const llvm::Function* Callee

Returns

True if the two functions have compatible attributes for inlining purposes.

¶bool areTypesABICompatible(
    const llvm::Function* Caller,
    const llvm::Function* Callee,
    const ArrayRef<llvm::Type*>& Types) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1352

Parameters

const llvm::Function* Caller
const llvm::Function* Callee
const ArrayRef<llvm::Type*>& Types: List of types to check.

Returns

True if the caller and callee agree on how \p Types will be passed to or returned from the callee. to the callee.

¶bool canHaveNonUndefGlobalInitializerInAddressSpace(
    unsigned int AS) const

Description

Return true if globals in this address space can have initializers other than `undef`.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:391

Parameters

unsigned int AS

¶bool canMacroFuseCmp() const

Description

Return true if the target can fuse a compare and branch. Loop-strength-reduction (LSR) uses that knowledge to adjust its cost calculation for the instructions in a loop.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:641

¶bool canSaveCmp(
    llvm::Loop* L,
    llvm::BranchInst** BI,
    llvm::ScalarEvolution* SE,
    llvm::LoopInfo* LI,
    llvm::DominatorTree* DT,
    llvm::AssumptionCache* AC,
    llvm::TargetLibraryInfo* LibInfo) const

Description

Return true if the target can save a compare for loop count, for example hardware loop saves a compare.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:645

Parameters

llvm::Loop* L
llvm::BranchInst** BI
llvm::ScalarEvolution* SE
llvm::LoopInfo* LI
llvm::DominatorTree* DT
llvm::AssumptionCache* AC
llvm::TargetLibraryInfo* LibInfo

¶bool collectFlatAddressOperands(
    SmallVectorImpl<int>& OpIndexes,
    Intrinsic::ID IID) const

Description

Return any intrinsic address operand indexes which may be rewritten if they use a flat address space pointer.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:384

Parameters

SmallVectorImpl<int>& OpIndexes
Intrinsic::ID IID

Returns

true if the intrinsic was handled.

¶llvm::PredicationStyle emitGetActiveLaneMask()
    const

Description

Query the target whether lowering of the llvm.get.active.lane.mask intrinsic is supported and how the mask should be used. A return value of PredicationStyle::Data indicates the mask is used as data only, whereas PredicationStyle::DataAndControlFlow indicates we should also use the mask for control flow in the loop. If unsupported the return value is PredicationStyle::None.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:542

¶bool enableAggressiveInterleaving(
    bool LoopHasReductions) const

Description

Don't restrict interleaved unrolling to small loops.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:790

Parameters

bool LoopHasReductions

¶bool enableInterleavedAccessVectorization() const

Description

Enable matching of interleaved access groups.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:823

¶bool enableMaskedInterleavedAccessVectorization()
    const

Description

Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore vectorized using masked vector loads/stores.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:828

¶llvm::TargetTransformInfo::MemCmpExpansionOptions
enableMemCmpExpansion(bool OptSize,
                      bool IsZeroCmp) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:819

Parameters

bool OptSize
bool IsZeroCmp

¶bool enableOrderedReductions() const

Description

Return true if we should be enabling ordered reductions for the target.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:700

¶bool enableScalableVectorization() const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1451

Returns

true when scalable vectorization is preferred.

¶bool enableWritePrefetching() const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1043

Returns

True if prefetching should also be done for writes.

¶bool forceScalarizeMaskedGather(
    llvm::VectorType* Type,
    llvm::Align Alignment) const

Description

Return true if the target forces scalarizing of llvm.masked.gather intrinsics.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:679

Parameters

llvm::VectorType* Type
llvm::Align Alignment

¶bool forceScalarizeMaskedScatter(
    llvm::VectorType* Type,
    llvm::Align Alignment) const

Description

Return true if the target forces scalarizing of llvm.masked.scatter intrinsics.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:682

Parameters

llvm::VectorType* Type
llvm::Align Alignment

¶llvm::InstructionCost getAddressComputationCost(
    llvm::Type* Ty,
    llvm::ScalarEvolution* SE = nullptr,
    const llvm::SCEV* Ptr = nullptr) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1296

Parameters

llvm::Type* Ty
llvm::ScalarEvolution* SE = nullptr
const llvm::SCEV* Ptr = nullptr

Returns

The cost of the address computation. For most targets this can be merged into the instruction indexing mode. Some targets might want to distinguish between address computation for memory operations on vector types and scalar types. Such targets should override this function. The 'SE' parameter holds pointer for the scalar evolution object which is used in order to get the Ptr step value in case of constant stride. The 'Ptr' parameter holds SCEV of the access pointer.

¶llvm::InstructionCost getArithmeticInstrCost(
    unsigned int Opcode,
    llvm::Type* Ty,
    TTI::TargetCostKind CostKind =
        TargetTransformInfo::TCK_RecipThroughput,
    llvm::TargetTransformInfo::OperandValueKind
        Opd1Info = OK_AnyValue,
    llvm::TargetTransformInfo::OperandValueKind
        Opd2Info = OK_AnyValue,
    llvm::TargetTransformInfo::
        OperandValueProperties Opd1PropInfo =
            OP_None,
    llvm::TargetTransformInfo::
        OperandValueProperties Opd2PropInfo =
            OP_None,
    ArrayRef<const llvm::Value*> Args =
        llvm::ArrayRef<const llvm::Value*>(),
    const llvm::Instruction* CxtI = nullptr) const

Description

This is an approximation of reciprocal throughput of a math/logic op. A higher cost indicates less expected throughput. From Agner Fog's guides, reciprocal throughput is "the average number of clock cycles per instruction when the instructions are not part of a limiting dependency chain." Therefore, costs should be scaled to account for multiple execution units on the target that can process this type of instruction. For example, if there are 5 scalar integer units and 2 vector integer units that can calculate an 'add' in a single cycle, this model should indicate that the cost of the vector add instruction is 2.5 times the cost of the scalar add instruction.\p Args is an optional argument which holds the instruction operands values so the TTI can analyze those values searching for special cases or optimizations based on those values.\p CxtI is the optional original context instruction, if one exists, to provide even more information.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1070

Parameters

unsigned int Opcode
llvm::Type* Ty
TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput
llvm::TargetTransformInfo::OperandValueKind Opd1Info = OK_AnyValue
llvm::TargetTransformInfo::OperandValueKind Opd2Info = OK_AnyValue
llvm::TargetTransformInfo::OperandValueProperties Opd1PropInfo = OP_None
llvm::TargetTransformInfo::OperandValueProperties Opd2PropInfo = OP_None
ArrayRef<const llvm::Value*> Args = llvm::ArrayRef<const llvm::Value *>()
const llvm::Instruction* CxtI = nullptr

¶llvm::InstructionCost getArithmeticReductionCost(
    unsigned int Opcode,
    llvm::VectorType* Ty,
    Optional<llvm::FastMathFlags> FMF,
    TTI::TargetCostKind CostKind =
        TargetTransformInfo::TCK_RecipThroughput)
    const

Description

Calculate the cost of vector reduction intrinsics. This is the cost of reducing the vector value of type \p Ty to a scalar value using the operation denoted by \p Opcode. The FastMathFlags parameter \p FMF indicates what type of reduction we are performing: 1. Tree-wise. This is the typical 'fast' reduction performed that involves successively splitting a vector into half and doing the operation on the pair of halves until you have a scalar value. For example: (v0, v1, v2, v3) ((v0+v2), (v1+v3), undef, undef) ((v0+v2+v1+v3), undef, undef, undef) This is the default behaviour for integer operations, whereas for floating point we only do this if \p FMF indicates that reassociation is allowed. 2. Ordered. For a vector with N elements this involves performing N operations in lane order, starting with an initial scalar value, i.e. result = InitVal + v0 result = result + v1 result = result + v2 result = result + v3 This is only the case for FP operations and when reassociation is not allowed.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1256

Parameters

unsigned int Opcode
llvm::VectorType* Ty
Optional<llvm::FastMathFlags> FMF
TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput

¶unsigned int getAssumedAddrSpace(
    const llvm::Value* V) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:393

Parameters

const llvm::Value* V

¶unsigned int getAtomicMemIntrinsicMaxElementSize()
    const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1315

Returns

The maximum element size, in bytes, for an element unordered-atomic memory intrinsic.

¶llvm::InstructionCost getCFInstrCost(
    unsigned int Opcode,
    TTI::TargetCostKind CostKind =
        TargetTransformInfo::TCK_SizeAndLatency,
    const llvm::Instruction* I = nullptr) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1147

Parameters

unsigned int Opcode
TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_SizeAndLatency
const llvm::Instruction* I = nullptr

Returns

The expected cost of control-flow related instructions such as Phi, Ret, Br, Switch.

¶Optional<unsigned int> getCacheAssociativity(
    llvm::TargetTransformInfo::CacheLevel Level)
    const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1009

Parameters

llvm::TargetTransformInfo::CacheLevel Level

Returns

The associativity of the cache level, if available.

¶unsigned int getCacheLineSize() const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:993

Returns

The size of a cache line in bytes.

¶Optional<unsigned int> getCacheSize(
    llvm::TargetTransformInfo::CacheLevel Level)
    const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1006

Parameters

llvm::TargetTransformInfo::CacheLevel Level

Returns

The size of the cache level in bytes, if available.

¶llvm::InstructionCost getCallInstrCost(
    llvm::Function* F,
    llvm::Type* RetTy,
    ArrayRef<llvm::Type*> Tys,
    TTI::TargetCostKind CostKind =
        TargetTransformInfo::TCK_SizeAndLatency)
    const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1281

Parameters

llvm::Function* F
llvm::Type* RetTy
ArrayRef<llvm::Type*> Tys
TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_SizeAndLatency

Returns

The cost of Call instructions.

¶static llvm::TargetTransformInfo::CastContextHint
getCastContextHint(const llvm::Instruction* I)

Description

Calculates a CastContextHint from \p I. This should be used by callers of getCastInstrCost if they wish to determine the context from some instruction.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1127

Parameters

const llvm::Instruction* I

Returns

the CastContextHint for ZExt/SExt/Trunc, None if \p I is nullptr, or if it's another type of cast.

¶llvm::InstructionCost getCastInstrCost(
    unsigned int Opcode,
    llvm::Type* Dst,
    llvm::Type* Src,
    TTI::CastContextHint CCH,
    TTI::TargetCostKind CostKind =
        TargetTransformInfo::TCK_SizeAndLatency,
    const llvm::Instruction* I = nullptr) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1133

Parameters

unsigned int Opcode
llvm::Type* Dst
llvm::Type* Src
TTI::CastContextHint CCH
TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_SizeAndLatency
const llvm::Instruction* I = nullptr

Returns

The expected cost of cast instructions, such as bitcast, trunc, zext, etc. If there is an existing instruction that holds Opcode, it may be passed in the 'I' parameter.

¶llvm::InstructionCost getCmpSelInstrCost(
    unsigned int Opcode,
    llvm::Type* ValTy,
    llvm::Type* CondTy,
    CmpInst::Predicate VecPred,
    TTI::TargetCostKind CostKind =
        TargetTransformInfo::TCK_RecipThroughput,
    const llvm::Instruction* I = nullptr) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1157

Parameters

unsigned int Opcode
llvm::Type* ValTy
llvm::Type* CondTy
CmpInst::Predicate VecPred
TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput
const llvm::Instruction* I = nullptr

Returns

The expected cost of compare and select instructions. If there is an existing instruction that holds Opcode, it may be passed in the 'I' parameter. The \p VecPred parameter can be used to indicate the select is using a compare with the specified predicate as condition. When vector types are passed, \p VecPred must be used for all lanes.

¶llvm::InstructionCost
getCostOfKeepingLiveOverCall(
    ArrayRef<llvm::Type*> Tys) const

Description

Some types may require the use of register classes that do not have any callee-saved registers, so would require a spill and fill.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1305

Parameters

ArrayRef<llvm::Type*> Tys

Returns

The cost, if any, of keeping values of the given types alive over a callsite.

¶unsigned int getEstimatedNumberOfCaseClusters(
    const llvm::SwitchInst& SI,
    unsigned int& JTSize,
    llvm::ProfileSummaryInfo* PSI,
    llvm::BlockFrequencyInfo* BFI) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:306

Parameters

const llvm::SwitchInst& SI
unsigned int& JTSize
llvm::ProfileSummaryInfo* PSI
llvm::BlockFrequencyInfo* BFI

Returns

The estimated number of case clusters when lowering \p 'SI'. \p JTSize Set a jump table size only when \p SI is suitable for a jump table.

¶llvm::InstructionCost getExtendedAddReductionCost(
    bool IsMLA,
    bool IsUnsigned,
    llvm::Type* ResTy,
    llvm::VectorType* Ty,
    TTI::TargetCostKind CostKind =
        TargetTransformInfo::TCK_RecipThroughput)
    const

Description

Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of an Add reduction with an extension and optional multiply. This is the cost of as: ResTy vecreduce.add(ext(Ty A)), or if IsMLA flag is set then: ResTy vecreduce.add(mul(ext(Ty A), ext(Ty B)). The reduction happens on a VectorType with ResTy elements and Ty lanes.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1270

Parameters

bool IsMLA
bool IsUnsigned
llvm::Type* ResTy
llvm::VectorType* Ty
TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput

¶llvm::InstructionCost getExtractWithExtendCost(
    unsigned int Opcode,
    llvm::Type* Dst,
    llvm::VectorType* VecTy,
    unsigned int Index = -1) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1140

Parameters

unsigned int Opcode
llvm::Type* Dst
llvm::VectorType* VecTy
unsigned int Index = -1

Returns

The expected cost of a sign- or zero-extended vector extract. Use -1 to indicate that there is no information about the index value.

¶llvm::InstructionCost getFPOpCost(
    llvm::Type* Ty) const

Description

Return the expected cost of supporting the floating point operation of the specified type.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:859

Parameters

llvm::Type* Ty

¶unsigned int getFlatAddressSpace() const

Description

This is for targets with different pointer representations which can be converted with the addrspacecast instruction. If a pointer is converted to this address space, optimizations should attempt to replace the access with the source address space.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:378

Returns

~0u if the target does not have such a flat address space to optimize away.

¶llvm::InstructionCost getGEPCost(
    llvm::Type* PointeeType,
    const llvm::Value* Ptr,
    ArrayRef<const llvm::Value*> Operands,
    llvm::TargetTransformInfo::TargetCostKind
        CostKind = TCK_SizeAndLatency) const

Description

Estimate the cost of a GEP operation when lowered.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:272

Parameters

llvm::Type* PointeeType
const llvm::Value* Ptr
ArrayRef<const llvm::Value*> Operands
llvm::TargetTransformInfo::TargetCostKind CostKind = TCK_SizeAndLatency

¶unsigned int getGISelRematGlobalCost() const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1441

Returns

the size cost of rematerializing a GlobalValue address relative to a stack reload.

¶llvm::InstructionCost getGatherScatterOpCost(
    unsigned int Opcode,
    llvm::Type* DataTy,
    const llvm::Value* Ptr,
    bool VariableMask,
    llvm::Align Alignment,
    TTI::TargetCostKind CostKind =
        TargetTransformInfo::TCK_RecipThroughput,
    const llvm::Instruction* I = nullptr) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1205

Parameters

unsigned int Opcode
llvm::Type* DataTy
const llvm::Value* Ptr
bool VariableMask
llvm::Align Alignment
TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput
const llvm::Instruction* I = nullptr

Returns

The cost of Gather or Scatter operation\p Opcode - is a type of memory access Load or Store\p DataTy - a vector type of the data to be loaded or stored\p Ptr - pointer [or vector of pointers] - address[es] in memory\p VariableMask - true when the memory access is predicated with a mask that is not a compile-time constant\p Alignment - alignment of single element\p I - the optional original context instruction, if one exists, e.g. the load/store to transform or the call to the gather/scatter intrinsic

¶int getInlinerVectorBonusPercent() const

Description

Vector bonuses: We want to more aggressively inline vector-dense kernels and apply this bonus based on the percentage of vector instructions. A bonus is applied if the vector instructions exceed 50% and half that amount is applied if it exceeds 10%. Note that these bonuses are some what arbitrary and evolved over time by accident as much as because they are principled bonuses. FIXME: It would be nice to base the bonus values on something more scientific. A target may has no bonus on vector instructions.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:297

Returns

Vector bonus in percent.

¶unsigned int getInliningThresholdMultiplier()
    const

Description

TODO: This is a rather blunt instrument. Perhaps altering the costs of individual classes of instructions would be better.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:282

Returns

A value by which our inlining threshold should be multiplied. This is primarily used to bump up the inlining threshold wholesale on targets where calls are unusually expensive.

¶llvm::InstructionCost getInstructionCost(
    const llvm::Instruction* I,
    enum TargetCostKind kind) const

Description

Query the cost of a specified instruction. Clients should use this interface to query the cost of an existing instruction. The instruction must have a valid parent (basic block). Note, this method does not cache the cost calculation and it can be expensive in some cases.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:228

Parameters

const llvm::Instruction* I
enum TargetCostKind kind

¶llvm::InstructionCost getInstructionLatency(
    const llvm::Instruction* I) const

Description

Estimate the latency of specified instruction. Returns 1 as the default value.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1501

Parameters

const llvm::Instruction* I

¶llvm::InstructionCost getInstructionThroughput(
    const llvm::Instruction* I) const

Description

Returns the expected throughput cost of the instruction. Returns -1 if the cost is unknown.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1505

Parameters

const llvm::Instruction* I

¶llvm::InstructionCost getIntImmCodeSizeCost(
    unsigned int Opc,
    unsigned int Idx,
    const llvm::APInt& Imm,
    llvm::Type* Ty) const

Description

Return the expected cost for the given integer when optimising for size. This is different than the other integer immediate cost functions in that it is subtarget agnostic. This is useful when you e.g. target one ISA such as Aarch32 but smaller encodings could be possible with another such as Thumb. This return value is used as a penalty when the total costs for a constant is calculated (the bigger the cost, the more beneficial constant hoisting is).

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:884

Parameters

unsigned int Opc
unsigned int Idx
const llvm::APInt& Imm
llvm::Type* Ty

¶llvm::InstructionCost getIntImmCost(
    const llvm::APInt& Imm,
    llvm::Type* Ty,
    llvm::TargetTransformInfo::TargetCostKind
        CostKind) const

Description

Return the expected cost of materializing for the given integer immediate of the specified type.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:863

Parameters

const llvm::APInt& Imm
llvm::Type* Ty
llvm::TargetTransformInfo::TargetCostKind CostKind

¶llvm::InstructionCost getIntImmCostInst(
    unsigned int Opc,
    unsigned int Idx,
    const llvm::APInt& Imm,
    llvm::Type* Ty,
    llvm::TargetTransformInfo::TargetCostKind
        CostKind,
    llvm::Instruction* Inst = nullptr) const

Description

Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction. The cost can be zero if the immediate can be folded into the specified instruction.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:869

Parameters

unsigned int Opc
unsigned int Idx
const llvm::APInt& Imm
llvm::Type* Ty
llvm::TargetTransformInfo::TargetCostKind CostKind
llvm::Instruction* Inst = nullptr

¶llvm::InstructionCost getIntImmCostIntrin(
    Intrinsic::ID IID,
    unsigned int Idx,
    const llvm::APInt& Imm,
    llvm::Type* Ty,
    llvm::TargetTransformInfo::TargetCostKind
        CostKind) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:873

Parameters

Intrinsic::ID IID
unsigned int Idx
const llvm::APInt& Imm
llvm::Type* Ty
llvm::TargetTransformInfo::TargetCostKind CostKind

¶llvm::InstructionCost getInterleavedMemoryOpCost(
    unsigned int Opcode,
    llvm::Type* VecTy,
    unsigned int Factor,
    ArrayRef<unsigned int> Indices,
    llvm::Align Alignment,
    unsigned int AddressSpace,
    TTI::TargetCostKind CostKind =
        TargetTransformInfo::TCK_RecipThroughput,
    bool UseMaskForCond = false,
    bool UseMaskForGaps = false) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1220

Parameters

unsigned int Opcode
llvm::Type* VecTy
unsigned int Factor
ArrayRef<unsigned int> Indices
llvm::Align Alignment
unsigned int AddressSpace
TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput
bool UseMaskForCond = false
bool UseMaskForGaps = false

Returns

The cost of the interleaved memory operation.\p Opcode is the memory operation code\p VecTy is the vector type of the interleaved access.\p Factor is the interleave factor\p Indices is the indices for interleaved load members (as interleaved load allows gaps)\p Alignment is the alignment of the memory operation\p AddressSpace is address space of the pointer.\p UseMaskForCond indicates if the memory access is predicated.\p UseMaskForGaps indicates if gaps should be masked.

¶llvm::InstructionCost getIntrinsicInstrCost(
    const llvm::IntrinsicCostAttributes& ICA,
    TTI::TargetCostKind CostKind) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1277

Parameters

const llvm::IntrinsicCostAttributes& ICA
TTI::TargetCostKind CostKind

Returns

The cost of Intrinsic instructions. Analyses the real arguments. Three cases are handled: 1. scalar instruction 2. vector instruction 3. scalar instruction which is to be vectorized.

¶unsigned int getLoadStoreVecRegBitWidth(
    unsigned int AddrSpace) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1372

Parameters

unsigned int AddrSpace

Returns

The bitwidth of the largest vector type that should be used to load/store in the given address space.

¶unsigned int getLoadVectorFactor(
    unsigned int VF,
    unsigned int LoadSize,
    unsigned int ChainSizeInBytes,
    llvm::VectorType* VecTy) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1397

Parameters

unsigned int VF
unsigned int LoadSize
unsigned int ChainSizeInBytes
llvm::VectorType* VecTy

Returns

The new vector factor value if the target doesn't support \p SizeInBytes loads or has a better vector factor.

¶llvm::InstructionCost getMaskedMemoryOpCost(
    unsigned int Opcode,
    llvm::Type* Src,
    llvm::Align Alignment,
    unsigned int AddressSpace,
    TTI::TargetCostKind CostKind =
        TargetTransformInfo::TCK_RecipThroughput)
    const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1192

Parameters

unsigned int Opcode
llvm::Type* Src
llvm::Align Alignment
unsigned int AddressSpace
TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput

Returns

The cost of masked Load and Store instructions.

¶unsigned int getMaxInterleaveFactor(
    unsigned int VF) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1048

Parameters

unsigned int VF

Returns

The maximum interleave factor that any transform should try to perform for this target. This number depends on the level of parallelism and the number of execution units in the CPU.

¶unsigned int getMaxPrefetchIterationsAhead() const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1040

Returns

The maximum number of iterations to prefetch ahead. If the required number of iterations is more than this number, no prefetching is performed.

¶Optional<unsigned int> getMaxVScale() const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:950

Returns

The maximum value of vscale if the target specifies an architectural maximum vector length, and None otherwise.

¶unsigned int getMaximumVF(
    unsigned int ElemWidth,
    unsigned int Opcode) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:973

Parameters

unsigned int ElemWidth
unsigned int Opcode

Returns

The maximum vectorization factor for types of given element bit width and opcode, or 0 if there is no maximum VF. Currently only used by the SLP vectorizer.

¶llvm::InstructionCost getMemcpyCost(
    const llvm::Instruction* I) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:301

Parameters

const llvm::Instruction* I

Returns

the expected cost of a memcpy, which could e.g. depend on the source/destination type and alignment and the number of bytes copied.

¶llvm::Type* getMemcpyLoopLoweringType(
    llvm::LLVMContext& Context,
    llvm::Value* Length,
    unsigned int SrcAddrSpace,
    unsigned int DestAddrSpace,
    unsigned int SrcAlign,
    unsigned int DestAlign,
    Optional<uint32_t> AtomicElementSize =
        None) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1326

Parameters

llvm::LLVMContext& Context
llvm::Value* Length
unsigned int SrcAddrSpace
unsigned int DestAddrSpace
unsigned int SrcAlign
unsigned int DestAlign
Optional<uint32_t> AtomicElementSize = None

Returns

The type to use in a loop expansion of a memcpy call.

¶void getMemcpyLoopResidualLoweringType(
    SmallVectorImpl<llvm::Type*>& OpsOut,
    llvm::LLVMContext& Context,
    unsigned int RemainingBytes,
    unsigned int SrcAddrSpace,
    unsigned int DestAddrSpace,
    unsigned int SrcAlign,
    unsigned int DestAlign,
    Optional<uint32_t> AtomicCpySize = None) const

Description

Calculates the operand types to use when copying \p RemainingBytes of memory, where source and destination alignments are \p SrcAlign and\p DestAlign respectively.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1337

Parameters

SmallVectorImpl<llvm::Type*>& OpsOut: The operand types to copy RemainingBytes of memory.
llvm::LLVMContext& Context
unsigned int RemainingBytes: The number of bytes to copy.
unsigned int SrcAddrSpace
unsigned int DestAddrSpace
unsigned int SrcAlign
unsigned int DestAlign
Optional<uint32_t> AtomicCpySize = None

¶llvm::InstructionCost getMemoryOpCost(
    unsigned int Opcode,
    llvm::Type* Src,
    llvm::Align Alignment,
    unsigned int AddressSpace,
    TTI::TargetCostKind CostKind =
        TargetTransformInfo::TCK_RecipThroughput,
    const llvm::Instruction* I = nullptr) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1179

Parameters

unsigned int Opcode
llvm::Type* Src
llvm::Align Alignment
unsigned int AddressSpace
TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput
const llvm::Instruction* I = nullptr

Returns

The cost of Load and Store instructions.

¶llvm::InstructionCost getMinMaxReductionCost(
    llvm::VectorType* Ty,
    llvm::VectorType* CondTy,
    bool IsUnsigned,
    TTI::TargetCostKind CostKind =
        TargetTransformInfo::TCK_RecipThroughput)
    const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1260

Parameters

llvm::VectorType* Ty
llvm::VectorType* CondTy
bool IsUnsigned
TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput

¶unsigned int getMinPrefetchStride(
    unsigned int NumMemAccesses,
    unsigned int NumStridedMemAccesses,
    unsigned int NumPrefetches,
    bool HasCall) const

Description

Some HW prefetchers can handle accesses up to a certain constant stride. Sometimes prefetching is beneficial even below the HW prefetcher limit, and the arguments provided are meant to serve as a basis for deciding this for a particular loop.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1033

Parameters

unsigned int NumMemAccesses: Number of memory accesses in the loop.
unsigned int NumStridedMemAccesses: Number of the memory accesses that ScalarEvolution could find a known stride for.
unsigned int NumPrefetches: Number of software prefetches that will be emitted as determined by the addresses involved and the cache line size.
bool HasCall: True if the loop contains a call.

Returns

This is the minimum stride in bytes where it makes sense to start adding SW prefetches. The default is 1, i.e. prefetch with any stride.

¶unsigned int getMinTripCountTailFoldingThreshold()
    const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1445

Returns

the lower bound of a trip count to decide on vectorization while tail-folding.

¶unsigned int getMinVectorRegisterBitWidth() const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:946

Returns

The width of the smallest vector register type.

¶llvm::ElementCount getMinimumVF(
    unsigned int ElemWidth,
    bool IsScalable) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:968

Parameters

unsigned int ElemWidth
bool IsScalable

Returns

The minimum vectorization factor for types of given element bit width, or 0 if there is no minimum VF. The returned value only applies when shouldMaximizeVectorBandwidth returns true. If IsScalable is true, the returned ElementCount must be a scalable VF.

¶unsigned int getNumberOfParts(
    llvm::Type* Tp) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1287

Parameters

llvm::Type* Tp

Returns

The number of pieces into which the provided type must be split during legalization. Zero is returned when the answer is unknown.

¶unsigned int getNumberOfRegisters(
    unsigned int ClassID) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:922

Parameters

unsigned int ClassID

Returns

the number of registers in the target-provided register class.

¶static llvm::TargetTransformInfo::OperandValueKind
getOperandInfo(
    const llvm::Value* V,
    llvm::TargetTransformInfo::
        OperandValueProperties& OpProps)

Description

Collect properties of V used in cost analysis, e.g. OP_PowerOf2.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1051

Parameters

const llvm::Value* V
llvm::TargetTransformInfo::OperandValueProperties& OpProps

¶llvm::InstructionCost
getOperandsScalarizationOverhead(
    ArrayRef<const llvm::Value*> Args,
    ArrayRef<llvm::Type*> Tys) const

Description

Estimate the overhead of scalarizing an instructions unique non-constant operands. The (potentially vector) types to use for each of argument are passes via Tys.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:778

Parameters

ArrayRef<const llvm::Value*> Args
ArrayRef<llvm::Type*> Tys

¶llvm::Value* getOrCreateResultFromMemIntrinsic(
    llvm::IntrinsicInst* Inst,
    llvm::Type* ExpectedType) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1321

Parameters

llvm::IntrinsicInst* Inst
llvm::Type* ExpectedType

Returns

A value which is the result of the given memory intrinsic. New instructions may be created to extract the result from the given intrinsic memory operation. Returns nullptr if the target cannot create a result from the given intrinsic.

¶void getPeelingPreferences(
    llvm::Loop* L,
    llvm::ScalarEvolution& SE,
    llvm::TargetTransformInfo::PeelingPreferences&
        PP) const

Description

Get target-customized preferences for the generic loop peeling transformation. The caller will initialize \p PP with the current target-independent defaults with information from \p L and \p SE.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:564

Parameters

llvm::Loop* L
llvm::ScalarEvolution& SE
llvm::TargetTransformInfo::PeelingPreferences& PP

¶llvm::TargetTransformInfo::PopcntSupportKind
getPopcntSupport(
    unsigned int IntTyWidthInBit) const

Description

Return hardware support for population count.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:846

Parameters

unsigned int IntTyWidthInBit

¶std::pair<const Value*, unsigned int>
getPredicatedAddrSpace(const llvm::Value* V) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:396

Parameters

const llvm::Value* V

¶llvm::BranchProbability
getPredictableBranchThreshold() const

Description

If a branch or a select condition is skewed in one direction by more than this factor, it is very likely to be predicted correctly.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:336

¶llvm::TargetTransformInfo::AddressingModeKind
getPreferredAddressingMode(
    const llvm::Loop* L,
    llvm::ScalarEvolution* SE) const

Description

Return the preferred addressing mode LSR should make efforts to generate.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:656

Parameters

const llvm::Loop* L
llvm::ScalarEvolution* SE

¶unsigned int getPrefetchDistance() const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1014

Returns

How much before a load we should place the prefetch instruction. This is currently measured in number of instructions.

¶unsigned int getRegUsageForType(
    llvm::Type* Ty) const

Description

Returns the estimated number of registers required to represent \p Ty.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:751

Parameters

llvm::Type* Ty

¶llvm::TypeSize getRegisterBitWidth(
    llvm::TargetTransformInfo::RegisterKind K)
    const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:943

Parameters

llvm::TargetTransformInfo::RegisterKind K

Returns

The width of the largest scalar or vector register type.

¶unsigned int getRegisterClassForType(
    bool Vector,
    llvm::Type* Ty = nullptr) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:935

Parameters

bool Vector
llvm::Type* Ty = nullptr

Returns

the target-provided register class ID for the provided type, accounting for type promotion and other type-legalization techniques that the target might apply. However, it specifically does not account for the scalarization or splitting of vector types. Should a vector type require scalarization or splitting into multiple underlying vector registers, that type should be mapped to a register class containing no registers. Specifically, this is designed to provide a simple, high-level view of the register allocation later performed by the backend. These register classes don't necessarily map onto the register classes used by the backend. FIXME: It's not currently possible to determine how many registers are used by the provided type.

¶const char* getRegisterClassName(
    unsigned int ClassID) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:938

Parameters

unsigned int ClassID

Returns

the target-provided register class name

¶llvm::InstructionCost getReplicationShuffleCost(
    llvm::Type* EltTy,
    int ReplicationFactor,
    int VF,
    const llvm::APInt& DemandedDstElts,
    TTI::TargetCostKind CostKind)

Description

For example, the mask for \p ReplicationFactor=3 and \p VF=4 is: < 0,0,0,1,1,1,2,2,2,3,3,3>

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1172

Parameters

llvm::Type* EltTy
int ReplicationFactor
int VF
const llvm::APInt& DemandedDstElts
TTI::TargetCostKind CostKind

Returns

The cost of replication shuffle of \p VF elements typed \p EltTy \p ReplicationFactor times.

¶llvm::InstructionCost getScalarizationOverhead(
    llvm::VectorType* Ty,
    const llvm::APInt& DemandedElts,
    bool Insert,
    bool Extract) const

Description

Estimate the overhead of scalarizing an instruction. Insert and Extract are set if the demanded result elements need to be inserted and/or extracted from vectors.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:771

Parameters

llvm::VectorType* Ty
const llvm::APInt& DemandedElts
bool Insert
bool Extract

¶llvm::InstructionCost getScalingFactorCost(
    llvm::Type* Ty,
    llvm::GlobalValue* BaseGV,
    int64_t BaseOffset,
    bool HasBaseReg,
    int64_t Scale,
    unsigned int AddrSpace = 0) const

Description

Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. If the AM is supported, the return value must be >= 0. If the AM is not supported, it returns a negative value. TODO: Handle pre/postinc as well.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:725

Parameters

llvm::Type* Ty
llvm::GlobalValue* BaseGV
int64_t BaseOffset
bool HasBaseReg
int64_t Scale
unsigned int AddrSpace = 0

¶llvm::InstructionCost getShuffleCost(
    llvm::TargetTransformInfo::ShuffleKind Kind,
    llvm::VectorType* Tp,
    ArrayRef<int> Mask = None,
    int Index = 0,
    llvm::VectorType* SubTp = nullptr,
    ArrayRef<const llvm::Value*> Args =
        None) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1088

Parameters

llvm::TargetTransformInfo::ShuffleKind Kind
llvm::VectorType* Tp
ArrayRef<int> Mask = None
int Index = 0
llvm::VectorType* SubTp = nullptr
ArrayRef<const llvm::Value*> Args = None

Returns

The cost of a shuffle instruction of kind Kind and of type Tp. The exact mask may be passed as Mask, or else the array will be empty. The index and subtype parameters are used by the subvector insertion and extraction shuffle kinds to show the insert/extract point and the type of the subvector being inserted/extracted. The operands of the shuffle can be passed through \p Args, which helps improve the cost estimation in some cases, like in broadcast loads. NOTE: For subvector extractions Tp represents the source type.

¶unsigned int getStoreMinimumVF(
    unsigned int VF,
    llvm::Type* ScalarMemTy,
    llvm::Type* ScalarValTy) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:983

Parameters

unsigned int VF: Initial estimation of the minimum vector factor.
llvm::Type* ScalarMemTy: Scalar memory type of the store operation.
llvm::Type* ScalarValTy: Scalar type of the stored value. Currently only used by the SLP vectorizer.

Returns

The minimum vectorization factor for the store instruction. Given the initial estimation of the minimum vector factor and store value type, it tries to find possible lowest VF, which still might be profitable for the vectorization.

¶unsigned int getStoreVectorFactor(
    unsigned int VF,
    unsigned int StoreSize,
    unsigned int ChainSizeInBytes,
    llvm::VectorType* VecTy) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1403

Parameters

unsigned int VF
unsigned int StoreSize
unsigned int ChainSizeInBytes
llvm::VectorType* VecTy

Returns

The new vector factor value if the target doesn't support \p SizeInBytes stores or has a better vector factor.

¶bool getTgtMemIntrinsic(
    llvm::IntrinsicInst* Inst,
    llvm::MemIntrinsicInfo& Info) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1311

Parameters

llvm::IntrinsicInst* Inst
llvm::MemIntrinsicInfo& Info

Returns

True if the intrinsic is a supported memory intrinsic. Info will contain additional information - whether the intrinsic may write or read to memory, volatility and the pointer. Info is undefined if false is returned.

¶void getUnrollingPreferences(
    llvm::Loop* L,
    llvm::ScalarEvolution&,
    llvm::TargetTransformInfo::
        UnrollingPreferences& UP,
    llvm::OptimizationRemarkEmitter* ORE) const

Description

Get target-customized preferences for the generic loop unrolling transformation. The caller will initialize UP with the current target-independent defaults.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:519

Parameters

llvm::Loop* L
llvm::ScalarEvolution&
llvm::TargetTransformInfo::UnrollingPreferences& UP
llvm::OptimizationRemarkEmitter* ORE

¶llvm::InstructionCost getUserCost(
    const llvm::User* U,
    ArrayRef<const llvm::Value*> Operands,
    llvm::TargetTransformInfo::TargetCostKind
        CostKind) const

Description

Estimate the cost of a given IR user when lowered. This can estimate the cost of either a ConstantExpr or Instruction when lowered. \p Operands is a list of operands which can be a result of transformations of the current operands. The number of the operands on the list must equal to the number of the current operands the IR user has. Their order on the list must be the same as the order of the current operands the IR user has. The returned cost is defined in terms of \c TargetCostConstants, see its comments for a detailed explanation of the cost values.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:324

Parameters

const llvm::User* U
ArrayRef<const llvm::Value*> Operands
llvm::TargetTransformInfo::TargetCostKind CostKind

¶llvm::InstructionCost getUserCost(
    const llvm::User* U,
    llvm::TargetTransformInfo::TargetCostKind
        CostKind) const

Description

This is a helper function which calls the two-argument getUserCost with \p Operands which are the current operands U has.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:329

Parameters

const llvm::User* U
llvm::TargetTransformInfo::TargetCostKind CostKind

¶llvm::TargetTransformInfo::VPLegalization
getVPLegalizationStrategy(
    const llvm::VPIntrinsic& PI) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1493

Parameters

const llvm::VPIntrinsic& PI

Returns

How the target needs this vector-predicated operation to be transformed.

¶llvm::InstructionCost getVPMemoryOpCost(
    unsigned int Opcode,
    llvm::Type* Src,
    llvm::Align Alignment,
    unsigned int AddressSpace,
    TTI::TargetCostKind CostKind =
        TargetTransformInfo::TCK_RecipThroughput,
    const llvm::Instruction* I = nullptr) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1186

Parameters

unsigned int Opcode
llvm::Type* Src
llvm::Align Alignment
unsigned int AddressSpace
TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput
const llvm::Instruction* I = nullptr

Returns

The cost of VP Load and Store instructions.

¶Optional<unsigned int> getVScaleForTuning() const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:953

Returns

the value of vscale to tune the cost model for.

¶llvm::InstructionCost getVectorInstrCost(
    unsigned int Opcode,
    llvm::Type* Val,
    unsigned int Index = -1) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1164

Parameters

unsigned int Opcode
llvm::Type* Val
unsigned int Index = -1

Returns

The expected cost of vector Insert and Extract. Use -1 to indicate that there is no information on the index value.

¶bool hasActiveVectorLength(
    unsigned int Opcode,
    llvm::Type* DataType,
    llvm::Align Alignment) const

Description

@ { Whether the target supports the %evl parameter of VP intrinsic efficiently in hardware, for the given opcode and type/alignment. (see LLVM Language Reference - "Vector Predication Intrinsics"). Use of %evl is discouraged when that is not the case.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1459

Parameters

unsigned int Opcode
llvm::Type* DataType
llvm::Align Alignment

¶bool hasBranchDivergence() const

Description

Return true if branch divergence exists. Branch divergence has a significantly negative impact on GPU performance when threads in the same wavefront take different paths due to conditional branches.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:343

¶bool hasDivRemOp(llvm::Type* DataType,
                 bool IsSigned) const

Description

Return true if the target has a unified operation to calculate division and remainder. If so, the additional implicit multiplication and subtraction required to calculate a remainder from division are free. This can enable more aggressive transformations for division and remainder than would typically be allowed using throughput or size cost models.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:707

Parameters

llvm::Type* DataType
bool IsSigned

¶bool hasVolatileVariant(
    llvm::Instruction* I,
    unsigned int AddrSpace) const

Description

Return true if the given instruction (assumed to be a memory access instruction) has a volatile variant. If that's the case then we can avoid addrspacecast to generic AS for volatile loads/stores. Default implementation returns false, which prevents address space inference for volatile loads/stores.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:714

Parameters

llvm::Instruction* I
unsigned int AddrSpace

¶bool haveFastSqrt(llvm::Type* Ty) const

Description

Return true if the hardware has a fast square-root instruction.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:849

Parameters

llvm::Type* Ty

¶Optional<llvm::Instruction*> instCombineIntrinsic(
    llvm::InstCombiner& IC,
    llvm::IntrinsicInst& II) const

Description

Targets can implement their own combinations for target-specific intrinsics. This function will be called from the InstCombine pass every time a target-specific intrinsic is encountered.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:574

Parameters

llvm::InstCombiner& IC
llvm::IntrinsicInst& II

Returns

None to not do anything target specific or a value that will be returned from the InstCombiner. It is possible to return null and stop further processing of the intrinsic by returning nullptr.

¶bool invalidate(
    llvm::Function&,
    const llvm::PreservedAnalyses&,
    FunctionAnalysisManager::Invalidator&)

Description

Handle the invalidation of this information. When used as a result of \c TargetIRAnalysis this method will be called when the function this was computed for changes. When it returns false, the information is preserved across those changes.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:200

Parameters

llvm::Function&
const llvm::PreservedAnalyses&
FunctionAnalysisManager::Invalidator&

¶bool isAlwaysUniform(const llvm::Value* V) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:360

Parameters

const llvm::Value* V

¶bool isElementTypeLegalForScalableVector(
    llvm::Type* Ty) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1393

Parameters

llvm::Type* Ty

Returns

True if the given type is supported for scalable vectors

¶bool isFCmpOrdCheaperThanFCmpZero(
    llvm::Type* Ty) const

Description

Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a comparison against a constant FP zero value. Targets should override this if materializing a 0.0 for comparison is generally as cheap as checking for ordered/unordered.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:855

Parameters

llvm::Type* Ty

¶bool isFPVectorizationPotentiallyUnsafe() const

Description

Indicate that it is potentially unsafe to automatically vectorize floating-point operations because the semantics of vector and scalar floating-point semantics may differ. For example, ARM NEON v7 SIMD math does not support IEEE-754 denormal numbers, while depending on the platform, scalar floating-point math does. This applies to floating-point math operations and calls, not memory operations, shuffles, or casts.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:837

¶bool isHardwareLoopProfitable(
    llvm::Loop* L,
    llvm::ScalarEvolution& SE,
    llvm::AssumptionCache& AC,
    llvm::TargetLibraryInfo* LibInfo,
    llvm::HardwareLoopInfo& HWLoopInfo) const

Description

Query the target whether it would be profitable to convert the given loop into a hardware loop.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:525

Parameters

llvm::Loop* L
llvm::ScalarEvolution& SE
llvm::AssumptionCache& AC
llvm::TargetLibraryInfo* LibInfo
llvm::HardwareLoopInfo& HWLoopInfo

¶bool isIndexedLoadLegal(enum MemIndexedMode Mode,
                        llvm::Type* Ty) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1365

Parameters

enum MemIndexedMode Mode
llvm::Type* Ty

Returns

True if the specified indexed load for the given type is legal.

¶bool isIndexedStoreLegal(enum MemIndexedMode Mode,
                         llvm::Type* Ty) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1368

Parameters

enum MemIndexedMode Mode
llvm::Type* Ty

Returns

True if the specified indexed store for the given type is legal.

¶bool isLSRCostLess(
    const TargetTransformInfo::LSRCost& C1,
    const TargetTransformInfo::LSRCost& C2) const

Description

Return true if LSR cost of C1 is lower than C1.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:627

Parameters

const TargetTransformInfo::LSRCost& C1
const TargetTransformInfo::LSRCost& C2

¶bool isLegalAddImmediate(int64_t Imm) const

Description

Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register with the immediate without having to materialize the immediate into a register.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:607

Parameters

int64_t Imm

¶bool isLegalAddressingMode(
    llvm::Type* Ty,
    llvm::GlobalValue* BaseGV,
    int64_t BaseOffset,
    bool HasBaseReg,
    int64_t Scale,
    unsigned int AddrSpace = 0,
    llvm::Instruction* I = nullptr) const

Description

Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type. The type may be VoidTy, in which case only return true if the addressing mode is legal for a load/store of any legal type. If target returns true in LSRWithInstrQueries(), I may be valid. TODO: Handle pre/postinc as well.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:621

Parameters

llvm::Type* Ty
llvm::GlobalValue* BaseGV
int64_t BaseOffset
bool HasBaseReg
int64_t Scale
unsigned int AddrSpace = 0
llvm::Instruction* I = nullptr

¶bool isLegalAltInstr(
    llvm::VectorType* VecTy,
    unsigned int Opcode0,
    unsigned int Opcode1,
    const llvm::SmallBitVector& OpcodeMask) const

Description

Return true if this is an alternating opcode pattern that can be lowered to a single instruction on the target. In X86 this is for the addsub instruction which corrsponds to a Shuffle + Fadd + FSub pattern in IR. This function expectes two opcodes: \p Opcode1 and \p Opcode2 being selected by \p OpcodeMask. The mask contains one bit per lane and is a `0` when \p Opcode0 is selected and `1` when Opcode1 is selected.\p VecTy is the vector type of the instruction to be generated.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:696

Parameters

llvm::VectorType* VecTy
unsigned int Opcode0
unsigned int Opcode1
const llvm::SmallBitVector& OpcodeMask

¶bool isLegalBroadcastLoad(
    llvm::Type* ElementTy,
    llvm::ElementCount NumElements) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:671

Parameters

llvm::Type* ElementTy
llvm::ElementCount NumElements

Returns

true if the target supports broadcasting a load to a vector of type <NumElements x ElementTy>.

¶bool isLegalICmpImmediate(int64_t Imm) const

Description

Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:613

Parameters

int64_t Imm

¶bool isLegalMaskedCompressStore(
    llvm::Type* DataType) const

Description

Return true if the target supports masked compress store.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:685

Parameters

llvm::Type* DataType

¶bool isLegalMaskedExpandLoad(
    llvm::Type* DataType) const

Description

Return true if the target supports masked expand load.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:687

Parameters

llvm::Type* DataType

¶bool isLegalMaskedGather(
    llvm::Type* DataType,
    llvm::Align Alignment) const

Description

Return true if the target supports masked gather.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:676

Parameters

llvm::Type* DataType
llvm::Align Alignment

¶bool isLegalMaskedLoad(
    llvm::Type* DataType,
    llvm::Align Alignment) const

Description

Return true if the target supports masked load.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:662

Parameters

llvm::Type* DataType
llvm::Align Alignment

¶bool isLegalMaskedScatter(
    llvm::Type* DataType,
    llvm::Align Alignment) const

Description

Return true if the target supports masked scatter.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:674

Parameters

llvm::Type* DataType
llvm::Align Alignment

¶bool isLegalMaskedStore(
    llvm::Type* DataType,
    llvm::Align Alignment) const

Description

Return true if the target supports masked store.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:660

Parameters

llvm::Type* DataType
llvm::Align Alignment

¶bool isLegalNTLoad(llvm::Type* DataType,
                   llvm::Align Alignment) const

Description

Return true if the target supports nontemporal load.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:667

Parameters

llvm::Type* DataType
llvm::Align Alignment

¶bool isLegalNTStore(llvm::Type* DataType,
                    llvm::Align Alignment) const

Description

Return true if the target supports nontemporal store.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:665

Parameters

llvm::Type* DataType
llvm::Align Alignment

¶bool isLegalToVectorizeLoad(
    llvm::LoadInst* LI) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1375

Parameters

llvm::LoadInst* LI

Returns

True if the load instruction is legal to vectorize.

¶bool isLegalToVectorizeLoadChain(
    unsigned int ChainSizeInBytes,
    llvm::Align Alignment,
    unsigned int AddrSpace) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1381

Parameters

unsigned int ChainSizeInBytes
llvm::Align Alignment
unsigned int AddrSpace

Returns

True if it is legal to vectorize the given load chain.

¶bool isLegalToVectorizeReduction(
    const llvm::RecurrenceDescriptor& RdxDesc,
    llvm::ElementCount VF) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1389

Parameters

const llvm::RecurrenceDescriptor& RdxDesc
llvm::ElementCount VF

Returns

True if it is legal to vectorize the given reduction kind.

¶bool isLegalToVectorizeStore(
    llvm::StoreInst* SI) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1378

Parameters

llvm::StoreInst* SI

Returns

True if the store instruction is legal to vectorize.

¶bool isLegalToVectorizeStoreChain(
    unsigned int ChainSizeInBytes,
    llvm::Align Alignment,
    unsigned int AddrSpace) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1385

Parameters

unsigned int ChainSizeInBytes
llvm::Align Alignment
unsigned int AddrSpace

Returns

True if it is legal to vectorize the given store chain.

¶bool isLoweredToCall(
    const llvm::Function* F) const

Description

Test whether calls to a function lower to actual program function calls. The idea is to test whether the program is likely to require a 'call' instruction or equivalent in order to call the given function. FIXME: It's not clear that this is a good or useful query API. Client's should probably move to simpler cost metrics using the above. Alternatively, we could split the cost interface into distinct code-size and execution-speed costs. This would allow modelling the core of this query more accurately as a call is a single small instruction, but incurs significant execution cost.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:418

Parameters

const llvm::Function* F

¶bool isNoopAddrSpaceCast(unsigned int FromAS,
                         unsigned int ToAS) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:387

Parameters

unsigned int FromAS
unsigned int ToAS

¶bool isNumRegsMajorCostOfLSR() const

Description

Return true if LSR major cost is number of registers. Targets which implement their own isLSRCostLess and unset number of registers as major cost should return false, otherwise return true.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:633

¶bool isProfitableLSRChainElement(
    llvm::Instruction* I) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:636

Parameters

llvm::Instruction* I

Returns

true if LSR should not optimize a chain that includes \p I.

¶bool isProfitableToHoist(
    llvm::Instruction* I) const

Description

Return true if it is profitable to hoist instruction in the then/else to before if.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:743

Parameters

llvm::Instruction* I

¶bool isSourceOfDivergence(
    const llvm::Value* V) const

Description

Returns whether V is a source of divergence. This function provides the target-dependent information for the target-independent LegacyDivergenceAnalysis. LegacyDivergenceAnalysis first builds the dependency graph, and then runs the reachability algorithm starting with the sources of divergence.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:355

Parameters

const llvm::Value* V

¶bool isTruncateFree(llvm::Type* Ty1,
                    llvm::Type* Ty2) const

Description

Return true if it's free to truncate a value of type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16 by referencing its sub-register AX.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:739

Parameters

llvm::Type* Ty1
llvm::Type* Ty2

¶bool isTypeLegal(llvm::Type* Ty) const

Description

Return true if this type is legal.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:748

Parameters

llvm::Type* Ty

¶bool preferInLoopReduction(
    unsigned int Opcode,
    llvm::Type* Ty,
    llvm::TargetTransformInfo::ReductionFlags
        Flags) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1418

Parameters

unsigned int Opcode
llvm::Type* Ty
llvm::TargetTransformInfo::ReductionFlags Flags

Returns

True if the target prefers reductions in loop.

¶bool preferPredicateOverEpilogue(
    llvm::Loop* L,
    llvm::LoopInfo* LI,
    llvm::ScalarEvolution& SE,
    llvm::AssumptionCache& AC,
    llvm::TargetLibraryInfo* TLI,
    llvm::DominatorTree* DT,
    llvm::LoopVectorizationLegality* LVL) const

Description

Query the target whether it would be prefered to create a predicated vector loop, which can avoid the need to emit a scalar epilogue loop.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:531

Parameters

llvm::Loop* L
llvm::LoopInfo* LI
llvm::ScalarEvolution& SE
llvm::AssumptionCache& AC
llvm::TargetLibraryInfo* TLI
llvm::DominatorTree* DT
llvm::LoopVectorizationLegality* LVL

¶bool preferPredicatedReductionSelect(
    unsigned int Opcode,
    llvm::Type* Ty,
    llvm::TargetTransformInfo::ReductionFlags
        Flags) const

Description

As opposed to the normal scheme of p = phi (0, a) which allows the select to be pulled out of the loop. If the select(.., add, ..) can be predicated by the target, this can lead to cleaner code generation.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1432

Parameters

unsigned int Opcode
llvm::Type* Ty
llvm::TargetTransformInfo::ReductionFlags Flags

Returns

True if the target prefers reductions select kept in the loop when tail folding. i.e. loop: p = phi (0, s) a = add (p, x) s = select (mask, a, p) vecreduce.add(s)

¶bool prefersVectorizedAddressing() const

Description

Return true if target doesn't mind addresses in vectors.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:717

¶static bool requiresOrderedReduction(
    Optional<llvm::FastMathFlags> FMF)

Description

A helper function to determine the type of reduction algorithm used for a given \p Opcode and set of FastMathFlags \p FMF.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1228

Parameters

Optional<llvm::FastMathFlags> FMF

¶llvm::Value* rewriteIntrinsicWithAddressSpace(
    llvm::IntrinsicInst* II,
    llvm::Value* OldV,
    llvm::Value* NewV) const

Description

Rewrite intrinsic call \p II such that \p OldV will be replaced with \p NewV, which has a different address space. This should happen for every operand index that collectFlatAddressOperands returned for the intrinsic.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:403

Parameters

llvm::IntrinsicInst* II
llvm::Value* OldV
llvm::Value* NewV

Returns

nullptr if the intrinsic was not handled. Otherwise, returns the new value (which may be the original \p II with modified operands).

¶bool shouldBuildLookupTables() const

Description

Return true if switches should be turned into lookup tables for the target.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:755

¶bool shouldBuildLookupTablesForConstant(
    llvm::Constant* C) const

Description

Return true if switches should be turned into lookup tables containing this constant value for the target.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:759

Parameters

llvm::Constant* C

¶bool shouldBuildRelLookupTables() const

Description

Return true if lookup tables should be turned into relative lookup tables.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:762

¶bool shouldConsiderAddressTypePromotion(
    const llvm::Instruction& I,
    bool& AllowPromotionWithoutCommonHeader) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:989

Parameters

const llvm::Instruction& I
bool& AllowPromotionWithoutCommonHeader

Returns

True if it should be considered for address type promotion.\p AllowPromotionWithoutCommonHeader Set true if promoting \p I is profitable without finding other extensions fed by the same input.

¶bool shouldExpandReduction(
    const llvm::IntrinsicInst* II) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1437

Parameters

const llvm::IntrinsicInst* II

Returns

True if the target wants to expand the given reduction intrinsic into a shuffle sequence.

¶bool shouldMaximizeVectorBandwidth(
    TargetTransformInfo::RegisterKind K) const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:962

Parameters

TargetTransformInfo::RegisterKind K

Returns

True if the vectorization factor should be chosen to make the vector of the smallest element type match the size of a vector register. For wider element types, this could result in creating vectors that span multiple vector registers. If false, the vectorization factor will be chosen based on the size of the widest element type.\p K Register Kind for vectorization.

¶Optional<llvm::Value*>
simplifyDemandedUseBitsIntrinsic(
    llvm::InstCombiner& IC,
    llvm::IntrinsicInst& II,
    llvm::APInt DemandedMask,
    llvm::KnownBits& Known,
    bool& KnownBitsComputed) const

Description

Can be used to implement target-specific instruction combining.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:579

Parameters

llvm::InstCombiner& IC
llvm::IntrinsicInst& II
llvm::APInt DemandedMask
llvm::KnownBits& Known
bool& KnownBitsComputed

¶Optional<llvm::Value*>
simplifyDemandedVectorEltsIntrinsic(
    llvm::InstCombiner& IC,
    llvm::IntrinsicInst& II,
    llvm::APInt DemandedElts,
    llvm::APInt& UndefElts,
    llvm::APInt& UndefElts2,
    llvm::APInt& UndefElts3,
    std::function<void(Instruction*,
                       unsigned int,
                       APInt,
                       APInt&)> SimplifyAndSetOp)
    const

Description

Can be used to implement target-specific instruction combining.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:584

Parameters

llvm::InstCombiner& IC
llvm::IntrinsicInst& II
llvm::APInt DemandedElts
llvm::APInt& UndefElts
llvm::APInt& UndefElts2
llvm::APInt& UndefElts3
std::function<void(Instruction*, unsigned int, APInt, APInt&)> SimplifyAndSetOp

¶bool supportsEfficientVectorElementLoadStore()
    const

Description

If target has efficient vector element load/store instructions, it can return true here so that insertion/extraction costs are not added to the scalarization cost of a load/store.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:784

¶bool supportsScalableVectors() const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:1448

Returns

True if the target supports scalable vectors.

¶bool supportsTailCalls() const

Description

If the target supports tail calls.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:787

¶bool useAA() const

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:745

¶bool useColdCCForColdCall(llvm::Function& F) const

Description

Return true if the input function which is cold at all call sites, should use coldcc calling convention.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:766

Parameters

llvm::Function& F

¶bool useGPUDivergenceAnalysis() const

Description

Return true if the target prefers to use GPU divergence analysis to replace the legacy version.

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:347

¶~TargetTransformInfo()

Declared at: llvm/include/llvm/Analysis/TargetTransformInfo.h:193

class TargetTransformInfo

Declaration

Description

Member Variables

Method Overview

Methods

¶bool LSRWithInstrQueries() const

Description

¶TargetTransformInfo( llvm::TargetTransformInfo&& Arg)

Parameters

¶template <typename T> TargetTransformInfo(T Impl)

Description

Templates

Parameters

¶TargetTransformInfo(const llvm::DataLayout& DL)

Description

Parameters

¶unsigned int adjustInliningThreshold( const llvm::CallBase* CB) const

Parameters

Returns

¶bool allowsMisalignedMemoryAccesses( llvm::LLVMContext& Context, unsigned int BitWidth, unsigned int AddressSpace = 0, llvm::Align Alignment = llvm::Align(1), bool* Fast = nullptr) const

Description

Parameters

¶bool areInlineCompatible( const llvm::Function* Caller, const llvm::Function* Callee) const

Parameters

Returns

¶bool areTypesABICompatible( const llvm::Function* Caller, const llvm::Function* Callee, const ArrayRef<llvm::Type*>& Types) const

Parameters

Returns

¶bool canHaveNonUndefGlobalInitializerInAddressSpace( unsigned int AS) const

Description

Parameters

¶bool canMacroFuseCmp() const

Description

¶bool canSaveCmp( llvm::Loop* L, llvm::BranchInst** BI, llvm::ScalarEvolution* SE, llvm::LoopInfo* LI, llvm::DominatorTree* DT, llvm::AssumptionCache* AC, llvm::TargetLibraryInfo* LibInfo) const

Description

Parameters

¶bool collectFlatAddressOperands( SmallVectorImpl<int>& OpIndexes, Intrinsic::ID IID) const

Description

Parameters

Returns

¶llvm::PredicationStyle emitGetActiveLaneMask() const

Description

¶bool enableAggressiveInterleaving( bool LoopHasReductions) const

Description

Parameters

¶bool enableInterleavedAccessVectorization() const

Description

¶bool enableMaskedInterleavedAccessVectorization() const

Description

¶llvm::TargetTransformInfo::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const

Parameters

¶bool enableOrderedReductions() const

Description

¶bool enableScalableVectorization() const

Returns

¶bool enableWritePrefetching() const

Returns

¶bool forceScalarizeMaskedGather( llvm::VectorType* Type, llvm::Align Alignment) const

Description

Parameters

¶bool forceScalarizeMaskedScatter( llvm::VectorType* Type, llvm::Align Alignment) const

Description

Parameters

¶llvm::InstructionCost getAddressComputationCost( llvm::Type* Ty, llvm::ScalarEvolution* SE = nullptr, const llvm::SCEV* Ptr = nullptr) const

Parameters

Returns

Description

Parameters

¶llvm::InstructionCost getArithmeticReductionCost( unsigned int Opcode, llvm::VectorType* Ty, Optional<llvm::FastMathFlags> FMF, TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput) const

Description

Parameters

¶unsigned int getAssumedAddrSpace( const llvm::Value* V) const

Parameters

¶unsigned int getAtomicMemIntrinsicMaxElementSize() const

Returns

¶llvm::InstructionCost getCFInstrCost( unsigned int Opcode, TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_SizeAndLatency, const llvm::Instruction* I = nullptr) const

Parameters

Returns

¶Optional<unsigned int> getCacheAssociativity( llvm::TargetTransformInfo::CacheLevel Level) const

¶`bool LSRWithInstrQueries() const`

¶`TargetTransformInfo( llvm::TargetTransformInfo&& Arg)`

¶`template <typename T> TargetTransformInfo(T Impl)`

¶`TargetTransformInfo(const llvm::DataLayout& DL)`

¶`unsigned int adjustInliningThreshold( const llvm::CallBase* CB) const`

¶`bool allowsMisalignedMemoryAccesses( llvm::LLVMContext& Context, unsigned int BitWidth, unsigned int AddressSpace = 0, llvm::Align Alignment = llvm::Align(1), bool* Fast = nullptr) const`

¶`bool areInlineCompatible( const llvm::Function* Caller, const llvm::Function* Callee) const`

¶`bool areTypesABICompatible( const llvm::Function* Caller, const llvm::Function* Callee, const ArrayRef<llvm::Type*>& Types) const`

¶`bool canHaveNonUndefGlobalInitializerInAddressSpace( unsigned int AS) const`

¶`bool canMacroFuseCmp() const`

¶`bool canSaveCmp( llvm::Loop* L, llvm::BranchInst** BI, llvm::ScalarEvolution* SE, llvm::LoopInfo* LI, llvm::DominatorTree* DT, llvm::AssumptionCache* AC, llvm::TargetLibraryInfo* LibInfo) const`

¶`bool collectFlatAddressOperands( SmallVectorImpl<int>& OpIndexes, Intrinsic::ID IID) const`

¶`llvm::PredicationStyle emitGetActiveLaneMask() const`

¶`bool enableAggressiveInterleaving( bool LoopHasReductions) const`

¶`bool enableInterleavedAccessVectorization() const`

¶`bool enableMaskedInterleavedAccessVectorization() const`

¶`llvm::TargetTransformInfo::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const`

¶`bool enableOrderedReductions() const`

¶`bool enableScalableVectorization() const`

¶`bool enableWritePrefetching() const`

¶`bool forceScalarizeMaskedGather( llvm::VectorType* Type, llvm::Align Alignment) const`

¶`bool forceScalarizeMaskedScatter( llvm::VectorType* Type, llvm::Align Alignment) const`

¶`llvm::InstructionCost getAddressComputationCost( llvm::Type* Ty, llvm::ScalarEvolution* SE = nullptr, const llvm::SCEV* Ptr = nullptr) const`

¶`llvm::InstructionCost getArithmeticReductionCost( unsigned int Opcode, llvm::VectorType* Ty, Optional<llvm::FastMathFlags> FMF, TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput) const`

¶`unsigned int getAssumedAddrSpace( const llvm::Value* V) const`

¶`unsigned int getAtomicMemIntrinsicMaxElementSize() const`

¶`llvm::InstructionCost getCFInstrCost( unsigned int Opcode, TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_SizeAndLatency, const llvm::Instruction* I = nullptr) const`

¶`Optional<unsigned int> getCacheAssociativity( llvm::TargetTransformInfo::CacheLevel Level) const`

¶`unsigned int getCacheLineSize() const`

¶`Optional<unsigned int> getCacheSize( llvm::TargetTransformInfo::CacheLevel Level) const`

¶`llvm::InstructionCost getCallInstrCost( llvm::Function* F, llvm::Type* RetTy, ArrayRef<llvm::Type*> Tys, TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_SizeAndLatency) const`

¶`static llvm::TargetTransformInfo::CastContextHint getCastContextHint(const llvm::Instruction* I)`

¶`llvm::InstructionCost getCastInstrCost( unsigned int Opcode, llvm::Type* Dst, llvm::Type* Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_SizeAndLatency, const llvm::Instruction* I = nullptr) const`

¶`llvm::InstructionCost getCmpSelInstrCost( unsigned int Opcode, llvm::Type* ValTy, llvm::Type* CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput, const llvm::Instruction* I = nullptr) const`

¶`llvm::InstructionCost getCostOfKeepingLiveOverCall( ArrayRef<llvm::Type*> Tys) const`

¶`unsigned int getEstimatedNumberOfCaseClusters( const llvm::SwitchInst& SI, unsigned int& JTSize, llvm::ProfileSummaryInfo* PSI, llvm::BlockFrequencyInfo* BFI) const`

¶`llvm::InstructionCost getExtendedAddReductionCost( bool IsMLA, bool IsUnsigned, llvm::Type* ResTy, llvm::VectorType* Ty, TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput) const`

¶`llvm::InstructionCost getExtractWithExtendCost( unsigned int Opcode, llvm::Type* Dst, llvm::VectorType* VecTy, unsigned int Index = -1) const`

¶`llvm::InstructionCost getFPOpCost( llvm::Type* Ty) const`

¶`unsigned int getFlatAddressSpace() const`

¶`llvm::InstructionCost getGEPCost( llvm::Type* PointeeType, const llvm::Value* Ptr, ArrayRef<const llvm::Value*> Operands, llvm::TargetTransformInfo::TargetCostKind CostKind = TCK_SizeAndLatency) const`

¶`unsigned int getGISelRematGlobalCost() const`

¶`llvm::InstructionCost getGatherScatterOpCost( unsigned int Opcode, llvm::Type* DataTy, const llvm::Value* Ptr, bool VariableMask, llvm::Align Alignment, TTI::TargetCostKind CostKind = TargetTransformInfo::TCK_RecipThroughput, const llvm::Instruction* I = nullptr) const`

¶`int getInlinerVectorBonusPercent() const`

¶`unsigned int getInliningThresholdMultiplier() const`

¶`llvm::InstructionCost getInstructionCost( const llvm::Instruction* I, enum TargetCostKind kind) const`

¶`llvm::InstructionCost getInstructionLatency( const llvm::Instruction* I) const`

¶`llvm::InstructionCost getInstructionThroughput( const llvm::Instruction* I) const`

¶`llvm::InstructionCost getIntImmCodeSizeCost( unsigned int Opc, unsigned int Idx, const llvm::APInt& Imm, llvm::Type* Ty) const`

¶`llvm::InstructionCost getIntImmCost( const llvm::APInt& Imm, llvm::Type* Ty, llvm::TargetTransformInfo::TargetCostKind CostKind) const`

¶`llvm::InstructionCost getIntImmCostInst( unsigned int Opc, unsigned int Idx, const llvm::APInt& Imm, llvm::Type* Ty, llvm::TargetTransformInfo::TargetCostKind CostKind, llvm::Instruction* Inst = nullptr) const`