class DispatchStage

Declaration

class DispatchStage : public Stage { /* full declaration omitted */ };

Declared at: llvm/include/llvm/MCA/Stages/DispatchStage.h:49

Inherits from: Stage

Member Variables

private unsigned int DispatchWidth

private unsigned int AvailableEntries

private unsigned int CarryOver

private llvm::mca::InstRef CarriedOver

private const llvm::MCSubtargetInfo& STI

private llvm::mca::RetireControlUnit& RCU

private llvm::mca::RegisterFile& PRF

Method Overview

• public DispatchStage(const llvm::MCSubtargetInfo & Subtarget, const llvm::MCRegisterInfo & MRI, unsigned int MaxDispatchWidth, llvm::mca::RetireControlUnit & R, llvm::mca::RegisterFile & F)
• private bool canDispatch(const llvm::mca::InstRef & IR) const
• private bool checkPRF(const llvm::mca::InstRef & IR) const
• private bool checkRCU(const llvm::mca::InstRef & IR) const
• public llvm::Error cycleStart()
• private llvm::Error dispatch(llvm::mca::InstRef IR)
• public void dump() const
• public llvm::Error execute(llvm::mca::InstRef & IR)
• public bool hasWorkToComplete() const
• public bool isAvailable(const llvm::mca::InstRef & IR) const
• private void notifyInstructionDispatched(const llvm::mca::InstRef & IR, ArrayRef<unsigned int> UsedPhysRegs, unsigned int uOps) const

Inherited from Stage:

• public addListener
• public checkNextStage
• public cycleEnd
• public cycleResume
• public cycleStart
• public execute
• protected getListeners
• public hasWorkToComplete
• public isAvailable
• public moveToTheNextStage
• public notifyEvent
• public setNextInSequence

Methods

¶DispatchStage(
    const llvm::MCSubtargetInfo& Subtarget,
    const llvm::MCRegisterInfo& MRI,
    unsigned int MaxDispatchWidth,
    llvm::mca::RetireControlUnit& R,
    llvm::mca::RegisterFile& F)

Declared at: llvm/include/llvm/MCA/Stages/DispatchStage.h:68

Parameters

const llvm::MCSubtargetInfo& Subtarget

const llvm::MCRegisterInfo& MRI

unsigned int MaxDispatchWidth

llvm::mca::RetireControlUnit& R

llvm::mca::RegisterFile& F

¶bool canDispatch(
    const llvm::mca::InstRef& IR) const

Declared at: llvm/include/llvm/MCA/Stages/DispatchStage.h:60

Parameters

const llvm::mca::InstRef& IR

¶bool checkPRF(const llvm::mca::InstRef& IR) const

Declared at: llvm/include/llvm/MCA/Stages/DispatchStage.h:59

Parameters

const llvm::mca::InstRef& IR

¶bool checkRCU(const llvm::mca::InstRef& IR) const

Declared at: llvm/include/llvm/MCA/Stages/DispatchStage.h:58

Parameters

const llvm::mca::InstRef& IR

¶llvm::Error cycleStart()

Description

Called once at the start of each cycle. This can be used as a setup phase to prepare for the executions during the cycle.

Declared at: llvm/include/llvm/MCA/Stages/DispatchStage.h:77

¶llvm::Error dispatch(llvm::mca::InstRef IR)

Declared at: llvm/include/llvm/MCA/Stages/DispatchStage.h:61

Parameters

llvm::mca::InstRef IR

¶void dump() const

Declared at: llvm/include/llvm/MCA/Stages/DispatchStage.h:81

¶llvm::Error execute(llvm::mca::InstRef& IR)

Description

The primary action that this stage performs on instruction IR.

Declared at: llvm/include/llvm/MCA/Stages/DispatchStage.h:78

Parameters

llvm::mca::InstRef& IR

¶bool hasWorkToComplete() const

Description

Returns true if some instructions are still executing this stage.

Declared at: llvm/include/llvm/MCA/Stages/DispatchStage.h:76

¶bool isAvailable(
    const llvm::mca::InstRef& IR) const

Description

Returns true if it can execute IR during this cycle.

Declared at: llvm/include/llvm/MCA/Stages/DispatchStage.h:72

Parameters

const llvm::mca::InstRef& IR

¶void notifyInstructionDispatched(
    const llvm::mca::InstRef& IR,
    ArrayRef<unsigned int> UsedPhysRegs,
    unsigned int uOps) const

Declared at: llvm/include/llvm/MCA/Stages/DispatchStage.h:63

Parameters

const llvm::mca::InstRef& IR

ArrayRef<unsigned int> UsedPhysRegs

unsigned int uOps