struct X86GenRegisterInfo

Declaration

struct X86GenRegisterInfo : public TargetRegisterInfo { /* full declaration omitted */ };

Description

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDesc objects that represent all of the machine registers that the target has. As such, we simply have to track a pointer to this array so that we can turn register number into a register descriptor.

Declared at: build/lib/Target/X86/X86GenRegisterInfo.inc:4458

Inherits from: TargetRegisterInfo

Member Variables

Method Overview

• public X86GenRegisterInfo(unsigned int RA, unsigned int D = 0, unsigned int E = 0, unsigned int PC = 0, unsigned int HwMode = 0)
• public llvm::LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned int, llvm::LaneBitmask) const
• public unsigned int composeSubRegIndicesImpl(unsigned int, unsigned int) const
• public static const llvm::X86FrameLowering * getFrameLowering(const llvm::MachineFunction & MF)
• public unsigned int getNumRegPressureSets() const
• public const int * getRegClassPressureSets(const llvm::TargetRegisterClass * RC) const
• public const llvm::RegClassWeight & getRegClassWeight(const llvm::TargetRegisterClass * RC) const
• public ArrayRef<const char *> getRegMaskNames() const
• public ArrayRef<const uint32_t *> getRegMasks() const
• public unsigned int getRegPressureSetLimit(const llvm::MachineFunction & MF, unsigned int Idx) const
• public const char * getRegPressureSetName(unsigned int Idx) const
• public const int * getRegUnitPressureSets(unsigned int RegUnit) const
• public unsigned int getRegUnitWeight(unsigned int RegUnit) const
• public const llvm::TargetRegisterClass * getSubClassWithSubReg(const llvm::TargetRegisterClass *, unsigned int) const
• public bool isArgumentRegister(const llvm::MachineFunction &, llvm::MCRegister) const
• public bool isFixedRegister(const llvm::MachineFunction &, llvm::MCRegister) const
• public bool isGeneralPurposeRegister(const llvm::MachineFunction &, llvm::MCRegister) const
• public llvm::LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned int, llvm::LaneBitmask) const

Inherited from TargetRegisterInfo:

• public adjustStackMapLiveOutMask
• public canRealignStack
• public checkAllSuperRegsMarked
• public composeSubRegIndexLaneMask
• protected composeSubRegIndexLaneMaskImpl
• public composeSubRegIndices
• protected composeSubRegIndicesImpl
• public dumpReg
• public eliminateFrameIndex
• public getAllocatableClass
• public getAllocatableSet
• public getCSRFirstUseCost
• public getCallPreservedMask
• public getCalleeSavedRegs
• public getCommonSubClass
• public getCommonSuperRegClass
• public getConstrainedRegClassForOperand
• public getCoveringLanes
• public getCoveringSubRegIndexes
• public getCrossCopyRegClass
• public getCustomEHPadPreservedMask
• public getFrameIndexInstrOffset
• public getFrameRegister
• public getIntraCallClobberedRegs
• public getLargestLegalSuperClass
• public getMatchingSuperReg
• public getMatchingSuperRegClass
• public getMinimalPhysRegClass
• public getMinimalPhysRegClassLLT
• public getNoPreservedMask
• public getNumRegClasses
• public getNumRegPressureSets
• public getOffsetOpcodes
• public getPointerRegClass
• public getRegAllocationHints
• public getRegAsmName
• public getRegClass
• protected getRegClassInfo
• public getRegClassName
• public getRegClassPressureSets
• public getRegClassWeight
• public getRegMaskNames
• public getRegMasks
• public getRegPressureLimit
• public getRegPressureSetLimit
• public getRegPressureSetName
• public getRegPressureSetScore
• public getRegSizeInBits
• public getRegSizeInBits
• public getRegUnitPressureSets
• public getRegUnitWeight
• protected getRegisterCostTableIndex
• public getRegisterCosts
• public getReservedRegs
• public getSpillAlign
• public getSpillSize
• public getSubClassWithSubReg
• public getSubReg
• public getSubRegIndexLaneMask
• public getSubRegIndexName
• public hasRegUnit
• public hasReservedSpillSlot
• public hasStackRealignment
• public isArgumentRegister
• public isAsmClobberable
• public isCalleeSavedPhysReg
• public isCallerPreservedPhysReg
• public isConstantPhysReg
• public isDivergentRegClass
• public isFixedRegister
• public isFrameOffsetLegal
• public isGeneralPurposeRegister
• public isInAllocatableClass
• public isInlineAsmReadOnlyReg
• public isNonallocatableRegisterCalleeSave
• public isTypeLegalForClass
• public isTypeLegalForClass
• public legalclasstypes_begin
• public legalclasstypes_end
• public lookThruCopyLike
• public lookThruSingleUseCopyChain
• public markSuperRegs
• public materializeFrameBaseRegister
• public needsFrameBaseReg
• public prependOffsetExpression
• public regClassPriorityTrumpsGlobalness
• public regclass_begin
• public regclass_end
• public regclasses
• public regmaskSubsetEqual
• public regsOverlap
• public requiresFrameIndexReplacementScavenging
• public requiresFrameIndexScavenging
• public requiresRegisterScavenging
• public requiresVirtualBaseRegisters
• public resolveFrameIndex
• public reverseComposeSubRegIndexLaneMask
• protected reverseComposeSubRegIndexLaneMaskImpl
• public reverseLocalAssignment
• public saveScavengerRegister
• public shouldCoalesce
• public shouldRealignStack
• public shouldRegionSplitForVirtReg
• public shouldRewriteCopySrc
• public shouldUseDeferredSpillingForVirtReg
• public shouldUseLastChanceRecoloringForVirtReg
• public trackLivenessAfterRegAlloc
• public updateRegAllocHint
• public useFPForScavengingIndex

Inherited from MCRegisterInfo:

• public InitMCRegisterInfo
• public get
• public getCodeViewRegNum
• public getDwarfRegNum
• public getDwarfRegNumFromDwarfEHRegNum
• public getEncodingValue
• public getLLVMRegNum
• public getMatchingSuperReg
• public getName
• public getNumRegClasses
• public getNumRegUnits
• public getNumRegs
• public getNumSubRegIndices
• public getProgramCounter
• public getRARegister
• public getRegClass
• public getRegClassName
• public getSEHRegNum
• public getSubReg
• public getSubRegIdxOffset
• public getSubRegIdxSize
• public getSubRegIndex
• public isSubRegister
• public isSubRegisterEq
• public isSuperOrSubRegisterEq
• public isSuperRegister
• public isSuperRegisterEq
• public mapDwarfRegsToLLVMRegs
• public mapLLVMRegToCVReg
• public mapLLVMRegToSEHReg
• public mapLLVMRegsToDwarfRegs
• public regclass_begin
• public regclass_end
• public regclasses
• public regsOverlap
• public sub_and_superregs_inclusive
• public subregs
• public subregs_inclusive
• public superregs
• public superregs_inclusive

Methods

¶X86GenRegisterInfo(unsigned int RA,
                   unsigned int D = 0,
                   unsigned int E = 0,
                   unsigned int PC = 0,
                   unsigned int HwMode = 0)

Declared at: build/lib/Target/X86/X86GenRegisterInfo.inc:4459

Parameters

unsigned int RA

unsigned int D = 0

unsigned int E = 0

unsigned int PC = 0

unsigned int HwMode = 0

¶llvm::LaneBitmask composeSubRegIndexLaneMaskImpl(
    unsigned int,
    llvm::LaneBitmask) const

Description

Overridden by TableGen in targets that have sub-registers.

Declared at: build/lib/Target/X86/X86GenRegisterInfo.inc:4462

Parameters

unsigned int

llvm::LaneBitmask

¶unsigned int composeSubRegIndicesImpl(
    unsigned int,
    unsigned int) const

Description

Overridden by TableGen in targets that have sub-registers.

Declared at: build/lib/Target/X86/X86GenRegisterInfo.inc:4461

Parameters

unsigned int

unsigned int

¶static const llvm::X86FrameLowering*
getFrameLowering(const llvm::MachineFunction& MF)

Description

Devirtualized TargetFrameLowering.

Declared at: build/lib/Target/X86/X86GenRegisterInfo.inc:4478

Parameters

const llvm::MachineFunction& MF

¶unsigned int getNumRegPressureSets() const

Description

Get the number of dimensions of register pressure.

Declared at: build/lib/Target/X86/X86GenRegisterInfo.inc:4467

¶const int* getRegClassPressureSets(
    const llvm::TargetRegisterClass* RC) const

Description

Get the dimensions of register pressure impacted by this register class. Returns a -1 terminated array of pressure set IDs.

Declared at: build/lib/Target/X86/X86GenRegisterInfo.inc:4470

Parameters

const llvm::TargetRegisterClass* RC

¶const llvm::RegClassWeight& getRegClassWeight(
    const llvm::TargetRegisterClass* RC) const

Description

Get the weight in units of pressure for this register class.

Declared at: build/lib/Target/X86/X86GenRegisterInfo.inc:4465

Parameters

const llvm::TargetRegisterClass* RC

¶ArrayRef<const char*> getRegMaskNames() const

Declared at: build/lib/Target/X86/X86GenRegisterInfo.inc:4472

¶ArrayRef<const uint32_t*> getRegMasks() const

Description

Return all the call-preserved register masks defined for this target.

Declared at: build/lib/Target/X86/X86GenRegisterInfo.inc:4473

¶unsigned int getRegPressureSetLimit(
    const llvm::MachineFunction& MF,
    unsigned int Idx) const

Description

Get the register unit pressure limit for this dimension. This limit must be adjusted dynamically for reserved registers.

Declared at: build/lib/Target/X86/X86GenRegisterInfo.inc:4469

Parameters

const llvm::MachineFunction& MF

unsigned int Idx

¶const char* getRegPressureSetName(
    unsigned int Idx) const

Description

Get the name of this register unit pressure set.

Declared at: build/lib/Target/X86/X86GenRegisterInfo.inc:4468

Parameters

unsigned int Idx

¶const int* getRegUnitPressureSets(
    unsigned int RegUnit) const

Description

Get the dimensions of register pressure impacted by this register unit. Returns a -1 terminated array of pressure set IDs.

Declared at: build/lib/Target/X86/X86GenRegisterInfo.inc:4471

Parameters

unsigned int RegUnit

¶unsigned int getRegUnitWeight(
    unsigned int RegUnit) const

Description

Get the weight in units of pressure for this register unit.

Declared at: build/lib/Target/X86/X86GenRegisterInfo.inc:4466

Parameters

unsigned int RegUnit

¶const llvm::TargetRegisterClass*
getSubClassWithSubReg(
    const llvm::TargetRegisterClass*,
    unsigned int) const

Description

Returns the largest legal sub-class of RC that supports the sub-register index Idx. If no such sub-class exists, return NULL. If all registers in RC already have an Idx sub-register, return RC. TableGen generates a version of this function that is good enough in most cases. Targets can override if they have constraints that TableGen doesn't understand. For example, the x86 sub_8bit sub-register index is supported by the full GR32 register class in 64-bit mode, but only by the GR32_ABCD regiister class in 32-bit mode. TableGen will synthesize missing RC sub-classes.

Declared at: build/lib/Target/X86/X86GenRegisterInfo.inc:4464

Parameters

const llvm::TargetRegisterClass*

unsigned int

¶bool isArgumentRegister(
    const llvm::MachineFunction&,
    llvm::MCRegister) const

Description

Returns true if PhysReg can be used as an argument to a function.

Declared at: build/lib/Target/X86/X86GenRegisterInfo.inc:4476

Parameters

const llvm::MachineFunction&

llvm::MCRegister

¶bool isFixedRegister(const llvm::MachineFunction&,
                     llvm::MCRegister) const

Description

Returns true if PhysReg is a fixed register.

Declared at: build/lib/Target/X86/X86GenRegisterInfo.inc:4475

Parameters

const llvm::MachineFunction&

llvm::MCRegister

¶bool isGeneralPurposeRegister(
    const llvm::MachineFunction&,
    llvm::MCRegister) const

Description

Returns true if PhysReg is a general purpose register.

Declared at: build/lib/Target/X86/X86GenRegisterInfo.inc:4474

Parameters

const llvm::MachineFunction&

llvm::MCRegister

¶llvm::LaneBitmask
reverseComposeSubRegIndexLaneMaskImpl(
    unsigned int,
    llvm::LaneBitmask) const

Declared at: build/lib/Target/X86/X86GenRegisterInfo.inc:4463

Parameters

unsigned int

llvm::LaneBitmask