class TargetRegisterInfo

Declaration

class TargetRegisterInfo : public MCRegisterInfo { /* full declaration omitted */ };

Description

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDesc objects that represent all of the machine registers that the target has. As such, we simply have to track a pointer to this array so that we can turn register number into a register descriptor.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:234

Inherits from: MCRegisterInfo

Member Variables

private const llvm::TargetRegisterInfoDesc* InfoDesc

private const char* const* SubRegIndexNames

private const llvm::LaneBitmask* SubRegIndexLaneMasks

private llvm::TargetRegisterInfo::regclass_iterator RegClassBegin

private llvm::TargetRegisterInfo::regclass_iterator RegClassEnd

private llvm::LaneBitmask CoveringLanes

private const llvm::TargetRegisterInfo:: RegClassInfo* const RCInfos

private unsigned int HwMode

Method Overview

• protected TargetRegisterInfo(const llvm::TargetRegisterInfoDesc * ID, llvm::TargetRegisterInfo::regclass_iterator RCB, llvm::TargetRegisterInfo::regclass_iterator RCE, const char *const * SRINames, const llvm::LaneBitmask * SRILaneMasks, llvm::LaneBitmask CoveringLanes, const llvm::TargetRegisterInfo::RegClassInfo *const RCIs, unsigned int Mode = 0)
• public virtual void adjustStackMapLiveOutMask(uint32_t * Mask) const
• public virtual bool canRealignStack(const llvm::MachineFunction & MF) const
• public bool checkAllSuperRegsMarked(const llvm::BitVector & RegisterSet, ArrayRef<llvm::MCPhysReg> Exceptions = llvm::ArrayRef<unsigned short>()) const
• public llvm::LaneBitmask composeSubRegIndexLaneMask(unsigned int IdxA, llvm::LaneBitmask Mask) const
• protected virtual llvm::LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned int, llvm::LaneBitmask) const
• public unsigned int composeSubRegIndices(unsigned int a, unsigned int b) const
• protected virtual unsigned int composeSubRegIndicesImpl(unsigned int, unsigned int) const
• public static void dumpReg(llvm::Register Reg, unsigned int SubRegIndex = 0, const llvm::TargetRegisterInfo * TRI = nullptr)
• public virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned int FIOperandNum, llvm::RegScavenger * RS = nullptr) const
• public const llvm::TargetRegisterClass * getAllocatableClass(const llvm::TargetRegisterClass * RC) const
• public llvm::BitVector getAllocatableSet(const llvm::MachineFunction & MF, const llvm::TargetRegisterClass * RC = nullptr) const
• public virtual unsigned int getCSRFirstUseCost() const
• public virtual const uint32_t * getCallPreservedMask(const llvm::MachineFunction & MF, CallingConv::ID) const
• public virtual const llvm::MCPhysReg * getCalleeSavedRegs(const llvm::MachineFunction * MF) const
• public const llvm::TargetRegisterClass * getCommonSubClass(const llvm::TargetRegisterClass * A, const llvm::TargetRegisterClass * B) const
• public const llvm::TargetRegisterClass * getCommonSuperRegClass(const llvm::TargetRegisterClass * RCA, unsigned int SubA, const llvm::TargetRegisterClass * RCB, unsigned int SubB, unsigned int & PreA, unsigned int & PreB) const
• public virtual const llvm::TargetRegisterClass * getConstrainedRegClassForOperand(const llvm::MachineOperand & MO, const llvm::MachineRegisterInfo & MRI) const
• public llvm::LaneBitmask getCoveringLanes() const
• public bool getCoveringSubRegIndexes(const llvm::MachineRegisterInfo & MRI, const llvm::TargetRegisterClass * RC, llvm::LaneBitmask LaneMask, SmallVectorImpl<unsigned int> & Indexes) const
• public virtual const llvm::TargetRegisterClass * getCrossCopyRegClass(const llvm::TargetRegisterClass * RC) const
• public virtual const uint32_t * getCustomEHPadPreservedMask(const llvm::MachineFunction & MF) const
• public virtual int64_t getFrameIndexInstrOffset(const llvm::MachineInstr * MI, int Idx) const
• public virtual llvm::Register getFrameRegister(const llvm::MachineFunction & MF) const
• public virtual ArrayRef<llvm::MCPhysReg> getIntraCallClobberedRegs(const llvm::MachineFunction * MF) const
• public virtual const llvm::TargetRegisterClass * getLargestLegalSuperClass(const llvm::TargetRegisterClass * RC, const llvm::MachineFunction &) const
• public llvm::MCRegister getMatchingSuperReg(llvm::MCRegister Reg, unsigned int SubIdx, const llvm::TargetRegisterClass * RC) const
• public virtual const llvm::TargetRegisterClass * getMatchingSuperRegClass(const llvm::TargetRegisterClass * A, const llvm::TargetRegisterClass * B, unsigned int Idx) const
• public const llvm::TargetRegisterClass * getMinimalPhysRegClass(llvm::MCRegister Reg, llvm::MVT VT = MVT::Other) const
• public const llvm::TargetRegisterClass * getMinimalPhysRegClassLLT(llvm::MCRegister Reg, llvm::LLT Ty = llvm::LLT()) const
• public virtual const uint32_t * getNoPreservedMask() const
• public unsigned int getNumRegClasses() const
• public virtual unsigned int getNumRegPressureSets() const
• public virtual void getOffsetOpcodes(const llvm::StackOffset & Offset, SmallVectorImpl<uint64_t> & Ops) const
• public virtual const llvm::TargetRegisterClass * getPointerRegClass(const llvm::MachineFunction & MF, unsigned int Kind = 0) const
• public virtual bool getRegAllocationHints(llvm::Register VirtReg, ArrayRef<llvm::MCPhysReg> Order, SmallVectorImpl<llvm::MCPhysReg> & Hints, const llvm::MachineFunction & MF, const llvm::VirtRegMap * VRM = nullptr, const llvm::LiveRegMatrix * Matrix = nullptr) const
• public virtual llvm::StringRef getRegAsmName(llvm::MCRegister Reg) const
• public const llvm::TargetRegisterClass * getRegClass(unsigned int i) const
• protected const llvm::TargetRegisterInfo::RegClassInfo & getRegClassInfo(const llvm::TargetRegisterClass & RC) const
• public const char * getRegClassName(const llvm::TargetRegisterClass * Class) const
• public virtual const int * getRegClassPressureSets(const llvm::TargetRegisterClass * RC) const
• public virtual const llvm::RegClassWeight & getRegClassWeight(const llvm::TargetRegisterClass * RC) const
• public virtual ArrayRef<const char *> getRegMaskNames() const
• public virtual ArrayRef<const uint32_t *> getRegMasks() const
• public virtual unsigned int getRegPressureLimit(const llvm::TargetRegisterClass * RC, llvm::MachineFunction & MF) const
• public virtual unsigned int getRegPressureSetLimit(const llvm::MachineFunction & MF, unsigned int Idx) const
• public virtual const char * getRegPressureSetName(unsigned int Idx) const
• public virtual unsigned int getRegPressureSetScore(const llvm::MachineFunction & MF, unsigned int PSetID) const
• public unsigned int getRegSizeInBits(const llvm::TargetRegisterClass & RC) const
• public unsigned int getRegSizeInBits(llvm::Register Reg, const llvm::MachineRegisterInfo & MRI) const
• public virtual const int * getRegUnitPressureSets(unsigned int RegUnit) const
• public virtual unsigned int getRegUnitWeight(unsigned int RegUnit) const
• protected virtual unsigned int getRegisterCostTableIndex(const llvm::MachineFunction & MF) const
• public ArrayRef<uint8_t> getRegisterCosts(const llvm::MachineFunction & MF) const
• public virtual llvm::BitVector getReservedRegs(const llvm::MachineFunction & MF) const
• public llvm::Align getSpillAlign(const llvm::TargetRegisterClass & RC) const
• public unsigned int getSpillSize(const llvm::TargetRegisterClass & RC) const
• public virtual const llvm::TargetRegisterClass * getSubClassWithSubReg(const llvm::TargetRegisterClass * RC, unsigned int Idx) const
• public inline llvm::MCRegister getSubReg(llvm::MCRegister Reg, unsigned int Idx) const
• public llvm::LaneBitmask getSubRegIndexLaneMask(unsigned int SubIdx) const
• public const char * getSubRegIndexName(unsigned int SubIdx) const
• public bool hasRegUnit(llvm::MCRegister Reg, llvm::Register RegUnit) const
• public virtual bool hasReservedSpillSlot(const llvm::MachineFunction & MF, llvm::Register Reg, int & FrameIdx) const
• public bool hasStackRealignment(const llvm::MachineFunction & MF) const
• public virtual bool isArgumentRegister(const llvm::MachineFunction & MF, llvm::MCRegister PhysReg) const
• public virtual bool isAsmClobberable(const llvm::MachineFunction & MF, llvm::MCRegister PhysReg) const
• public virtual bool isCalleeSavedPhysReg(llvm::MCRegister PhysReg, const llvm::MachineFunction & MF) const
• public virtual bool isCallerPreservedPhysReg(llvm::MCRegister PhysReg, const llvm::MachineFunction & MF) const
• public virtual bool isConstantPhysReg(llvm::MCRegister PhysReg) const
• public virtual bool isDivergentRegClass(const llvm::TargetRegisterClass * RC) const
• public virtual bool isFixedRegister(const llvm::MachineFunction & MF, llvm::MCRegister PhysReg) const
• public virtual bool isFrameOffsetLegal(const llvm::MachineInstr * MI, llvm::Register BaseReg, int64_t Offset) const
• public virtual bool isGeneralPurposeRegister(const llvm::MachineFunction & MF, llvm::MCRegister PhysReg) const
• public bool isInAllocatableClass(llvm::MCRegister RegNo) const
• public virtual bool isInlineAsmReadOnlyReg(const llvm::MachineFunction & MF, unsigned int PhysReg) const
• public virtual bool isNonallocatableRegisterCalleeSave(llvm::MCRegister Reg) const
• public bool isTypeLegalForClass(const llvm::TargetRegisterClass & RC, llvm::LLT T) const
• public bool isTypeLegalForClass(const llvm::TargetRegisterClass & RC, llvm::MVT T) const
• public llvm::TargetRegisterInfo::vt_iterator legalclasstypes_begin(const llvm::TargetRegisterClass & RC) const
• public llvm::TargetRegisterInfo::vt_iterator legalclasstypes_end(const llvm::TargetRegisterClass & RC) const
• public virtual llvm::Register lookThruCopyLike(llvm::Register SrcReg, const llvm::MachineRegisterInfo * MRI) const
• public virtual llvm::Register lookThruSingleUseCopyChain(llvm::Register SrcReg, const llvm::MachineRegisterInfo * MRI) const
• public void markSuperRegs(llvm::BitVector & RegisterSet, llvm::MCRegister Reg) const
• public virtual llvm::Register materializeFrameBaseRegister(llvm::MachineBasicBlock * MBB, int FrameIdx, int64_t Offset) const
• public virtual bool needsFrameBaseReg(llvm::MachineInstr * MI, int64_t Offset) const
• public llvm::DIExpression * prependOffsetExpression(const llvm::DIExpression * Expr, unsigned int PrependFlags, const llvm::StackOffset & Offset) const
• public virtual bool regClassPriorityTrumpsGlobalness(const llvm::MachineFunction & MF) const
• public llvm::TargetRegisterInfo::regclass_iterator regclass_begin() const
• public llvm::TargetRegisterInfo::regclass_iterator regclass_end() const
• public iterator_range<llvm::TargetRegisterInfo::regclass_iterator> regclasses() const
• public bool regmaskSubsetEqual(const uint32_t * mask0, const uint32_t * mask1) const
• public bool regsOverlap(llvm::Register RegA, llvm::Register RegB) const
• public virtual bool requiresFrameIndexReplacementScavenging(const llvm::MachineFunction & MF) const
• public virtual bool requiresFrameIndexScavenging(const llvm::MachineFunction & MF) const
• public virtual bool requiresRegisterScavenging(const llvm::MachineFunction & MF) const
• public virtual bool requiresVirtualBaseRegisters(const llvm::MachineFunction & MF) const
• public virtual void resolveFrameIndex(llvm::MachineInstr & MI, llvm::Register BaseReg, int64_t Offset) const
• public llvm::LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned int IdxA, llvm::LaneBitmask LaneMask) const
• protected virtual llvm::LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned int, llvm::LaneBitmask) const
• public virtual bool reverseLocalAssignment() const
• public virtual bool saveScavengerRegister(llvm::MachineBasicBlock & MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator & UseMI, const llvm::TargetRegisterClass * RC, llvm::Register Reg) const
• public virtual bool shouldCoalesce(llvm::MachineInstr * MI, const llvm::TargetRegisterClass * SrcRC, unsigned int SubReg, const llvm::TargetRegisterClass * DstRC, unsigned int DstSubReg, const llvm::TargetRegisterClass * NewRC, llvm::LiveIntervals & LIS) const
• public virtual bool shouldRealignStack(const llvm::MachineFunction & MF) const
• public virtual bool shouldRegionSplitForVirtReg(const llvm::MachineFunction & MF, const llvm::LiveInterval & VirtReg) const
• public virtual bool shouldRewriteCopySrc(const llvm::TargetRegisterClass * DefRC, unsigned int DefSubReg, const llvm::TargetRegisterClass * SrcRC, unsigned int SrcSubReg) const
• public virtual bool shouldUseDeferredSpillingForVirtReg(const llvm::MachineFunction & MF, const llvm::LiveInterval & VirtReg) const
• public virtual bool shouldUseLastChanceRecoloringForVirtReg(const llvm::MachineFunction & MF, const llvm::LiveInterval & VirtReg) const
• public virtual bool trackLivenessAfterRegAlloc(const llvm::MachineFunction & MF) const
• public virtual void updateRegAllocHint(llvm::Register Reg, llvm::Register NewReg, llvm::MachineFunction & MF) const
• public virtual bool useFPForScavengingIndex(const llvm::MachineFunction & MF) const
• protected virtual ~TargetRegisterInfo()

Inherited from MCRegisterInfo:

• public InitMCRegisterInfo
• public get
• public getCodeViewRegNum
• public getDwarfRegNum
• public getDwarfRegNumFromDwarfEHRegNum
• public getEncodingValue
• public getLLVMRegNum
• public getMatchingSuperReg
• public getName
• public getNumRegClasses
• public getNumRegUnits
• public getNumRegs
• public getNumSubRegIndices
• public getProgramCounter
• public getRARegister
• public getRegClass
• public getRegClassName
• public getSEHRegNum
• public getSubReg
• public getSubRegIdxOffset
• public getSubRegIdxSize
• public getSubRegIndex
• public isSubRegister
• public isSubRegisterEq
• public isSuperOrSubRegisterEq
• public isSuperRegister
• public isSuperRegisterEq
• public mapDwarfRegsToLLVMRegs
• public mapLLVMRegToCVReg
• public mapLLVMRegToSEHReg
• public mapLLVMRegsToDwarfRegs
• public regclass_begin
• public regclass_end
• public regclasses
• public regsOverlap
• public sub_and_superregs_inclusive
• public subregs
• public subregs_inclusive
• public superregs
• public superregs_inclusive

Methods

¶TargetRegisterInfo(
    const llvm::TargetRegisterInfoDesc* ID,
    llvm::TargetRegisterInfo::regclass_iterator
        RCB,
    llvm::TargetRegisterInfo::regclass_iterator
        RCE,
    const char* const* SRINames,
    const llvm::LaneBitmask* SRILaneMasks,
    llvm::LaneBitmask CoveringLanes,
    const llvm::TargetRegisterInfo::
        RegClassInfo* const RCIs,
    unsigned int Mode = 0)

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:254

Parameters

const llvm::TargetRegisterInfoDesc* ID

llvm::TargetRegisterInfo::regclass_iterator RCB

llvm::TargetRegisterInfo::regclass_iterator RCE

const char* const* SRINames

const llvm::LaneBitmask* SRILaneMasks

llvm::LaneBitmask CoveringLanes

const llvm::TargetRegisterInfo:: RegClassInfo* const RCIs

unsigned int Mode = 0

¶virtual void adjustStackMapLiveOutMask(
    uint32_t* Mask) const

Description

Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opportunity to adjust it (mainly to remove pseudo-registers that should be ignored).

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:584

Parameters

uint32_t* Mask

¶virtual bool canRealignStack(
    const llvm::MachineFunction& MF) const

Description

True if the stack can be realigned for the target.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:940

Parameters

const llvm::MachineFunction& MF

¶bool checkAllSuperRegsMarked(
    const llvm::BitVector& RegisterSet,
    ArrayRef<llvm::MCPhysReg> Exceptions =
        llvm::ArrayRef<unsigned short>()) const

Description

Returns true if for every register in the set all super registers are part of the set as well.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:1101

Parameters

const llvm::BitVector& RegisterSet

ArrayRef<llvm::MCPhysReg> Exceptions = llvm::ArrayRef<unsigned short>()

¶llvm::LaneBitmask composeSubRegIndexLaneMask(
    unsigned int IdxA,
    llvm::LaneBitmask Mask) const

Description

Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when composing the subsubregisters with IdxA first.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:651

Parameters

unsigned int IdxA

llvm::LaneBitmask Mask

¶virtual llvm::LaneBitmask
composeSubRegIndexLaneMaskImpl(
    unsigned int,
    llvm::LaneBitmask) const

Description

Overridden by TableGen in targets that have sub-registers.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:684

Parameters

unsigned int

llvm::LaneBitmask

¶unsigned int composeSubRegIndices(
    unsigned int a,
    unsigned int b) const

Description

Return the subregister index you get from composing two subregister indices. The special null sub-register index composes as the identity. If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) returns c. Note that composeSubRegIndices does not tell you about illegal compositions. If R does not have a subreg a, or R:a does not have a subreg b, composeSubRegIndices doesn't tell you. The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has ssub_0:S0 - ssub_3:S3 subregs. If you compose subreg indices dsub_1, ssub_0 you get ssub_2.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:642

Parameters

unsigned int a

unsigned int b

¶virtual unsigned int composeSubRegIndicesImpl(
    unsigned int,
    unsigned int) const

Description

Overridden by TableGen in targets that have sub-registers.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:678

Parameters

unsigned int

unsigned int

¶static void dumpReg(
    llvm::Register Reg,
    unsigned int SubRegIndex = 0,
    const llvm::TargetRegisterInfo* TRI = nullptr)

Description

Debugging helper: dump register in human readable form to dbgs() stream.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:673

Parameters

llvm::Register Reg

unsigned int SubRegIndex = 0

const llvm::TargetRegisterInfo* TRI = nullptr

¶virtual void eliminateFrameIndex(
    MachineBasicBlock::iterator MI,
    int SPAdj,
    unsigned int FIOperandNum,
    llvm::RegScavenger* RS = nullptr) const

Description

This method must be overriden to eliminate abstract frame indices from instructions which may use them. The instruction referenced by the iterator contains an MO_FrameIndex operand which must be eliminated by this method. This method may modify or replace the specified instruction, as long as it keeps the iterator pointing at the finished product. SPAdj is the SP adjustment due to call frame setup instruction. FIOperandNum is the FI operand number.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:1017

Parameters

MachineBasicBlock::iterator MI

int SPAdj

unsigned int FIOperandNum

llvm::RegScavenger* RS = nullptr

¶const llvm::TargetRegisterClass*
getAllocatableClass(
    const llvm::TargetRegisterClass* RC) const

Description

Return the maximal subclass of the given register class that is allocatable or NULL.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:343

Parameters

const llvm::TargetRegisterClass* RC

¶llvm::BitVector getAllocatableSet(
    const llvm::MachineFunction& MF,
    const llvm::TargetRegisterClass* RC =
        nullptr) const

Description

Returns a bitset indexed by register number indicating if a register is allocatable or not. If a register class is specified, returns the subset for the class.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:348

Parameters

const llvm::MachineFunction& MF

const llvm::TargetRegisterClass* RC = nullptr

¶virtual unsigned int getCSRFirstUseCost() const

Description

Allow the target to override the cost of using a callee-saved register for the first time. Default value of 0 means we will use a callee-saved register if it is available.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:890

¶virtual const uint32_t* getCallPreservedMask(
    const llvm::MachineFunction& MF,
    CallingConv::ID) const

Description

Return a mask of call-preserved registers for the given calling convention on the current function. The mask should include all call-preserved aliases. This is used by the register allocator to determine which registers can be live across a call. The mask is an array containing (TRI::getNumRegs()+31)/32 entries. A set bit indicates that all bits of the corresponding register are preserved across the function call. The bit mask is expected to be sub-register complete, i.e. if A is preserved, so are all its sub-registers. Bits are numbered from the LSB, so the bit for physical register Reg can be found as (Mask[Reg / 32] >> Reg % 32) & 1. A NULL pointer means that no register mask will be used, and call instructions should use implicit-def operands to indicate call clobbered registers.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:480

Parameters

const llvm::MachineFunction& MF

CallingConv::ID

¶virtual const llvm::MCPhysReg* getCalleeSavedRegs(
    const llvm::MachineFunction* MF) const

Description

Return a null-terminated list of all of the callee-saved registers on this target. The register should be in the order of desired callee-save stack frame offset. The first register is closest to the incoming stack pointer if stack grows down, and vice versa. Notice: This function does not take into account disabled CSRs. In most cases you will want to use instead the function getCalleeSavedRegs that is implemented in MachineRegisterInfo.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:460

Parameters

const llvm::MachineFunction* MF

¶const llvm::TargetRegisterClass*
getCommonSubClass(
    const llvm::TargetRegisterClass* A,
    const llvm::TargetRegisterClass* B) const

Description

Find the largest common subclass of A and B. Return NULL if there is no common subclass.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:763

Parameters

const llvm::TargetRegisterClass* A

const llvm::TargetRegisterClass* B

¶const llvm::TargetRegisterClass*
getCommonSuperRegClass(
    const llvm::TargetRegisterClass* RCA,
    unsigned int SubA,
    const llvm::TargetRegisterClass* RCB,
    unsigned int SubB,
    unsigned int& PreA,
    unsigned int& PreB) const

Description

Find a common super-register class if it exists. Find a register class, SuperRC and two sub-register indices, PreA and PreB, such that: 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()). SuperRC will be chosen such that no super-class of SuperRC satisfies the requirements, and there is no register class with a smaller spill size that satisfies the requirements. SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead. Either of the PreA and PreB sub-register indices may be returned as 0. In that case, the returned register class will be a sub-class of the corresponding argument register class. The function returns NULL if no register class can be found.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:724

Parameters

const llvm::TargetRegisterClass* RCA

unsigned int SubA

const llvm::TargetRegisterClass* RCB

unsigned int SubB

unsigned int& PreA

unsigned int& PreB

¶virtual const llvm::TargetRegisterClass*
getConstrainedRegClassForOperand(
    const llvm::MachineOperand& MO,
    const llvm::MachineRegisterInfo& MRI) const

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:1105

Parameters

const llvm::MachineOperand& MO

const llvm::MachineRegisterInfo& MRI

¶llvm::LaneBitmask getCoveringLanes() const

Description

The lane masks returned by getSubRegIndexLaneMask() above can only be used to determine if sub-registers overlap - they can't be used to determine if a set of sub-registers completely cover another sub-register. The X86 general purpose registers have two lanes corresponding to the sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have lane masks '3', but the sub_16bit sub-register doesn't fully cover the sub_32bit sub-register. On the other hand, the ARM NEON lanes fully cover their registers: The dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes. This is related to the CoveredBySubRegs property on register definitions. This function returns a bit mask of lanes that completely cover their sub-registers. More precisely, given: Covering = getCoveringLanes(); MaskA = getSubRegIndexLaneMask(SubA); MaskB = getSubRegIndexLaneMask(SubB); If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by SubB.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:415

¶bool getCoveringSubRegIndexes(
    const llvm::MachineRegisterInfo& MRI,
    const llvm::TargetRegisterClass* RC,
    llvm::LaneBitmask LaneMask,
    SmallVectorImpl<unsigned int>& Indexes) const

Description

Try to find one or more subregister indexes to cover \p LaneMask. If this is possible, returns true and appends the best matching set of indexes to \p Indexes. If this is not possible, returns false.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:387

Parameters

const llvm::MachineRegisterInfo& MRI

const llvm::TargetRegisterClass* RC

llvm::LaneBitmask LaneMask

SmallVectorImpl<unsigned int>& Indexes

¶virtual const llvm::TargetRegisterClass*
getCrossCopyRegClass(
    const llvm::TargetRegisterClass* RC) const

Description

Returns a legal register class to copy a register in the specified class to or from. If it is possible to copy the register directly without using a cross register class copy, return the specified RC. Returns NULL if it is not possible to copy between two registers of the specified class.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:779

Parameters

const llvm::TargetRegisterClass* RC

¶virtual const uint32_t*
getCustomEHPadPreservedMask(
    const llvm::MachineFunction& MF) const

Description

Return a register mask for the registers preserved by the unwinder, or nullptr if no custom mask is needed.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:489

Parameters

const llvm::MachineFunction& MF

¶virtual int64_t getFrameIndexInstrOffset(
    const llvm::MachineInstr* MI,
    int Idx) const

Description

Get the offset from the referenced frame index in the instruction, if there is one.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:953

Parameters

const llvm::MachineInstr* MI

int Idx

¶virtual llvm::Register getFrameRegister(
    const llvm::MachineFunction& MF) const

Description

getFrameRegister - This method should return the register used as a base for values allocated in the current stack frame.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:1094

Parameters

const llvm::MachineFunction& MF

¶virtual ArrayRef<llvm::MCPhysReg>
getIntraCallClobberedRegs(
    const llvm::MachineFunction* MF) const

Description

Return a list of all of the registers which are clobbered "inside" a call to the given function. For example, these might be needed for PLT sequences of long-branch veneers.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:502

Parameters

const llvm::MachineFunction* MF

¶virtual const llvm::TargetRegisterClass*
getLargestLegalSuperClass(
    const llvm::TargetRegisterClass* RC,
    const llvm::MachineFunction&) const

Description

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size. The returned register class can be used to create virtual registers which means that all its registers can be copied and spilled.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:788

Parameters

const llvm::TargetRegisterClass* RC

const llvm::MachineFunction&

¶llvm::MCRegister getMatchingSuperReg(
    llvm::MCRegister Reg,
    unsigned int SubIdx,
    const llvm::TargetRegisterClass* RC) const

Description

Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:588

Parameters

llvm::MCRegister Reg

unsigned int SubIdx

const llvm::TargetRegisterClass* RC

¶virtual const llvm::TargetRegisterClass*
getMatchingSuperRegClass(
    const llvm::TargetRegisterClass* A,
    const llvm::TargetRegisterClass* B,
    unsigned int Idx) const

Description

Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B. TableGen will synthesize missing A sub-classes.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:599

Parameters

const llvm::TargetRegisterClass* A

const llvm::TargetRegisterClass* B

unsigned int Idx

¶const llvm::TargetRegisterClass*
getMinimalPhysRegClass(
    llvm::MCRegister Reg,
    llvm::MVT VT = MVT::Other) const

Description

Returns the Register Class of a physical register of the given type, picking the most sub register class of the right type that contains this physreg.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:330

Parameters

llvm::MCRegister Reg

llvm::MVT VT = MVT::Other

¶const llvm::TargetRegisterClass*
getMinimalPhysRegClassLLT(
    llvm::MCRegister Reg,
    llvm::LLT Ty = llvm::LLT()) const

Description

Returns the Register Class of a physical register of the given type, picking the most sub register class of the right type that contains this physreg. If there is no register class compatible with the given type, returns nullptr.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:337

Parameters

llvm::MCRegister Reg

llvm::LLT Ty = llvm::LLT()

¶virtual const uint32_t* getNoPreservedMask() const

Description

Return a register mask that clobbers everything.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:494

¶unsigned int getNumRegClasses() const

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:744

¶virtual unsigned int getNumRegPressureSets() const

Description

Get the number of dimensions of register pressure.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:826

¶virtual void getOffsetOpcodes(
    const llvm::StackOffset& Offset,
    SmallVectorImpl<uint64_t>& Ops) const

Description

Gets the DWARF expression opcodes for \p Offset.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:990

Parameters

const llvm::StackOffset& Offset

SmallVectorImpl<uint64_t>& Ops

¶virtual const llvm::TargetRegisterClass*
getPointerRegClass(
    const llvm::MachineFunction& MF,
    unsigned int Kind = 0) const

Description

Returns a TargetRegisterClass used for pointer values. If a target supports multiple different pointer register classes, kind specifies which one is indicated.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:770

Parameters

const llvm::MachineFunction& MF

unsigned int Kind = 0

¶virtual bool getRegAllocationHints(
    llvm::Register VirtReg,
    ArrayRef<llvm::MCPhysReg> Order,
    SmallVectorImpl<llvm::MCPhysReg>& Hints,
    const llvm::MachineFunction& MF,
    const llvm::VirtRegMap* VRM = nullptr,
    const llvm::LiveRegMatrix* Matrix =
        nullptr) const

Description

Get a list of 'hint' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg. These registers are effectively moved to the front of the allocation order. If true is returned, regalloc will try to only use hints to the greatest extent possible even if it means spilling. The Order argument is the allocation order for VirtReg's register class as returned from RegisterClassInfo::getOrder(). The hint registers must come from Order, and they must not be reserved. The default implementation of this function will only add target independent register allocation hints. Targets that override this function should typically call this default implementation as well and expect to see generic copy hints added.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:860

Parameters

llvm::Register VirtReg

ArrayRef<llvm::MCPhysReg> Order

SmallVectorImpl<llvm::MCPhysReg>& Hints

const llvm::MachineFunction& MF

const llvm::VirtRegMap* VRM = nullptr

const llvm::LiveRegMatrix* Matrix = nullptr

¶virtual llvm::StringRef getRegAsmName(
    llvm::MCRegister Reg) const

Description

Return the assembly name for \p Reg.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:1022

Parameters

llvm::MCRegister Reg

¶const llvm::TargetRegisterClass* getRegClass(
    unsigned int i) const

Description

Returns the register class associated with the enumeration value. See class MCOperandInfo.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:750

Parameters

unsigned int i

¶const llvm::TargetRegisterInfo::RegClassInfo&
getRegClassInfo(
    const llvm::TargetRegisterClass& RC) const

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:732

Parameters

const llvm::TargetRegisterClass& RC

¶const char* getRegClassName(
    const llvm::TargetRegisterClass* Class) const

Description

Returns the name of the register class.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:756

Parameters

const llvm::TargetRegisterClass* Class

¶virtual const int* getRegClassPressureSets(
    const llvm::TargetRegisterClass* RC) const

Description

Get the dimensions of register pressure impacted by this register class. Returns a -1 terminated array of pressure set IDs.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:838

Parameters

const llvm::TargetRegisterClass* RC

¶virtual const llvm::RegClassWeight&
getRegClassWeight(
    const llvm::TargetRegisterClass* RC) const

Description

Get the weight in units of pressure for this register class.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:816

Parameters

const llvm::TargetRegisterClass* RC

¶virtual ArrayRef<const char*> getRegMaskNames()
    const

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:512

¶virtual ArrayRef<const uint32_t*> getRegMasks()
    const

Description

Return all the call-preserved register masks defined for this target.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:511

¶virtual unsigned int getRegPressureLimit(
    const llvm::TargetRegisterClass* RC,
    llvm::MachineFunction& MF) const

Description

Return the register pressure "high water mark" for the specific register class. The scheduler is in high register pressure mode (for the specific register class) if it goes over the limit. Note: this is the old register pressure model that relies on a manually specified representative register class per value type.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:801

Parameters

const llvm::TargetRegisterClass* RC

llvm::MachineFunction& MF

¶virtual unsigned int getRegPressureSetLimit(
    const llvm::MachineFunction& MF,
    unsigned int Idx) const

Description

Get the register unit pressure limit for this dimension. This limit must be adjusted dynamically for reserved registers.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:833

Parameters

const llvm::MachineFunction& MF

unsigned int Idx

¶virtual const char* getRegPressureSetName(
    unsigned int Idx) const

Description

Get the name of this register unit pressure set.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:829

Parameters

unsigned int Idx

¶virtual unsigned int getRegPressureSetScore(
    const llvm::MachineFunction& MF,
    unsigned int PSetID) const

Description

Return a heuristic for the machine scheduler to compare the profitability of increasing one register pressure set versus another. The scheduler will prefer increasing the register pressure of the set which returns the largest value for this function.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:810

Parameters

const llvm::MachineFunction& MF

unsigned int PSetID

¶unsigned int getRegSizeInBits(
    const llvm::TargetRegisterClass& RC) const

Description

Return the size in bits of a register from class RC.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:277

Parameters

const llvm::TargetRegisterClass& RC

¶unsigned int getRegSizeInBits(
    llvm::Register Reg,
    const llvm::MachineRegisterInfo& MRI) const

Description

Returns size in bits of a phys/virtual/generic register.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:820

Parameters

llvm::Register Reg

const llvm::MachineRegisterInfo& MRI

¶virtual const int* getRegUnitPressureSets(
    unsigned int RegUnit) const

Description

Get the dimensions of register pressure impacted by this register unit. Returns a -1 terminated array of pressure set IDs.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:843

Parameters

unsigned int RegUnit

¶virtual unsigned int getRegUnitWeight(
    unsigned int RegUnit) const

Description

Get the weight in units of pressure for this register unit.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:823

Parameters

unsigned int RegUnit

¶virtual unsigned int getRegisterCostTableIndex(
    const llvm::MachineFunction& MF) const

Description

Return the register cost table index. This implementation is sufficient for most architectures and can be overriden by targets in case there are multiple cost values associated with each register.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:696

Parameters

const llvm::MachineFunction& MF

¶ArrayRef<uint8_t> getRegisterCosts(
    const llvm::MachineFunction& MF) const

Description

Get a list of cost values for all registers that correspond to the index returned by RegisterCostTableIndex.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:353

Parameters

const llvm::MachineFunction& MF

¶virtual llvm::BitVector getReservedRegs(
    const llvm::MachineFunction& MF) const

Description

Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times, e.g. stack pointer, return address. A reserved register: - is not allocatable - is considered always live - is ignored by liveness tracking It is often necessary to reserve the super registers of a reserved register as well, to avoid them getting allocated indirectly. You may use markSuperRegs() and checkAllSuperRegsMarked() in this case.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:524

Parameters

const llvm::MachineFunction& MF

¶llvm::Align getSpillAlign(
    const llvm::TargetRegisterClass& RC) const

Description

Return the minimum required alignment in bytes for a spill slot for a register of this class.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:289

Parameters

const llvm::TargetRegisterClass& RC

¶unsigned int getSpillSize(
    const llvm::TargetRegisterClass& RC) const

Description

Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class RC.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:283

Parameters

const llvm::TargetRegisterClass& RC

¶virtual const llvm::TargetRegisterClass*
getSubClassWithSubReg(
    const llvm::TargetRegisterClass* RC,
    unsigned int Idx) const

Description

Returns the largest legal sub-class of RC that supports the sub-register index Idx. If no such sub-class exists, return NULL. If all registers in RC already have an Idx sub-register, return RC. TableGen generates a version of this function that is good enough in most cases. Targets can override if they have constraints that TableGen doesn't understand. For example, the x86 sub_8bit sub-register index is supported by the full GR32 register class in 64-bit mode, but only by the GR32_ABCD regiister class in 32-bit mode. TableGen will synthesize missing RC sub-classes.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:624

Parameters

const llvm::TargetRegisterClass* RC

unsigned int Idx

¶inline llvm::MCRegister getSubReg(
    llvm::MCRegister Reg,
    unsigned int Idx) const

Description

Returns the physical register number of sub-register "Index" for physical register RegNo. Return zero if the sub-register does not exist.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:1113

Parameters

llvm::MCRegister Reg

unsigned int Idx

¶llvm::LaneBitmask getSubRegIndexLaneMask(
    unsigned int SubIdx) const

Description

Return a bitmask representing the parts of a register that are covered by SubIdx SubIdx == 0 is allowed, it has the lane mask ~0u.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:378

Parameters

unsigned int SubIdx

¶const char* getSubRegIndexName(
    unsigned int SubIdx) const

Description

Return the human-readable symbolic target-specific name for the specified SubRegIndex.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:368

Parameters

unsigned int SubIdx

¶bool hasRegUnit(llvm::MCRegister Reg,
                llvm::Register RegUnit) const

Description

Returns true if Reg contains RegUnit.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:428

Parameters

llvm::MCRegister Reg

llvm::Register RegUnit

¶virtual bool hasReservedSpillSlot(
    const llvm::MachineFunction& MF,
    llvm::Register Reg,
    int& FrameIdx) const

Description

Return true if target has reserved a spill slot in the stack frame of the given function for the specified register. e.g. On x86, if the frame register is required, the first fixed stack object is reserved as its spill slot. This tells PEI not to create a new stack frame object for the given register. It should be called only after determineCalleeSaves().

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:929

Parameters

const llvm::MachineFunction& MF

llvm::Register Reg

int& FrameIdx

¶bool hasStackRealignment(
    const llvm::MachineFunction& MF) const

Description

True if stack realignment is required and still possible.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:947

Parameters

const llvm::MachineFunction& MF

¶virtual bool isArgumentRegister(
    const llvm::MachineFunction& MF,
    llvm::MCRegister PhysReg) const

Description

Returns true if PhysReg can be used as an argument to a function.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:564

Parameters

const llvm::MachineFunction& MF

llvm::MCRegister PhysReg

¶virtual bool isAsmClobberable(
    const llvm::MachineFunction& MF,
    llvm::MCRegister PhysReg) const

Description

Returns false if we can't guarantee that Physreg, specified as an IR asm clobber constraint, will be preserved across the statement.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:528

Parameters

const llvm::MachineFunction& MF

llvm::MCRegister PhysReg

¶virtual bool isCalleeSavedPhysReg(
    llvm::MCRegister PhysReg,
    const llvm::MachineFunction& MF) const

Description

This is a wrapper around getCallPreservedMask(). Return true if the register is preserved after the call.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:560

Parameters

llvm::MCRegister PhysReg

const llvm::MachineFunction& MF

¶virtual bool isCallerPreservedPhysReg(
    llvm::MCRegister PhysReg,
    const llvm::MachineFunction& MF) const

Description

Physical registers that may be modified within a function but are guaranteed to be restored before any uses. This is useful for targets that have call sequences where a GOT register may be updated by the caller prior to a call and is guaranteed to be restored (also by the caller) after the call.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:553

Parameters

llvm::MCRegister PhysReg

const llvm::MachineFunction& MF

¶virtual bool isConstantPhysReg(
    llvm::MCRegister PhysReg) const

Description

Returns true if PhysReg is unallocatable and constant throughout the function. Used by MachineRegisterInfo::isConstantPhysReg().

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:541

Parameters

llvm::MCRegister PhysReg

¶virtual bool isDivergentRegClass(
    const llvm::TargetRegisterClass* RC) const

Description

Returns true if the register class is considered divergent.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:544

Parameters

const llvm::TargetRegisterClass* RC

¶virtual bool isFixedRegister(
    const llvm::MachineFunction& MF,
    llvm::MCRegister PhysReg) const

Description

Returns true if PhysReg is a fixed register.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:570

Parameters

const llvm::MachineFunction& MF

llvm::MCRegister PhysReg

¶virtual bool isFrameOffsetLegal(
    const llvm::MachineInstr* MI,
    llvm::Register BaseReg,
    int64_t Offset) const

Description

Determine whether a given base register plus offset immediate is encodable to resolve a frame index.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:984

Parameters

const llvm::MachineInstr* MI

llvm::Register BaseReg

int64_t Offset

¶virtual bool isGeneralPurposeRegister(
    const llvm::MachineFunction& MF,
    llvm::MCRegister PhysReg) const

Description

Returns true if PhysReg is a general purpose register.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:576

Parameters

const llvm::MachineFunction& MF

llvm::MCRegister PhysReg

¶bool isInAllocatableClass(
    llvm::MCRegister RegNo) const

Description

Return true if the register is in the allocation of any register class.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:362

Parameters

llvm::MCRegister RegNo

¶virtual bool isInlineAsmReadOnlyReg(
    const llvm::MachineFunction& MF,
    unsigned int PhysReg) const

Description

Returns true if PhysReg cannot be written to in inline asm statements.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:534

Parameters

const llvm::MachineFunction& MF

unsigned int PhysReg

¶virtual bool isNonallocatableRegisterCalleeSave(
    llvm::MCRegister Reg) const

Description

Some targets have non-allocatable registers that aren't technically part of the explicit callee saved register list, but should be handled as such in certain cases.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:1120

Parameters

llvm::MCRegister Reg

¶bool isTypeLegalForClass(
    const llvm::TargetRegisterClass& RC,
    llvm::LLT T) const

Description

Return true if the given TargetRegisterClass is compatible with LLT T.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:302

Parameters

const llvm::TargetRegisterClass& RC

llvm::LLT T

¶bool isTypeLegalForClass(
    const llvm::TargetRegisterClass& RC,
    llvm::MVT T) const

Description

Return true if the given TargetRegisterClass has the ValueType T.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:294

Parameters

const llvm::TargetRegisterClass& RC

llvm::MVT T

¶llvm::TargetRegisterInfo::vt_iterator
legalclasstypes_begin(
    const llvm::TargetRegisterClass& RC) const

Description

Loop over all of the value types that can be represented by values in the given register class.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:316

Parameters

const llvm::TargetRegisterClass& RC

¶llvm::TargetRegisterInfo::vt_iterator
legalclasstypes_end(
    const llvm::TargetRegisterClass& RC) const

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:320

Parameters

const llvm::TargetRegisterClass& RC

¶virtual llvm::Register lookThruCopyLike(
    llvm::Register SrcReg,
    const llvm::MachineRegisterInfo* MRI) const

Description

Returns the original SrcReg unless it is the target of a copy-like operation, in which case we chain backwards through all such operations to the ultimate source register. If a physical register is encountered, we stop the search.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:439

Parameters

llvm::Register SrcReg

const llvm::MachineRegisterInfo* MRI

¶virtual llvm::Register lookThruSingleUseCopyChain(
    llvm::Register SrcReg,
    const llvm::MachineRegisterInfo* MRI) const

Description

Find the original SrcReg unless it is the target of a copy-like operation, in which case we chain backwards through all such operations to the ultimate source register. If a physical register is encountered, we stop the search. Return the original SrcReg if all the definitions in the chain only have one user and not a physical register.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:449

Parameters

llvm::Register SrcReg

const llvm::MachineRegisterInfo* MRI

¶void markSuperRegs(llvm::BitVector& RegisterSet,
                   llvm::MCRegister Reg) const

Description

Mark a register and all its aliases as reserved in the given set.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:1097

Parameters

llvm::BitVector& RegisterSet

llvm::MCRegister Reg

¶virtual llvm::Register
materializeFrameBaseRegister(
    llvm::MachineBasicBlock* MBB,
    int FrameIdx,
    int64_t Offset) const

Description

Insert defining instruction(s) for a pointer to FrameIdx before insertion point I. Return materialized frame pointer.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:968

Parameters

llvm::MachineBasicBlock* MBB

int FrameIdx

int64_t Offset

¶virtual bool needsFrameBaseReg(
    llvm::MachineInstr* MI,
    int64_t Offset) const

Description

Returns true if the instruction's frame index reference would be better served by a base register other than FP or SP. Used by LocalStackFrameAllocation to determine which frame index references it should create new base registers for.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:962

Parameters

llvm::MachineInstr* MI

int64_t Offset

¶llvm::DIExpression* prependOffsetExpression(
    const llvm::DIExpression* Expr,
    unsigned int PrependFlags,
    const llvm::StackOffset& Offset) const

Description

Prepends a DWARF expression for \p Offset to DIExpression \p Expr.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:995

Parameters

const llvm::DIExpression* Expr

unsigned int PrependFlags

const llvm::StackOffset& Offset

¶virtual bool regClassPriorityTrumpsGlobalness(
    const llvm::MachineFunction& MF) const

Description

When prioritizing live ranges in register allocation, if this hook returns true then the AllocationPriority of the register class will be treated as more important than whether the range is local to a basic block or global.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:1085

Parameters

const llvm::MachineFunction& MF

¶llvm::TargetRegisterInfo::regclass_iterator
regclass_begin() const

Description

Register class iterators

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:738

¶llvm::TargetRegisterInfo::regclass_iterator
regclass_end() const

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:739

¶iterator_range<
    llvm::TargetRegisterInfo::regclass_iterator>
regclasses() const

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:740

¶bool regmaskSubsetEqual(
    const uint32_t* mask0,
    const uint32_t* mask1) const

Description

Return true if all bits that are set in mask \p mask0 are also set in\p mask1.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:508

Parameters

const uint32_t* mask0

const uint32_t* mask1

¶bool regsOverlap(llvm::Register RegA,
                 llvm::Register RegB) const

Description

Returns true if the two registers are equal or alias each other. The registers may be virtual registers.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:419

Parameters

llvm::Register RegA

llvm::Register RegB

¶virtual bool
requiresFrameIndexReplacementScavenging(
    const llvm::MachineFunction& MF) const

Description

Returns true if the target requires using the RegScavenger directly for frame elimination despite using requiresFrameIndexScavenging.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:912

Parameters

const llvm::MachineFunction& MF

¶virtual bool requiresFrameIndexScavenging(
    const llvm::MachineFunction& MF) const

Description

Returns true if the target requires post PEI scavenging of registers for materializing frame index constants.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:906

Parameters

const llvm::MachineFunction& MF

¶virtual bool requiresRegisterScavenging(
    const llvm::MachineFunction& MF) const

Description

Returns true if the target requires (and can make use of) the register scavenger.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:894

Parameters

const llvm::MachineFunction& MF

¶virtual bool requiresVirtualBaseRegisters(
    const llvm::MachineFunction& MF) const

Description

Returns true if the target wants the LocalStackAllocation pass to be run and virtual base registers used for more efficient stack access.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:919

Parameters

const llvm::MachineFunction& MF

¶virtual void resolveFrameIndex(
    llvm::MachineInstr& MI,
    llvm::Register BaseReg,
    int64_t Offset) const

Description

Resolve a frame index operand of an instruction to reference the indicated base register plus offset instead.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:977

Parameters

llvm::MachineInstr& MI

llvm::Register BaseReg

int64_t Offset

¶llvm::LaneBitmask
reverseComposeSubRegIndexLaneMask(
    unsigned int IdxA,
    llvm::LaneBitmask LaneMask) const

Description

Transform a lanemask given for a virtual register to the corresponding lanemask before using subregister with index \p IdxA. This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a valie lane mask (no invalid bits set) the following holds: X0 = composeSubRegIndexLaneMask(Idx, Mask) X1 = reverseComposeSubRegIndexLaneMask(Idx, X0) => X1 == Mask

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:665

Parameters

unsigned int IdxA

llvm::LaneBitmask LaneMask

¶virtual llvm::LaneBitmask
reverseComposeSubRegIndexLaneMaskImpl(
    unsigned int,
    llvm::LaneBitmask) const

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:688

Parameters

unsigned int

llvm::LaneBitmask

¶virtual bool reverseLocalAssignment() const

Description

Allow the target to reverse allocation order of local live ranges. This will generally allocate shorter local live ranges first. For targets with many registers, this could reduce regalloc compile time by a large factor. It is disabled by default for three reasons: (1) Top-down allocation is simpler and easier to debug for targets that don't benefit from reversing the order. (2) Bottom-up allocation could result in poor evicition decisions on some targets affecting the performance of compiled code. (3) Bottom-up allocation is no longer guaranteed to optimally color.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:885

¶virtual bool saveScavengerRegister(
    llvm::MachineBasicBlock& MBB,
    MachineBasicBlock::iterator I,
    MachineBasicBlock::iterator& UseMI,
    const llvm::TargetRegisterClass* RC,
    llvm::Register Reg) const

Description

Spill the register so it can be used by the register scavenger. Return true if the register was spilled, false otherwise. If this function does not spill the register, the scavenger will instead spill it to the emergency spill slot.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:1002

Parameters

llvm::MachineBasicBlock& MBB

MachineBasicBlock::iterator I

MachineBasicBlock::iterator& UseMI

const llvm::TargetRegisterClass* RC

llvm::Register Reg

¶virtual bool shouldCoalesce(
    llvm::MachineInstr* MI,
    const llvm::TargetRegisterClass* SrcRC,
    unsigned int SubReg,
    const llvm::TargetRegisterClass* DstRC,
    unsigned int DstSubReg,
    const llvm::TargetRegisterClass* NewRC,
    llvm::LiveIntervals& LIS) const

Description

SrcRC and DstRC will be morphed into NewRC if this returns true.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:1036

Parameters

llvm::MachineInstr* MI

const llvm::TargetRegisterClass* SrcRC

unsigned int SubReg

const llvm::TargetRegisterClass* DstRC

unsigned int DstSubReg

const llvm::TargetRegisterClass* NewRC

llvm::LiveIntervals& LIS

¶virtual bool shouldRealignStack(
    const llvm::MachineFunction& MF) const

Description

True if storage within the function requires the stack pointer to be aligned more than the normal calling convention calls for.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:944

Parameters

const llvm::MachineFunction& MF

¶virtual bool shouldRegionSplitForVirtReg(
    const llvm::MachineFunction& MF,
    const llvm::LiveInterval& VirtReg) const

Description

Region split has a high compile time cost especially for large live range. This method is used to decide whether or not \p VirtReg should go through this expensive splitting heuristic.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:1048

Parameters

const llvm::MachineFunction& MF

const llvm::LiveInterval& VirtReg

¶virtual bool shouldRewriteCopySrc(
    const llvm::TargetRegisterClass* DefRC,
    unsigned int DefSubReg,
    const llvm::TargetRegisterClass* SrcRC,
    unsigned int SrcSubReg) const

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:606

Parameters

const llvm::TargetRegisterClass* DefRC

unsigned int DefSubReg

const llvm::TargetRegisterClass* SrcRC

unsigned int SrcSubReg

¶virtual bool shouldUseDeferredSpillingForVirtReg(
    const llvm::MachineFunction& MF,
    const llvm::LiveInterval& VirtReg) const

Description

Deferred spilling delays the spill insertion of a virtual register after every other allocation. By deferring the spilling, it is sometimes possible to eliminate that spilling altogether because something else could have been eliminated, thus leaving some space for the virtual register. However, this comes with a compile time impact because it adds one more stage to the greedy register allocator. This method is used to decide whether \p VirtReg should use the deferred spilling stage instead of being spilled right away.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:1076

Parameters

const llvm::MachineFunction& MF

const llvm::LiveInterval& VirtReg

¶virtual bool
shouldUseLastChanceRecoloringForVirtReg(
    const llvm::MachineFunction& MF,
    const llvm::LiveInterval& VirtReg) const

Description

Last chance recoloring has a high compile time cost especially for targets with a lot of registers. This method is used to decide whether or not \p VirtReg should go through this expensive heuristic. When this target hook is hit, by returning false, there is a high chance that the register allocation will fail altogether (usually with "ran out of registers"). That said, this error usually points to another problem in the optimization pipeline.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:1061

Parameters

const llvm::MachineFunction& MF

const llvm::LiveInterval& VirtReg

¶virtual bool trackLivenessAfterRegAlloc(
    const llvm::MachineFunction& MF) const

Description

Returns true if the live-ins should be tracked after register allocation.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:935

Parameters

const llvm::MachineFunction& MF

¶virtual void updateRegAllocHint(
    llvm::Register Reg,
    llvm::Register NewReg,
    llvm::MachineFunction& MF) const

Description

A callback to allow target a chance to update register allocation hints when a register is "changed" (e.g. coalesced) to another register. e.g. On ARM, some virtual registers should target register pairs, if one of pair is coalesced to another register, the allocation hint of the other half of the pair should be changed to point to the new register.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:871

Parameters

llvm::Register Reg

llvm::Register NewReg

llvm::MachineFunction& MF

¶virtual bool useFPForScavengingIndex(
    const llvm::MachineFunction& MF) const

Description

Returns true if the target wants to use frame pointer based accesses to spill to the scavenger emergency spill slot.

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:900

Parameters

const llvm::MachineFunction& MF

¶virtual ~TargetRegisterInfo()

Declared at: llvm/include/llvm/CodeGen/TargetRegisterInfo.h:262