class ConvergingVLIWScheduler

Declaration

class ConvergingVLIWScheduler : public MachineSchedStrategy { /* full declaration omitted */ };

Description

MachineSchedStrategy - Interface to the scheduling algorithm used by ScheduleDAGMI. Initialization sequence: initPolicy -> shouldTrackPressure -> initialize(DAG) -> registerRoots

Declared at: llvm/include/llvm/CodeGen/VLIWMachineScheduler.h:88

Inherits from: MachineSchedStrategy

Member Variables

protected llvm::VLIWMachineScheduler* DAG = nullptr
protected const llvm::TargetSchedModel* SchedModel = nullptr
protected llvm::ConvergingVLIWScheduler::VLIWSchedBoundary Top
protected llvm::ConvergingVLIWScheduler::VLIWSchedBoundary Bot
protected SmallVector<bool> HighPressureSets
List of pressure sets that have a high pressure level in the region.
protected static const unsigned int PriorityOne = 200
protected static const unsigned int PriorityTwo = 50
protected static const unsigned int PriorityThree = 75
protected static const unsigned int ScaleTwo = 10

Method Overview

  • public ConvergingVLIWScheduler()
  • protected virtual int SchedulingCost(llvm::ReadyQueue & Q, llvm::SUnit * SU, llvm::ConvergingVLIWScheduler::SchedCandidate & Candidate, llvm::RegPressureDelta & Delta, bool verbose)
  • protected virtual llvm::VLIWResourceModel * createVLIWResourceModel(const llvm::TargetSubtargetInfo & STI, const llvm::TargetSchedModel * SchedModel) const
  • public void initialize(llvm::ScheduleDAGMI * dag)
  • public llvm::SUnit * pickNode(bool & IsTopNode)
  • protected llvm::SUnit * pickNodeBidrectional(bool & IsTopNode)
  • protected llvm::ConvergingVLIWScheduler::CandResult pickNodeFromQueue(llvm::ConvergingVLIWScheduler::VLIWSchedBoundary & Zone, const llvm::RegPressureTracker & RPTracker, llvm::ConvergingVLIWScheduler::SchedCandidate & Candidate)
  • protected int pressureChange(const llvm::SUnit * SU, bool isBotUp)
  • protected void readyQueueVerboseDump(const llvm::RegPressureTracker & RPTracker, llvm::ConvergingVLIWScheduler::SchedCandidate & Candidate, llvm::ReadyQueue & Q)
  • public void releaseBottomNode(llvm::SUnit * SU)
  • public void releaseTopNode(llvm::SUnit * SU)
  • public unsigned int reportPackets()
  • public void schedNode(llvm::SUnit * SU, bool IsTopNode)
  • protected void traceCandidate(const char * Label, const llvm::ReadyQueue & Q, llvm::SUnit * SU, int Cost, llvm::PressureChange P = llvm::PressureChange())
  • public virtual ~ConvergingVLIWScheduler()

Inherited from MachineSchedStrategy:

Methods

ConvergingVLIWScheduler()

Declared at: llvm/include/llvm/CodeGen/VLIWMachineScheduler.h:221

virtual int SchedulingCost(
    llvm::ReadyQueue& Q,
    llvm::SUnit* SU,
    llvm::ConvergingVLIWScheduler::SchedCandidate&
        Candidate,
    llvm::RegPressureDelta& Delta,
    bool verbose)

Description

Single point to compute overall scheduling cost. TODO: More heuristics will be used soon.

Declared at: llvm/include/llvm/CodeGen/VLIWMachineScheduler.h:248

Parameters

llvm::ReadyQueue& Q
llvm::SUnit* SU
llvm::ConvergingVLIWScheduler::SchedCandidate& Candidate
llvm::RegPressureDelta& Delta
bool verbose

virtual llvm::VLIWResourceModel*
createVLIWResourceModel(
    const llvm::TargetSubtargetInfo& STI,
    const llvm::TargetSchedModel* SchedModel)
    const

Declared at: llvm/include/llvm/CodeGen/VLIWMachineScheduler.h:241

Parameters

const llvm::TargetSubtargetInfo& STI
const llvm::TargetSchedModel* SchedModel

void initialize(llvm::ScheduleDAGMI* dag)

Description

Initialize the strategy after building the DAG for a new region.

Declared at: llvm/include/llvm/CodeGen/VLIWMachineScheduler.h:224

Parameters

llvm::ScheduleDAGMI* dag

llvm::SUnit* pickNode(bool& IsTopNode)

Description

Pick the best node to balance the schedule. Implements MachineSchedStrategy.

Declared at: llvm/include/llvm/CodeGen/VLIWMachineScheduler.h:226

Parameters

bool& IsTopNode

llvm::SUnit* pickNodeBidrectional(bool& IsTopNode)

Description

Pick the best candidate node from either the top or bottom queue.

Declared at: llvm/include/llvm/CodeGen/VLIWMachineScheduler.h:244

Parameters

bool& IsTopNode

llvm::ConvergingVLIWScheduler::CandResult
pickNodeFromQueue(
    llvm::ConvergingVLIWScheduler::
        VLIWSchedBoundary& Zone,
    const llvm::RegPressureTracker& RPTracker,
    llvm::ConvergingVLIWScheduler::SchedCandidate&
        Candidate)

Description

Pick the best candidate from the top queue. TODO: getMaxPressureDelta results can be mostly cached for each SUnit during DAG building. To adjust for the current scheduling location we need to maintain the number of vreg uses remaining to be top-scheduled.

Declared at: llvm/include/llvm/CodeGen/VLIWMachineScheduler.h:252

Parameters

llvm::ConvergingVLIWScheduler::VLIWSchedBoundary& Zone
const llvm::RegPressureTracker& RPTracker
llvm::ConvergingVLIWScheduler::SchedCandidate& Candidate

int pressureChange(const llvm::SUnit* SU,
                   bool isBotUp)

Description

Check if the instruction changes the register pressure of a register in the high pressure set. The function returns a negative value if the pressure decreases and a positive value is the pressure increases. If the instruction doesn't use a high pressure register or doesn't change the register pressure, then return 0.

Declared at: llvm/include/llvm/CodeGen/VLIWMachineScheduler.h:246

Parameters

const llvm::SUnit* SU
bool isBotUp

void readyQueueVerboseDump(
    const llvm::RegPressureTracker& RPTracker,
    llvm::ConvergingVLIWScheduler::SchedCandidate&
        Candidate,
    llvm::ReadyQueue& Q)

Declared at: llvm/include/llvm/CodeGen/VLIWMachineScheduler.h:259

Parameters

const llvm::RegPressureTracker& RPTracker
llvm::ConvergingVLIWScheduler::SchedCandidate& Candidate
llvm::ReadyQueue& Q

void releaseBottomNode(llvm::SUnit* SU)

Description

When all successor dependencies have been resolved, free this node for bottom-up scheduling.

Declared at: llvm/include/llvm/CodeGen/VLIWMachineScheduler.h:232

Parameters

llvm::SUnit* SU

void releaseTopNode(llvm::SUnit* SU)

Description

When all predecessor dependencies have been resolved, free this node for top-down scheduling.

Declared at: llvm/include/llvm/CodeGen/VLIWMachineScheduler.h:230

Parameters

llvm::SUnit* SU

unsigned int reportPackets()

Declared at: llvm/include/llvm/CodeGen/VLIWMachineScheduler.h:234

void schedNode(llvm::SUnit* SU, bool IsTopNode)

Description

Update the scheduler's state after scheduling a node. This is the same node that was just returned by pickNode(). However, VLIWMachineScheduler needs to update it's state based on the current cycle before MachineSchedStrategy does.

Declared at: llvm/include/llvm/CodeGen/VLIWMachineScheduler.h:228

Parameters

llvm::SUnit* SU
bool IsTopNode

void traceCandidate(const char* Label,
                    const llvm::ReadyQueue& Q,
                    llvm::SUnit* SU,
                    int Cost,
                    llvm::PressureChange P =
                        llvm::PressureChange())

Declared at: llvm/include/llvm/CodeGen/VLIWMachineScheduler.h:256

Parameters

const char* Label
const llvm::ReadyQueue& Q
llvm::SUnit* SU
int Cost
llvm::PressureChange P = llvm::PressureChange()

virtual ~ConvergingVLIWScheduler()

Declared at: llvm/include/llvm/CodeGen/VLIWMachineScheduler.h:222