class TargetSchedModel

Declaration

class TargetSchedModel { /* full declaration omitted */ };

Description

Provide an instruction scheduling machine model to CodeGen passes.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:30

Member Variables

private llvm::MCSchedModel SchedModel
private llvm::InstrItineraryData InstrItins
private const llvm::TargetSubtargetInfo* STI = nullptr
private const llvm::TargetInstrInfo* TII = nullptr
private SmallVector<unsigned int, 16> ResourceFactors
private unsigned int MicroOpFactor = 0
private unsigned int ResourceLCM = 0

Method Overview

Methods

TargetSchedModel()

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:49

unsigned int computeInstrLatency(
    const llvm::MCSchedClassDesc& SCDesc) const

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:46

Parameters

const llvm::MCSchedClassDesc& SCDesc

unsigned int computeInstrLatency(
    unsigned int Opcode) const

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:191

Parameters

unsigned int Opcode

unsigned int computeInstrLatency(
    const llvm::MCInst& Inst) const

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:190

Parameters

const llvm::MCInst& Inst

unsigned int computeInstrLatency(
    const llvm::MachineInstr* MI,
    bool UseDefaultDefLatency = true) const

Description

Compute the instruction latency based on the available machine model. Compute and return the expected latency of this instruction independent of a particular use. computeOperandLatency is the preferred API, but this is occasionally useful to help estimate instruction cost. If UseDefaultDefLatency is false and no new machine sched model is present this method falls back to TII->getInstrLatency with an empty instruction itinerary (this is so we preserve the previous behavior of the if converter after moving it to TargetSchedModel).

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:188

Parameters

const llvm::MachineInstr* MI
bool UseDefaultDefLatency = true

unsigned int computeOperandLatency(
    const llvm::MachineInstr* DefMI,
    unsigned int DefOperIdx,
    const llvm::MachineInstr* UseMI,
    unsigned int UseOperIdx) const

Description

Compute operand latency based on the available machine model. Compute and return the latency of the given data dependent def and use when the operand indices are already known. UseMI may be NULL for an unknown user.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:173

Parameters

const llvm::MachineInstr* DefMI
unsigned int DefOperIdx
const llvm::MachineInstr* UseMI
unsigned int UseOperIdx

unsigned int computeOutputLatency(
    const llvm::MachineInstr* DefMI,
    unsigned int DefOperIdx,
    const llvm::MachineInstr* DepMI) const

Description

Output dependency latency of a pair of defs of the same register. This is typically one cycle.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:197

Parameters

const llvm::MachineInstr* DefMI
unsigned int DefOperIdx
const llvm::MachineInstr* DepMI

double computeReciprocalThroughput(
    unsigned int Opcode) const

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:203

Parameters

unsigned int Opcode

double computeReciprocalThroughput(
    const llvm::MCInst& MI) const

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:202

Parameters

const llvm::MCInst& MI

double computeReciprocalThroughput(
    const llvm::MachineInstr* MI) const

Description

Compute the reciprocal throughput of the given instruction.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:201

Parameters

const llvm::MachineInstr* MI

const llvm::TargetInstrInfo* getInstrInfo() const

Description

TargetInstrInfo getter.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:65

const llvm::InstrItineraryData*
getInstrItineraries() const

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:82

unsigned int getIssueWidth() const

Description

Maximum number of micro-ops that may be scheduled per cycle.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:98

unsigned int getLatencyFactor() const

Description

Multiply cycle count by this factor to normalize it relative to other resources. This is the number of resource units per cycle.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:155

const llvm::MCSchedModel* getMCSchedModel() const

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:74

unsigned int getMicroOpBufferSize() const

Description

Number of micro-ops that may be buffered for OOO execution.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:160

unsigned int getMicroOpFactor() const

Description

Multiply number of micro-ops by this factor to normalize it relative to other resources.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:149

unsigned int getNumMicroOps(
    const llvm::MachineInstr* MI,
    const llvm::MCSchedClassDesc* SC =
        nullptr) const

Description

Return the number of issue slots required for this MI.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:108

Parameters

const llvm::MachineInstr* MI
const llvm::MCSchedClassDesc* SC = nullptr

unsigned int getNumProcResourceKinds() const

Description

Get the number of kinds of resources for this target.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:112

const llvm::MCProcResourceDesc* getProcResource(
    unsigned int PIdx) const

Description

Get a processor resource by ID for convenience.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:117

Parameters

unsigned int PIdx

unsigned int getProcessorID() const

Description

Identify the processor corresponding to the current subtarget.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:95

int getResourceBufferSize(unsigned int PIdx) const

Description

Number of resource units that may be buffered for OOO execution.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:164

Parameters

unsigned int PIdx

Returns

The buffer size in resource units or -1 for unlimited.

unsigned int getResourceFactor(
    unsigned int ResIdx) const

Description

Multiply the number of units consumed for a resource by this factor to normalize it relative to other resources.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:143

Parameters

unsigned int ResIdx

const char* getResourceName(
    unsigned int PIdx) const

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:122

Parameters

unsigned int PIdx

const llvm::TargetSubtargetInfo*
getSubtargetInfo() const

Description

TargetSubtargetInfo getter.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:62

llvm::TargetSchedModel::ProcResIter
getWriteProcResBegin(
    const llvm::MCSchedClassDesc* SC) const

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:133

Parameters

const llvm::MCSchedClassDesc* SC

llvm::TargetSchedModel::ProcResIter
getWriteProcResEnd(
    const llvm::MCSchedClassDesc* SC) const

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:137

Parameters

const llvm::MCSchedClassDesc* SC

bool hasInstrItineraries() const

Description

Return true if this machine model includes cycle-to-cycle itinerary data. This models scheduling at each stage in the processor pipeline.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:80

bool hasInstrSchedModel() const

Description

Return true if this machine model includes an instruction-level scheduling model. This is more detailed than the course grain IssueWidth and default latency properties, but separate from the per-cycle itinerary data.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:72

bool hasInstrSchedModelOrItineraries() const

Description

Return true if this machine model includes an instruction-level scheduling model or cycle-to-cycle itinerary data.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:90

void init(const llvm::TargetSubtargetInfo* TSInfo)

Description

Initialize the machine model for instruction scheduling. The machine model API keeps a copy of the top-level MCSchedModel table indices and may query TargetSubtargetInfo and TargetInstrInfo to resolve dynamic properties.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:56

Parameters

const llvm::TargetSubtargetInfo* TSInfo

bool mustBeginGroup(const llvm::MachineInstr* MI,
                    const llvm::MCSchedClassDesc*
                        SC = nullptr) const

Description

Return true if new group must begin.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:101

Parameters

const llvm::MachineInstr* MI
const llvm::MCSchedClassDesc* SC = nullptr

bool mustEndGroup(const llvm::MachineInstr* MI,
                  const llvm::MCSchedClassDesc*
                      SC = nullptr) const

Description

Return true if current group must end.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:104

Parameters

const llvm::MachineInstr* MI
const llvm::MCSchedClassDesc* SC = nullptr

const llvm::MCSchedClassDesc* resolveSchedClass(
    const llvm::MachineInstr* MI) const

Description

Return the MCSchedClassDesc for this instruction.

Declared at: llvm/include/llvm/CodeGen/TargetSchedule.h:59

Parameters

const llvm::MachineInstr* MI