struct X86GenSubtargetInfo

Declaration

struct X86GenSubtargetInfo : public TargetSubtargetInfo { /* full declaration omitted */ };

Description

TargetSubtargetInfo - Generic base class for all target subtargets. All Target-specific options that control code generation and printing should be exposed through a TargetSubtargetInfo-derived class.

Declared at: build/lib/Target/X86/X86GenSubtargetInfo.inc:31397

Inherits from: TargetSubtargetInfo

Member Variables

Method Overview

• public X86GenSubtargetInfo(const llvm::Triple & TT, llvm::StringRef CPU, llvm::StringRef TuneCPU, llvm::StringRef FS)
• public llvm::DFAPacketizer * createDFAPacketizer(const llvm::InstrItineraryData * IID) const
• public bool isDependencyBreaking(const llvm::MachineInstr * MI, llvm::APInt & Mask) const
• public bool isOptimizableRegisterMove(const llvm::MachineInstr * MI) const
• public bool isZeroIdiom(const llvm::MachineInstr * MI, llvm::APInt & Mask) const
• public unsigned int resolveSchedClass(unsigned int SchedClass, const llvm::MachineInstr * DefMI, const llvm::TargetSchedModel * SchedModel) const
• public unsigned int resolveVariantSchedClass(unsigned int SchedClass, const llvm::MCInst * MI, const llvm::MCInstrInfo * MCII, unsigned int CPUID) const

Inherited from TargetSubtargetInfo:

• public addrSinkUsingGEPs
• public adjustSchedDependency
• public enableAtomicExpand
• public enableEarlyIfConversion
• public enableIndirectBrExpand
• public enableJoinGlobalCopies
• public enableMachinePipeliner
• public enableMachineSchedDefaultSched
• public enableMachineScheduler
• public enablePostRAMachineScheduler
• public enablePostRAScheduler
• public enableRALocalReassignment
• public enableSubRegLiveness
• public getAntiDepBreakMode
• public getCallLowering
• public getCriticalPathRCs
• public getCustomPBQPConstraints
• public getDAGScheduler
• public getFrameLowering
• public getInlineAsmLowering
• public getInstrInfo
• public getInstrItineraryData
• public getInstructionSelector
• public getLegalizerInfo
• public getOptLevelToEnablePostRAScheduler
• public getPostRAMutations
• public getRegBankInfo
• public getRegisterInfo
• public getSMSMutations
• public getSelectionDAGInfo
• public getTargetLowering
• public ignoreCSRForAllocationOrder
• public isDependencyBreaking
• public isOptimizableRegisterMove
• public isXRaySupported
• public isZeroIdiom
• public mirFileLoaded
• public overrideSchedPolicy
• public resolveSchedClass
• public useAA
• public useDFAforSMS

Inherited from MCSubtargetInfo:

• public ApplyFeatureFlag
• public ClearFeatureBitsTransitively
• protected InitMCProcessorInfo
• public SetFeatureBitsTransitively
• public ToggleFeature
• public ToggleFeature
• public ToggleFeature
• public checkFeatures
• public enableWritePrefetching
• public getCPU
• public getCacheAssociativity
• public getCacheLineSize
• public getCacheLineSize
• public getCacheSize
• public getFeatureBits
• public getFeatureString
• public getHwMode
• public getInstrItineraryForCPU
• public getMaxPrefetchIterationsAhead
• public getMinPrefetchStride
• public getPrefetchDistance
• public getReadAdvanceCycles
• public getReadAdvanceEntries
• public getSchedModel
• public getSchedModelForCPU
• public getTargetTriple
• public getTuneCPU
• public getWriteLatencyEntry
• public getWriteProcResBegin
• public getWriteProcResEnd
• public hasFeature
• public initInstrItins
• public isCPUStringValid
• public resolveVariantSchedClass
• public setDefaultFeatures
• public setFeatureBits

Methods

¶X86GenSubtargetInfo(const llvm::Triple& TT,
                    llvm::StringRef CPU,
                    llvm::StringRef TuneCPU,
                    llvm::StringRef FS)

Declared at: build/lib/Target/X86/X86GenSubtargetInfo.inc:31398

Parameters

const llvm::Triple& TT

llvm::StringRef CPU

llvm::StringRef TuneCPU

llvm::StringRef FS

¶llvm::DFAPacketizer* createDFAPacketizer(
    const llvm::InstrItineraryData* IID) const

Declared at: build/lib/Target/X86/X86GenSubtargetInfo.inc:31402

Parameters

const llvm::InstrItineraryData* IID

¶bool isDependencyBreaking(
    const llvm::MachineInstr* MI,
    llvm::APInt& Mask) const

Description

Returns true if MI is a dependency breaking instruction for the subtarget. Similar in behavior to `isZeroIdiom`. However, it knows how to identify all dependency breaking instructions (i.e. not just zero-idioms). As for `isZeroIdiom`, this method returns a mask of "broken" dependencies. (See method `isZeroIdiom` for a detailed description of Mask).

Declared at: build/lib/Target/X86/X86GenSubtargetInfo.inc:31404

Parameters

const llvm::MachineInstr* MI

llvm::APInt& Mask

¶bool isOptimizableRegisterMove(
    const llvm::MachineInstr* MI) const

Description

Returns true if MI is a candidate for move elimination. A candidate for move elimination may be optimized out at register renaming stage. Subtargets can specify the set of optimizable moves by instantiating tablegen class `IsOptimizableRegisterMove` (see llvm/Target/TargetInstrPredicate.td). SubtargetEmitter is responsible for processing all the definitions of class IsOptimizableRegisterMove, and auto-generate an override for this method.

Declared at: build/lib/Target/X86/X86GenSubtargetInfo.inc:31405

Parameters

const llvm::MachineInstr* MI

¶bool isZeroIdiom(const llvm::MachineInstr* MI,
                 llvm::APInt& Mask) const

Description

Returns true if MI is a dependency breaking zero-idiom instruction for the subtarget. This function also sets bits in Mask related to input operands that are not in a data dependency relationship. There is one bit for each machine operand; implicit operands follow explicit operands in the bit representation used for Mask. An empty (i.e. a mask with all bits cleared) means: data dependencies are "broken" for all the explicit input machine operands of MI.

Declared at: build/lib/Target/X86/X86GenSubtargetInfo.inc:31403

Parameters

const llvm::MachineInstr* MI

llvm::APInt& Mask

¶unsigned int resolveSchedClass(
    unsigned int SchedClass,
    const llvm::MachineInstr* DefMI,
    const llvm::TargetSchedModel* SchedModel)
    const

Description

Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant property. This may return the ID of another variant SchedClass, but repeated invocation must quickly terminate in a nonvariant SchedClass.

Declared at: build/lib/Target/X86/X86GenSubtargetInfo.inc:31400

Parameters

unsigned int SchedClass

const llvm::MachineInstr* DefMI

const llvm::TargetSchedModel* SchedModel

¶unsigned int resolveVariantSchedClass(
    unsigned int SchedClass,
    const llvm::MCInst* MI,
    const llvm::MCInstrInfo* MCII,
    unsigned int CPUID) const

Description

Resolve a variant scheduling class for the given MCInst and CPU.

Declared at: build/lib/Target/X86/X86GenSubtargetInfo.inc:31401

Parameters

unsigned int SchedClass

const llvm::MCInst* MI

const llvm::MCInstrInfo* MCII

unsigned int CPUID