class TargetInstrInfo
Declaration
class TargetInstrInfo : public MCInstrInfo { /* full declaration omitted */ };
Description
TargetInstrInfo - Interface to description of machine instruction set
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:96
Inherits from: MCInstrInfo
Member Variables
- private std::unique_ptr<MIRFormatter> Formatter
- private unsigned int CallFrameSetupOpcode
- private unsigned int CallFrameDestroyOpcode
- private unsigned int CatchRetOpcode
- private unsigned int ReturnOpcode
- public static const unsigned int CommuteAnyOperandIndex = ~0U
Method Overview
- public virtual bool ClobbersPredicate(llvm::MachineInstr & MI, std::vector<MachineOperand> & Pred, bool SkipDead) const
- public virtual llvm::ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const llvm::TargetSubtargetInfo * STI, const llvm::ScheduleDAG * DAG) const
- public virtual llvm::ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const llvm::InstrItineraryData *, const llvm::ScheduleDAGMI * DAG) const
- public virtual llvm::ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const llvm::MachineFunction & MF) const
- public virtual llvm::ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const llvm::InstrItineraryData *, const llvm::ScheduleDAG * DAG) const
- public virtual llvm::DFAPacketizer * CreateTargetScheduleState(const llvm::TargetSubtargetInfo &) const
- public virtual bool FoldImmediate(llvm::MachineInstr & UseMI, llvm::MachineInstr & DefMI, llvm::Register Reg, llvm::MachineRegisterInfo * MRI) const
- public virtual bool PredicateInstruction(llvm::MachineInstr & MI, ArrayRef<llvm::MachineOperand> Pred) const
- public virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, llvm::MachineBasicBlock * NewDest) const
- public virtual bool SubsumesPredicate(ArrayRef<llvm::MachineOperand> Pred1, ArrayRef<llvm::MachineOperand> Pred2) const
- public TargetInstrInfo(unsigned int CFSetupOpcode = ~0U, unsigned int CFDestroyOpcode = ~0U, unsigned int CatchRetOpcode = ~0U, unsigned int ReturnOpcode = ~0U)
- public TargetInstrInfo(const llvm::TargetInstrInfo &)
- public virtual bool analyzeBranch(llvm::MachineBasicBlock & MBB, llvm::MachineBasicBlock *& TBB, llvm::MachineBasicBlock *& FBB, SmallVectorImpl<llvm::MachineOperand> & Cond, bool AllowModify = false) const
- public virtual bool analyzeBranchPredicate(llvm::MachineBasicBlock & MBB, llvm::TargetInstrInfo::MachineBranchPredicate & MBP, bool AllowModify = false) const
- public virtual bool analyzeCompare(const llvm::MachineInstr & MI, llvm::Register & SrcReg, llvm::Register & SrcReg2, int64_t & Mask, int64_t & Value) const
- public virtual bool analyzeLoop(llvm::MachineLoop & L, llvm::MachineInstr *& IndVarInst, llvm::MachineInstr *& CmpInst) const
- public virtual std::unique_ptr<PipelinerLoopInfo> analyzeLoopForPipelining(llvm::MachineBasicBlock * LoopBB) const
- public virtual bool analyzeSelect(const llvm::MachineInstr & MI, SmallVectorImpl<llvm::MachineOperand> & Cond, unsigned int & TrueOp, unsigned int & FalseOp, bool & Optimizable) const
- public virtual bool areLoadsFromSameBasePtr(llvm::SDNode * Load1, llvm::SDNode * Load2, int64_t & Offset1, int64_t & Offset2) const
- public virtual bool areMemAccessesTriviallyDisjoint(const llvm::MachineInstr & MIa, const llvm::MachineInstr & MIb) const
- public virtual void breakPartialRegDependency(llvm::MachineInstr & MI, unsigned int OpNum, const llvm::TargetRegisterInfo * TRI) const
- public virtual void buildOutlinedFrame(llvm::MachineBasicBlock & MBB, llvm::MachineFunction & MF, const outliner::OutlinedFunction & OF) const
- public virtual bool canCopyGluedNodeDuringSchedule(llvm::SDNode * N) const
- public virtual bool canInsertSelect(const llvm::MachineBasicBlock & MBB, ArrayRef<llvm::MachineOperand> Cond, llvm::Register DstReg, llvm::Register TrueReg, llvm::Register FalseReg, int & CondCycles, int & TrueCycles, int & FalseCycles) const
- public virtual bool canMakeTailCallConditional(SmallVectorImpl<llvm::MachineOperand> & Cond, const llvm::MachineInstr & TailCall) const
- public llvm::MachineInstr * commuteInstruction(llvm::MachineInstr & MI, bool NewMI = false, unsigned int OpIdx1 = CommuteAnyOperandIndex, unsigned int OpIdx2 = CommuteAnyOperandIndex) const
- protected virtual llvm::MachineInstr * commuteInstructionImpl(llvm::MachineInstr & MI, bool NewMI, unsigned int OpIdx1, unsigned int OpIdx2) const
- public virtual llvm::MachineInstr * convertToThreeAddress(llvm::MachineInstr & MI, llvm::LiveVariables * LV, llvm::LiveIntervals * LIS) const
- public virtual void copyPhysReg(llvm::MachineBasicBlock & MBB, MachineBasicBlock::iterator MI, const llvm::DebugLoc & DL, llvm::MCRegister DestReg, llvm::MCRegister SrcReg, bool KillSrc) const
- public virtual std::string createMIROperandComment(const llvm::MachineInstr & MI, const llvm::MachineOperand & Op, unsigned int OpIdx, const llvm::TargetRegisterInfo * TRI) const
- public virtual llvm::MachineInstr * createPHIDestinationCopy(llvm::MachineBasicBlock & MBB, MachineBasicBlock::iterator InsPt, const llvm::DebugLoc & DL, llvm::Register Src, llvm::Register Dst) const
- public virtual llvm::MachineInstr * createPHISourceCopy(llvm::MachineBasicBlock & MBB, MachineBasicBlock::iterator InsPt, const llvm::DebugLoc & DL, llvm::Register Src, unsigned int SrcSubReg, llvm::Register Dst) const
- public virtual std::pair<unsigned int, unsigned int> decomposeMachineOperandsTargetFlags(unsigned int) const
- public unsigned int defaultDefLatency(const llvm::MCSchedModel & SchedModel, const llvm::MachineInstr & DefMI) const
- public virtual Optional<llvm::ParamLoadedValue> describeLoadedValue(const llvm::MachineInstr & MI, llvm::Register Reg) const
- public virtual llvm::MachineInstr & duplicate(llvm::MachineBasicBlock & MBB, MachineBasicBlock::iterator InsertBefore, const llvm::MachineInstr & Orig) const
- public virtual bool expandPostRAPseudo(llvm::MachineInstr & MI) const
- public virtual unsigned int extraSizeToPredicateInstructions(const llvm::MachineFunction & MF, unsigned int NumInsts) const
- public virtual void finalizeInsInstrs(llvm::MachineInstr & Root, llvm::MachineCombinerPattern & P, SmallVectorImpl<llvm::MachineInstr *> & InsInstrs) const
- public virtual bool findCommutedOpIndices(const llvm::MachineInstr & MI, unsigned int & SrcOpIdx1, unsigned int & SrcOpIdx2) const
- protected static bool fixCommutedOpIndices(unsigned int & ResultIdx1, unsigned int & ResultIdx2, unsigned int CommutableOpIdx1, unsigned int CommutableOpIdx2)
- public llvm::MachineInstr * foldMemoryOperand(llvm::MachineInstr & MI, ArrayRef<unsigned int> Ops, int FI, llvm::LiveIntervals * LIS = nullptr, llvm::VirtRegMap * VRM = nullptr) const
- public llvm::MachineInstr * foldMemoryOperand(llvm::MachineInstr & MI, ArrayRef<unsigned int> Ops, llvm::MachineInstr & LoadMI, llvm::LiveIntervals * LIS = nullptr) const
- protected virtual llvm::MachineInstr * foldMemoryOperandImpl(llvm::MachineFunction & MF, llvm::MachineInstr & MI, ArrayRef<unsigned int> Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, llvm::LiveIntervals * LIS = nullptr, llvm::VirtRegMap * VRM = nullptr) const
- protected virtual llvm::MachineInstr * foldMemoryOperandImpl(llvm::MachineFunction & MF, llvm::MachineInstr & MI, ArrayRef<unsigned int> Ops, MachineBasicBlock::iterator InsertPt, llvm::MachineInstr & LoadMI, llvm::LiveIntervals * LIS = nullptr) const
- public virtual void genAlternativeCodeSequence(llvm::MachineInstr & Root, llvm::MachineCombinerPattern Pattern, SmallVectorImpl<llvm::MachineInstr *> & InsInstrs, SmallVectorImpl<llvm::MachineInstr *> & DelInstrs, DenseMap<unsigned int, unsigned int> & InstIdxForVirtReg) const
- public virtual Optional<llvm::ExtAddrMode> getAddrModeFromMemoryOp(const llvm::MachineInstr & MemI, const llvm::TargetRegisterInfo * TRI) const
- public virtual bool getBaseAndOffsetPosition(const llvm::MachineInstr & MI, unsigned int & BasePos, unsigned int & OffsetPos) const
- public virtual llvm::MachineBasicBlock * getBranchDestBlock(const llvm::MachineInstr & MI) const
- public unsigned int getCallFrameDestroyOpcode() const
- public unsigned int getCallFrameSetupOpcode() const
- public virtual const llvm::MachineOperand & getCalleeOperand(const llvm::MachineInstr & MI) const
- public unsigned int getCatchReturnOpcode() const
- public virtual bool getConstValDefinedInReg(const llvm::MachineInstr & MI, const llvm::Register Reg, int64_t & ImmVal) const
- public virtual std::pair<uint16_t, uint16_t> getExecutionDomain(const llvm::MachineInstr & MI) const
- public virtual int getExtendResourceLenLimit() const
- public bool getExtractSubregInputs(const llvm::MachineInstr & MI, unsigned int DefIdx, llvm::TargetInstrInfo::RegSubRegPairAndIdx & InputReg) const
- protected virtual bool getExtractSubregLikeInputs(const llvm::MachineInstr & MI, unsigned int DefIdx, llvm::TargetInstrInfo::RegSubRegPairAndIdx & InputReg) const
- public int64_t getFrameSize(const llvm::MachineInstr & I) const
- public int64_t getFrameTotalSize(const llvm::MachineInstr & I) const
- public virtual bool getIncrementValue(const llvm::MachineInstr & MI, int & Value) const
- public virtual unsigned int getInlineAsmLength(const char * Str, const llvm::MCAsmInfo & MAI, const llvm::TargetSubtargetInfo * STI = nullptr) const
- public bool getInsertSubregInputs(const llvm::MachineInstr & MI, unsigned int DefIdx, llvm::TargetInstrInfo::RegSubRegPair & BaseReg, llvm::TargetInstrInfo::RegSubRegPairAndIdx & InsertedReg) const
- protected virtual bool getInsertSubregLikeInputs(const llvm::MachineInstr & MI, unsigned int DefIdx, llvm::TargetInstrInfo::RegSubRegPair & BaseReg, llvm::TargetInstrInfo::RegSubRegPairAndIdx & InsertedReg) const
- public virtual unsigned int getInstSizeInBytes(const llvm::MachineInstr & MI) const
- public virtual int getInstrLatency(const llvm::InstrItineraryData * ItinData, llvm::SDNode * Node) const
- public virtual unsigned int getInstrLatency(const llvm::InstrItineraryData * ItinData, const llvm::MachineInstr & MI, unsigned int * PredCost = nullptr) const
- public virtual const llvm::MIRFormatter * getMIRFormatter() const
- public virtual unsigned int getMachineCSELookAheadLimit() const
- public virtual bool getMachineCombinerPatterns(llvm::MachineInstr & Root, SmallVectorImpl<llvm::MachineCombinerPattern> & Patterns, bool DoRegPressureReduce) const
- public virtual unsigned int getMemOperandAACheckLimit() const
- public bool getMemOperandWithOffset(const llvm::MachineInstr & MI, const llvm::MachineOperand *& BaseOp, int64_t & Offset, bool & OffsetIsScalable, const llvm::TargetRegisterInfo * TRI) const
- public virtual bool getMemOperandsWithOffsetWidth(const llvm::MachineInstr & MI, SmallVectorImpl<const llvm::MachineOperand *> & BaseOps, int64_t & Offset, bool & OffsetIsScalable, unsigned int & Width, const llvm::TargetRegisterInfo * TRI) const
- public virtual llvm::MCInst getNop() const
- public virtual unsigned int getNumMicroOps(const llvm::InstrItineraryData * ItinData, const llvm::MachineInstr & MI) const
- public virtual unsigned int getOpcodeAfterMemoryUnfold(unsigned int Opc, bool UnfoldLoad, bool UnfoldStore, unsigned int * LoadRegIndex = nullptr) const
- public virtual int getOperandLatency(const llvm::InstrItineraryData * ItinData, const llvm::MachineInstr & DefMI, unsigned int DefIdx, const llvm::MachineInstr & UseMI, unsigned int UseIdx) const
- public virtual int getOperandLatency(const llvm::InstrItineraryData * ItinData, llvm::SDNode * DefNode, unsigned int DefIdx, llvm::SDNode * UseNode, unsigned int UseIdx) const
- public virtual outliner::OutlinedFunction getOutliningCandidateInfo(std::vector<outliner::Candidate> & RepeatedSequenceLocs) const
- public virtual outliner::InstrType getOutliningType(MachineBasicBlock::iterator & MIT, unsigned int Flags) const
- public virtual unsigned int getPartialRegUpdateClearance(const llvm::MachineInstr & MI, unsigned int OpNum, const llvm::TargetRegisterInfo * TRI) const
- public virtual std::pair<unsigned int, unsigned int> getPatchpointUnfoldableRange(const llvm::MachineInstr & MI) const
- public virtual unsigned int getPredicationCost(const llvm::MachineInstr & MI) const
- public virtual const llvm::TargetRegisterClass * getRegClass(const llvm::MCInstrDesc & MCID, unsigned int OpNum, const llvm::TargetRegisterInfo * TRI, const llvm::MachineFunction & MF) const
- public bool getRegSequenceInputs(const llvm::MachineInstr & MI, unsigned int DefIdx, SmallVectorImpl<llvm::TargetInstrInfo::RegSubRegPairAndIdx> & InputRegs) const
- protected virtual bool getRegSequenceLikeInputs(const llvm::MachineInstr & MI, unsigned int DefIdx, SmallVectorImpl<llvm::TargetInstrInfo::RegSubRegPairAndIdx> & InputRegs) const
- public unsigned int getReturnOpcode() const
- public virtual int getSPAdjust(const llvm::MachineInstr & MI) const
- public virtual ArrayRef<std::pair<unsigned int, const char *>> getSerializableBitmaskMachineOperandTargetFlags() const
- public virtual ArrayRef<std::pair<unsigned int, const char *>> getSerializableDirectMachineOperandTargetFlags() const
- public virtual ArrayRef<std::pair<MachineMemOperand::Flags, const char *>> getSerializableMachineMemOperandTargetFlags() const
- public virtual ArrayRef<std::pair<int, const char *>> getSerializableTargetIndices() const
- public virtual bool getStackSlotRange(const llvm::TargetRegisterClass * RC, unsigned int SubIdx, unsigned int & Size, unsigned int & Offset, const llvm::MachineFunction & MF) const
- public virtual unsigned int getTailDuplicateSize(CodeGenOpt::Level OptLevel) const
- public virtual unsigned int getUndefRegClearance(const llvm::MachineInstr & MI, unsigned int OpNum, const llvm::TargetRegisterInfo * TRI) const
- public virtual bool hasCommutePreference(llvm::MachineInstr & MI, bool & Commute) const
- public virtual bool hasHighOperandLatency(const llvm::TargetSchedModel & SchedModel, const llvm::MachineRegisterInfo * MRI, const llvm::MachineInstr & DefMI, unsigned int DefIdx, const llvm::MachineInstr & UseMI, unsigned int UseIdx) const
- public virtual bool hasLoadFromStackSlot(const llvm::MachineInstr & MI, SmallVectorImpl<const llvm::MachineMemOperand *> & Accesses) const
- public virtual bool hasLowDefLatency(const llvm::TargetSchedModel & SchedModel, const llvm::MachineInstr & DefMI, unsigned int DefIdx) const
- public virtual bool hasReassociableOperands(const llvm::MachineInstr & Inst, const llvm::MachineBasicBlock * MBB) const
- public bool hasReassociableSibling(const llvm::MachineInstr & Inst, bool & Commuted) const
- public virtual bool hasStoreToStackSlot(const llvm::MachineInstr & MI, SmallVectorImpl<const llvm::MachineMemOperand *> & Accesses) const
- public virtual unsigned int insertBranch(llvm::MachineBasicBlock & MBB, llvm::MachineBasicBlock * TBB, llvm::MachineBasicBlock * FBB, ArrayRef<llvm::MachineOperand> Cond, const llvm::DebugLoc & DL, int * BytesAdded = nullptr) const
- public virtual void insertIndirectBranch(llvm::MachineBasicBlock & MBB, llvm::MachineBasicBlock & NewDestBB, llvm::MachineBasicBlock & RestoreBB, const llvm::DebugLoc & DL, int64_t BrOffset = 0, llvm::RegScavenger * RS = nullptr) const
- public virtual void insertNoop(llvm::MachineBasicBlock & MBB, MachineBasicBlock::iterator MI) const
- public virtual void insertNoops(llvm::MachineBasicBlock & MBB, MachineBasicBlock::iterator MI, unsigned int Quantity) const
- public virtual MachineBasicBlock::iterator insertOutlinedCall(llvm::Module & M, llvm::MachineBasicBlock & MBB, MachineBasicBlock::iterator & It, llvm::MachineFunction & MF, outliner::Candidate & C) const
- public virtual void insertSelect(llvm::MachineBasicBlock & MBB, MachineBasicBlock::iterator I, const llvm::DebugLoc & DL, llvm::Register DstReg, ArrayRef<llvm::MachineOperand> Cond, llvm::Register TrueReg, llvm::Register FalseReg) const
- public unsigned int insertUnconditionalBranch(llvm::MachineBasicBlock & MBB, llvm::MachineBasicBlock * DestBB, const llvm::DebugLoc & DL, int * BytesAdded = nullptr) const
- public virtual Optional<llvm::RegImmPair> isAddImmediate(const llvm::MachineInstr & MI, llvm::Register Reg) const
- public virtual bool isAsCheapAsAMove(const llvm::MachineInstr & MI) const
- public virtual bool isAssociativeAndCommutative(const llvm::MachineInstr & Inst) const
- public virtual bool isBasicBlockPrologue(const llvm::MachineInstr & MI) const
- public virtual bool isBranchOffsetInRange(unsigned int BranchOpc, int64_t BrOffset) const
- public virtual bool isCoalescableExtInstr(const llvm::MachineInstr & MI, llvm::Register & SrcReg, llvm::Register & DstReg, unsigned int & SubIdx) const
- public Optional<llvm::DestSourcePair> isCopyInstr(const llvm::MachineInstr & MI) const
- protected virtual Optional<llvm::DestSourcePair> isCopyInstrImpl(const llvm::MachineInstr & MI) const
- public virtual bool isExtendLikelyToBeFolded(llvm::MachineInstr & ExtMI, llvm::MachineRegisterInfo & MRI) const
- public bool isFrameInstr(const llvm::MachineInstr & I) const
- public bool isFrameSetup(const llvm::MachineInstr & I) const
- public virtual bool isFunctionSafeToOutlineFrom(llvm::MachineFunction & MF, bool OutlineFromLinkOnceODRs) const
- public static bool isGenericOpcode(unsigned int Opc)
- public virtual bool isHighLatencyDef(int opc) const
- public virtual bool isIgnorableUse(const llvm::MachineOperand & MO) const
- public virtual bool isLegalToSplitMBBAt(llvm::MachineBasicBlock & MBB, MachineBasicBlock::iterator MBBI) const
- public virtual unsigned int isLoadFromStackSlot(const llvm::MachineInstr & MI, int & FrameIndex) const
- public virtual unsigned int isLoadFromStackSlot(const llvm::MachineInstr & MI, int & FrameIndex, unsigned int & MemBytes) const
- public virtual unsigned int isLoadFromStackSlotPostFE(const llvm::MachineInstr & MI, int & FrameIndex) const
- public virtual bool isMBBSafeToOutlineFrom(llvm::MachineBasicBlock & MBB, unsigned int & Flags) const
- public virtual bool isPCRelRegisterOperandLegal(const llvm::MachineOperand & MO) const
- public virtual bool isPostIncrement(const llvm::MachineInstr & MI) const
- public virtual bool isPredicable(const llvm::MachineInstr & MI) const
- public virtual bool isPredicated(const llvm::MachineInstr & MI) const
- public virtual bool isProfitableToDupForIfCvt(llvm::MachineBasicBlock & MBB, unsigned int NumCycles, llvm::BranchProbability Probability) const
- public virtual bool isProfitableToIfCvt(llvm::MachineBasicBlock & MBB, unsigned int NumCycles, unsigned int ExtraPredCycles, llvm::BranchProbability Probability) const
- public virtual bool isProfitableToIfCvt(llvm::MachineBasicBlock & TMBB, unsigned int NumTCycles, unsigned int ExtraTCycles, llvm::MachineBasicBlock & FMBB, unsigned int NumFCycles, unsigned int ExtraFCycles, llvm::BranchProbability Probability) const
- public virtual bool isProfitableToUnpredicate(llvm::MachineBasicBlock & TMBB, llvm::MachineBasicBlock & FMBB) const
- protected virtual bool isReallyTriviallyReMaterializable(const llvm::MachineInstr & MI) const
- private bool isReallyTriviallyReMaterializableGeneric(const llvm::MachineInstr & MI) const
- public bool isReassociationCandidate(const llvm::MachineInstr & Inst, bool & Commuted) const
- public virtual bool isSafeToMoveRegClassDefs(const llvm::TargetRegisterClass * RC) const
- public virtual bool isSchedulingBoundary(const llvm::MachineInstr & MI, const llvm::MachineBasicBlock * MBB, const llvm::MachineFunction & MF) const
- public virtual bool isStackSlotCopy(const llvm::MachineInstr & MI, int & DestFrameIndex, int & SrcFrameIndex) const
- public virtual unsigned int isStoreToStackSlot(const llvm::MachineInstr & MI, int & FrameIndex) const
- public virtual unsigned int isStoreToStackSlot(const llvm::MachineInstr & MI, int & FrameIndex, unsigned int & MemBytes) const
- public virtual unsigned int isStoreToStackSlotPostFE(const llvm::MachineInstr & MI, int & FrameIndex) const
- public virtual bool isSubregFoldable() const
- public virtual bool isTailCall(const llvm::MachineInstr & Inst) const
- public virtual bool isThroughputPattern(llvm::MachineCombinerPattern Pattern) const
- public bool isTriviallyReMaterializable(const llvm::MachineInstr & MI) const
- public virtual bool isUnconditionalTailCall(const llvm::MachineInstr & MI) const
- public bool isUnpredicatedTerminator(const llvm::MachineInstr & MI) const
- public bool isUnspillableTerminator(const llvm::MachineInstr * MI) const
- protected virtual bool isUnspillableTerminatorImpl(const llvm::MachineInstr * MI) const
- public bool isZeroCost(unsigned int Opcode) const
- public virtual void loadRegFromStackSlot(llvm::MachineBasicBlock & MBB, MachineBasicBlock::iterator MI, llvm::Register DestReg, int FrameIndex, const llvm::TargetRegisterClass * RC, const llvm::TargetRegisterInfo * TRI) const
- public virtual void mergeOutliningCandidateAttributes(llvm::Function & F, std::vector<outliner::Candidate> & Candidates) const
- public virtual bool optimizeCompareInstr(llvm::MachineInstr & CmpInstr, llvm::Register SrcReg, llvm::Register SrcReg2, int64_t Mask, int64_t Value, const llvm::MachineRegisterInfo * MRI) const
- public virtual bool optimizeCondBranch(llvm::MachineInstr & MI) const
- public virtual llvm::MachineInstr * optimizeLoadInstr(llvm::MachineInstr & MI, const llvm::MachineRegisterInfo * MRI, llvm::Register & FoldAsLoadDefReg, llvm::MachineInstr *& DefMI) const
- public virtual llvm::MachineInstr * optimizeSelect(llvm::MachineInstr & MI, SmallPtrSetImpl<llvm::MachineInstr *> & NewMIs, bool PreferFalse = false) const
- public virtual unsigned int predictBranchSizeForIfCvt(llvm::MachineInstr & MI) const
- public virtual bool preservesZeroValueInReg(const llvm::MachineInstr * MI, const llvm::Register NullValueReg, const llvm::TargetRegisterInfo * TRI) const
- public virtual bool produceSameValue(const llvm::MachineInstr & MI0, const llvm::MachineInstr & MI1, const llvm::MachineRegisterInfo * MRI = nullptr) const
- public virtual void reMaterialize(llvm::MachineBasicBlock & MBB, MachineBasicBlock::iterator MI, llvm::Register DestReg, unsigned int SubIdx, const llvm::MachineInstr & Orig, const llvm::TargetRegisterInfo & TRI) const
- public void reassociateOps(llvm::MachineInstr & Root, llvm::MachineInstr & Prev, llvm::MachineCombinerPattern Pattern, SmallVectorImpl<llvm::MachineInstr *> & InsInstrs, SmallVectorImpl<llvm::MachineInstr *> & DelInstrs, DenseMap<unsigned int, unsigned int> & InstrIdxForVirtReg) const
- public virtual unsigned int reduceLoopCount(llvm::MachineBasicBlock & MBB, llvm::MachineBasicBlock & PreHeader, llvm::MachineInstr * IndVar, llvm::MachineInstr & Cmp, SmallVectorImpl<llvm::MachineOperand> & Cond, SmallVectorImpl<llvm::MachineInstr *> & PrevInsts, unsigned int Iter, unsigned int MaxIter) const
- public virtual unsigned int removeBranch(llvm::MachineBasicBlock & MBB, int * BytesRemoved = nullptr) const
- public virtual void replaceBranchWithTailCall(llvm::MachineBasicBlock & MBB, SmallVectorImpl<llvm::MachineOperand> & Cond, const llvm::MachineInstr & TailCall) const
- public virtual bool reverseBranchCondition(SmallVectorImpl<llvm::MachineOperand> & Cond) const
- public virtual void setExecutionDomain(llvm::MachineInstr & MI, unsigned int Domain) const
- public virtual void setSpecialOperandAttr(llvm::MachineInstr & OldMI1, llvm::MachineInstr & OldMI2, llvm::MachineInstr & NewMI1, llvm::MachineInstr & NewMI2) const
- public virtual bool shouldClusterMemOps(ArrayRef<const llvm::MachineOperand *> BaseOps1, ArrayRef<const llvm::MachineOperand *> BaseOps2, unsigned int NumLoads, unsigned int NumBytes) const
- public virtual bool shouldHoist(const llvm::MachineInstr & MI, const llvm::MachineLoop * FromLoop) const
- public virtual bool shouldOutlineFromFunctionByDefault(llvm::MachineFunction & MF) const
- public virtual bool shouldReduceRegisterPressure(llvm::MachineBasicBlock * MBB, llvm::RegisterClassInfo * RegClassInfo) const
- public virtual bool shouldScheduleLoadsNear(llvm::SDNode * Load1, llvm::SDNode * Load2, int64_t Offset1, int64_t Offset2, unsigned int NumLoads) const
- public virtual bool shouldSink(const llvm::MachineInstr & MI) const
- public virtual void storeRegToStackSlot(llvm::MachineBasicBlock & MBB, MachineBasicBlock::iterator MI, llvm::Register SrcReg, bool isKill, int FrameIndex, const llvm::TargetRegisterClass * RC, const llvm::TargetRegisterInfo * TRI) const
- public virtual bool unfoldMemoryOperand(llvm::SelectionDAG & DAG, llvm::SDNode * N, SmallVectorImpl<llvm::SDNode *> & NewNodes) const
- public virtual bool unfoldMemoryOperand(llvm::MachineFunction & MF, llvm::MachineInstr & MI, unsigned int Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<llvm::MachineInstr *> & NewMIs) const
- public virtual bool useMachineCombiner() const
- public bool usePreRAHazardRecognizer() const
- public virtual bool verifyInstruction(const llvm::MachineInstr & MI, llvm::StringRef & ErrInfo) const
- public virtual ~TargetInstrInfo()
Inherited from MCInstrInfo:
Methods
¶virtual bool ClobbersPredicate(
llvm::MachineInstr& MI,
std::vector<MachineOperand>& Pred,
bool SkipDead) const
virtual bool ClobbersPredicate(
llvm::MachineInstr& MI,
std::vector<MachineOperand>& Pred,
bool SkipDead) const
Description
If the specified instruction defines any predicate or condition code register(s) used for predication, returns true as well as the definition predicate(s) by reference. SkipDead should be set to false at any point that dead predicate instructions should be considered as being defined. A dead predicate instruction is one that is guaranteed to be removed after a call to PredicateInstruction.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1479
Parameters
- llvm::MachineInstr& MI
- std::vector<MachineOperand>& Pred
- bool SkipDead
¶virtual llvm::ScheduleHazardRecognizer*
CreateTargetHazardRecognizer(
const llvm::TargetSubtargetInfo* STI,
const llvm::ScheduleDAG* DAG) const
virtual llvm::ScheduleHazardRecognizer*
CreateTargetHazardRecognizer(
const llvm::TargetSubtargetInfo* STI,
const llvm::ScheduleDAG* DAG) const
Description
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1513
Parameters
- const llvm::TargetSubtargetInfo* STI
- const llvm::ScheduleDAG* DAG
¶virtual llvm::ScheduleHazardRecognizer*
CreateTargetMIHazardRecognizer(
const llvm::InstrItineraryData*,
const llvm::ScheduleDAGMI* DAG) const
virtual llvm::ScheduleHazardRecognizer*
CreateTargetMIHazardRecognizer(
const llvm::InstrItineraryData*,
const llvm::ScheduleDAGMI* DAG) const
Description
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1519
Parameters
- const llvm::InstrItineraryData*
- const llvm::ScheduleDAGMI* DAG
¶virtual llvm::ScheduleHazardRecognizer*
CreateTargetPostRAHazardRecognizer(
const llvm::MachineFunction& MF) const
virtual llvm::ScheduleHazardRecognizer*
CreateTargetPostRAHazardRecognizer(
const llvm::MachineFunction& MF) const
Description
Allocate and return a hazard recognizer to use for by non-scheduling passes.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1531
Parameters
- const llvm::MachineFunction& MF
¶virtual llvm::ScheduleHazardRecognizer*
CreateTargetPostRAHazardRecognizer(
const llvm::InstrItineraryData*,
const llvm::ScheduleDAG* DAG) const
virtual llvm::ScheduleHazardRecognizer*
CreateTargetPostRAHazardRecognizer(
const llvm::InstrItineraryData*,
const llvm::ScheduleDAG* DAG) const
Description
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions after register allocation.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1525
Parameters
- const llvm::InstrItineraryData*
- const llvm::ScheduleDAG* DAG
¶virtual llvm::DFAPacketizer*
CreateTargetScheduleState(
const llvm::TargetSubtargetInfo&) const
virtual llvm::DFAPacketizer*
CreateTargetScheduleState(
const llvm::TargetSubtargetInfo&) const
Description
Create machine specific model for scheduling.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1779
Parameters
- const llvm::TargetSubtargetInfo&
¶virtual bool FoldImmediate(
llvm::MachineInstr& UseMI,
llvm::MachineInstr& DefMI,
llvm::Register Reg,
llvm::MachineRegisterInfo* MRI) const
virtual bool FoldImmediate(
llvm::MachineInstr& UseMI,
llvm::MachineInstr& DefMI,
llvm::Register Reg,
llvm::MachineRegisterInfo* MRI) const
Description
'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction. If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true, then the caller may assume that DefMI has been erased from its parent block. The caller may assume that it will not be erased by this function otherwise.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1580
Parameters
- llvm::MachineInstr& UseMI
- llvm::MachineInstr& DefMI
- llvm::Register Reg
- llvm::MachineRegisterInfo* MRI
¶virtual bool PredicateInstruction(
llvm::MachineInstr& MI,
ArrayRef<llvm::MachineOperand> Pred) const
virtual bool PredicateInstruction(
llvm::MachineInstr& MI,
ArrayRef<llvm::MachineOperand> Pred) const
Description
Convert the instruction into a predicated instruction. It returns true if the operation was successful.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1462
Parameters
- llvm::MachineInstr& MI
- ArrayRef<llvm::MachineOperand> Pred
¶virtual void ReplaceTailWithBranchTo(
MachineBasicBlock::iterator Tail,
llvm::MachineBasicBlock* NewDest) const
virtual void ReplaceTailWithBranchTo(
MachineBasicBlock::iterator Tail,
llvm::MachineBasicBlock* NewDest) const
Description
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to NewDest. This is used by the tail merging pass.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:792
Parameters
- MachineBasicBlock::iterator Tail
- llvm::MachineBasicBlock* NewDest
¶virtual bool SubsumesPredicate(
ArrayRef<llvm::MachineOperand> Pred1,
ArrayRef<llvm::MachineOperand> Pred2) const
virtual bool SubsumesPredicate(
ArrayRef<llvm::MachineOperand> Pred1,
ArrayRef<llvm::MachineOperand> Pred2) const
Description
Returns true if the first specified predicate subsumes the second, e.g. GE subsumes GT.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1467
Parameters
¶TargetInstrInfo(
unsigned int CFSetupOpcode = ~0U,
unsigned int CFDestroyOpcode = ~0U,
unsigned int CatchRetOpcode = ~0U,
unsigned int ReturnOpcode = ~0U)
TargetInstrInfo(
unsigned int CFSetupOpcode = ~0U,
unsigned int CFDestroyOpcode = ~0U,
unsigned int CatchRetOpcode = ~0U,
unsigned int ReturnOpcode = ~0U)
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:98
Parameters
- unsigned int CFSetupOpcode = ~0U
- unsigned int CFDestroyOpcode = ~0U
- unsigned int CatchRetOpcode = ~0U
- unsigned int ReturnOpcode = ~0U
¶TargetInstrInfo(const llvm::TargetInstrInfo&)
TargetInstrInfo(const llvm::TargetInstrInfo&)
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:103
Parameters
- const llvm::TargetInstrInfo&
¶virtual bool analyzeBranch(
llvm::MachineBasicBlock& MBB,
llvm::MachineBasicBlock*& TBB,
llvm::MachineBasicBlock*& FBB,
SmallVectorImpl<llvm::MachineOperand>& Cond,
bool AllowModify = false) const
virtual bool analyzeBranch(
llvm::MachineBasicBlock& MBB,
llvm::MachineBasicBlock*& TBB,
llvm::MachineBasicBlock*& FBB,
SmallVectorImpl<llvm::MachineOperand>& Cond,
bool AllowModify = false) const
Description
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g. it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases: 1. If this block ends with no branches (it just falls through to its succ) just return false, leaving TBB/FBB null. 2. If this block ends with only an unconditional branch, it sets TBB to be the destination block. 3. If this block ends with a conditional branch and it falls through to a successor block, it sets TBB to be the branch destination block and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches. 4. If this block ends with a conditional branch followed by an unconditional branch, it returns the 'true' destination in TBB, the 'false' destination in FBB, and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches. Note that removeBranch and insertBranch must be implemented to support cases where this method returns success. If AllowModify is true, then this routine is allowed to modify the basic block (e.g. delete instructions after the unconditional branch). The CFG information in MBB.Predecessors and MBB.Successors must be valid before calling this function.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:634
Parameters
- llvm::MachineBasicBlock& MBB
- llvm::MachineBasicBlock*& TBB
- llvm::MachineBasicBlock*& FBB
- SmallVectorImpl<llvm::MachineOperand>& Cond
- bool AllowModify = false
¶virtual bool analyzeBranchPredicate(
llvm::MachineBasicBlock& MBB,
llvm::TargetInstrInfo::MachineBranchPredicate&
MBP,
bool AllowModify = false) const
virtual bool analyzeBranchPredicate(
llvm::MachineBasicBlock& MBB,
llvm::TargetInstrInfo::MachineBranchPredicate&
MBP,
bool AllowModify = false) const
Description
Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure if possible. Returns false on success and true on failure. If AllowModify is true, then this routine is allowed to modify the basic block (e.g. delete instructions after the unconditional branch).
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:676
Parameters
- llvm::MachineBasicBlock& MBB
- llvm::TargetInstrInfo::MachineBranchPredicate& MBP
- bool AllowModify = false
¶virtual bool analyzeCompare(
const llvm::MachineInstr& MI,
llvm::Register& SrcReg,
llvm::Register& SrcReg2,
int64_t& Mask,
int64_t& Value) const
virtual bool analyzeCompare(
const llvm::MachineInstr& MI,
llvm::Register& SrcReg,
llvm::Register& SrcReg2,
int64_t& Mask,
int64_t& Value) const
Description
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. Return true if the comparison instruction can be analyzed.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1543
Parameters
- const llvm::MachineInstr& MI
- llvm::Register& SrcReg
- llvm::Register& SrcReg2
- int64_t& Mask
- int64_t& Value
¶virtual bool analyzeLoop(
llvm::MachineLoop& L,
llvm::MachineInstr*& IndVarInst,
llvm::MachineInstr*& CmpInst) const
virtual bool analyzeLoop(
llvm::MachineLoop& L,
llvm::MachineInstr*& IndVarInst,
llvm::MachineInstr*& CmpInst) const
Description
Analyze the loop code, return true if it cannot be understood. Upon success, this function returns false and returns information about the induction variable and compare instruction used at the end.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:772
Parameters
- llvm::MachineLoop& L
- llvm::MachineInstr*& IndVarInst
- llvm::MachineInstr*& CmpInst
¶virtual std::unique_ptr<PipelinerLoopInfo>
analyzeLoopForPipelining(
llvm::MachineBasicBlock* LoopBB) const
virtual std::unique_ptr<PipelinerLoopInfo>
analyzeLoopForPipelining(
llvm::MachineBasicBlock* LoopBB) const
Description
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enough produce a PipelinerLoopInfo object.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:765
Parameters
- llvm::MachineBasicBlock* LoopBB
¶virtual bool analyzeSelect(
const llvm::MachineInstr& MI,
SmallVectorImpl<llvm::MachineOperand>& Cond,
unsigned int& TrueOp,
unsigned int& FalseOp,
bool& Optimizable) const
virtual bool analyzeSelect(
const llvm::MachineInstr& MI,
SmallVectorImpl<llvm::MachineOperand>& Cond,
unsigned int& TrueOp,
unsigned int& FalseOp,
bool& Optimizable) const
Description
Analyze the given select instruction, returning true if it cannot be understood. It is assumed that MI->isSelect() is true. When successful, return the controlling condition and the operands that determine the true and false result values. Result = SELECT Cond, TrueOp, FalseOp Some targets can optimize select instructions, for example by predicating the instruction defining one of the operands. Such targets should set Optimizable.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:935
Parameters
- const llvm::MachineInstr& MI
- Select instruction to analyze.
- SmallVectorImpl<llvm::MachineOperand>& Cond
- Condition controlling the select.
- unsigned int& TrueOp
- Operand number of the value selected when Cond is true.
- unsigned int& FalseOp
- Operand number of the value selected when Cond is false.
- bool& Optimizable
- Returned as true if MI is optimizable.
Returns
False on success.
¶virtual bool areLoadsFromSameBasePtr(
llvm::SDNode* Load1,
llvm::SDNode* Load2,
int64_t& Offset1,
int64_t& Offset2) const
virtual bool areLoadsFromSameBasePtr(
llvm::SDNode* Load1,
llvm::SDNode* Load2,
int64_t& Offset1,
int64_t& Offset2) const
Description
This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address. It should only return true if the base pointers are the same and the only differences between the two addresses are the offset. It also returns the offsets by reference.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1313
Parameters
- llvm::SDNode* Load1
- llvm::SDNode* Load2
- int64_t& Offset1
- int64_t& Offset2
¶virtual bool areMemAccessesTriviallyDisjoint(
const llvm::MachineInstr& MIa,
const llvm::MachineInstr& MIb) const
virtual bool areMemAccessesTriviallyDisjoint(
const llvm::MachineInstr& MIa,
const llvm::MachineInstr& MIb) const
Description
Sometimes, it is possible for the target to tell, even without aliasing information, that two MIs access different memory addresses. This function returns true if two MIs access different memory addresses and false otherwise. Assumes any physical registers used to compute addresses have the same value for both instructions. (This is the most useful assumption for post-RA scheduling.) See also MachineInstr::mayAlias, which is implemented on top of this function.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1795
Parameters
- const llvm::MachineInstr& MIa
- const llvm::MachineInstr& MIb
¶virtual void breakPartialRegDependency(
llvm::MachineInstr& MI,
unsigned int OpNum,
const llvm::TargetRegisterInfo* TRI) const
virtual void breakPartialRegDependency(
llvm::MachineInstr& MI,
unsigned int OpNum,
const llvm::TargetRegisterInfo* TRI) const
Description
Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum. If it wasn't possible to avoid a def in the last N instructions before MI (see getPartialRegUpdateClearance), this hook will be called to break the unwanted dependency. On x86, an xorps instruction can be used as a dependency breaker: addps %xmm1, %xmm0 movaps %xmm0, (%rax) xorps %xmm0, %xmm0 cvtsi2ss %rbx, %xmm0 An <imp -kill> operand should be added to MI if an instruction was inserted. This ties the instructions together in the post-ra scheduler.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1774
Parameters
- llvm::MachineInstr& MI
- unsigned int OpNum
- const llvm::TargetRegisterInfo* TRI
¶virtual void buildOutlinedFrame(
llvm::MachineBasicBlock& MBB,
llvm::MachineFunction& MF,
const outliner::OutlinedFunction& OF) const
virtual void buildOutlinedFrame(
llvm::MachineBasicBlock& MBB,
llvm::MachineFunction& MF,
const outliner::OutlinedFunction& OF) const
Description
Insert a custom frame for outlined functions.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1937
Parameters
- llvm::MachineBasicBlock& MBB
- llvm::MachineFunction& MF
- const outliner::OutlinedFunction& OF
¶virtual bool canCopyGluedNodeDuringSchedule(
llvm::SDNode* N) const
virtual bool canCopyGluedNodeDuringSchedule(
llvm::SDNode* N) const
Description
Return true if the given SDNode can be copied during scheduling even if it has glue.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1209
Parameters
- llvm::SDNode* N
¶virtual bool canInsertSelect(
const llvm::MachineBasicBlock& MBB,
ArrayRef<llvm::MachineOperand> Cond,
llvm::Register DstReg,
llvm::Register TrueReg,
llvm::Register FalseReg,
int& CondCycles,
int& TrueCycles,
int& FalseCycles) const
virtual bool canInsertSelect(
const llvm::MachineBasicBlock& MBB,
ArrayRef<llvm::MachineOperand> Cond,
llvm::Register DstReg,
llvm::Register TrueReg,
llvm::Register FalseReg,
int& CondCycles,
int& TrueCycles,
int& FalseCycles) const
Description
Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond. When successful, also return the latency in cycles from TrueReg, FalseReg, and Cond to the destination register. In most cases, a select instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1 Some x86 implementations have 2-cycle cmov instructions.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:887
Parameters
- const llvm::MachineBasicBlock& MBB
- Block where select instruction would be inserted.
- ArrayRef<llvm::MachineOperand> Cond
- Condition returned by analyzeBranch.
- llvm::Register DstReg
- Virtual dest register that the result should write to.
- llvm::Register TrueReg
- Virtual register to select when Cond is true.
- llvm::Register FalseReg
- Virtual register to select when Cond is false.
- int& CondCycles
- Latency from Cond+Branch to select output.
- int& TrueCycles
- Latency from TrueReg to select output.
- int& FalseCycles
- Latency from FalseReg to select output.
¶virtual bool canMakeTailCallConditional(
SmallVectorImpl<llvm::MachineOperand>& Cond,
const llvm::MachineInstr& TailCall) const
virtual bool canMakeTailCallConditional(
SmallVectorImpl<llvm::MachineOperand>& Cond,
const llvm::MachineInstr& TailCall) const
Description
Returns true if the tail call can be made conditional on BranchCond.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1448
Parameters
- SmallVectorImpl<llvm::MachineOperand>& Cond
- const llvm::MachineInstr& TailCall
¶llvm::MachineInstr* commuteInstruction(
llvm::MachineInstr& MI,
bool NewMI = false,
unsigned int OpIdx1 = CommuteAnyOperandIndex,
unsigned int OpIdx2 =
CommuteAnyOperandIndex) const
llvm::MachineInstr* commuteInstruction(
llvm::MachineInstr& MI,
bool NewMI = false,
unsigned int OpIdx1 = CommuteAnyOperandIndex,
unsigned int OpIdx2 =
CommuteAnyOperandIndex) const
Description
This method commutes the operands of the given machine instruction MI. The operands to be commuted are specified by their indices OpIdx1 and OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value 'CommuteAnyOperandIndex', which means that the method is free to choose any arbitrarily chosen commutable operand. If both arguments are set to 'CommuteAnyOperandIndex' then the method looks for 2 different commutable operands; then commutes them if such operands could be found. If NewMI is false, MI is modified in place and returned; otherwise, a new machine instruction is created and returned. Do not call this method for a non-commutable instruction or for non-commuable operands. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:453
Parameters
- llvm::MachineInstr& MI
- bool NewMI = false
- unsigned int OpIdx1 = CommuteAnyOperandIndex
- unsigned int OpIdx2 = CommuteAnyOperandIndex
¶virtual llvm::MachineInstr*
commuteInstructionImpl(llvm::MachineInstr& MI,
bool NewMI,
unsigned int OpIdx1,
unsigned int OpIdx2) const
virtual llvm::MachineInstr*
commuteInstructionImpl(llvm::MachineInstr& MI,
bool NewMI,
unsigned int OpIdx1,
unsigned int OpIdx2) const
Description
This method commutes the operands of the given machine instruction MI. The operands to be commuted are specified by their indices OpIdx1 and OpIdx2. If a target has any instructions that are commutable but require converting to different instructions or making non-trivial changes to commute them, this method can be overloaded to do that. The default implementation simply swaps the commutable operands. If NewMI is false, MI is modified in place and returned; otherwise, a new machine instruction is created and returned. Do not call this method for a non-commutable instruction. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:163
Parameters
- llvm::MachineInstr& MI
- bool NewMI
- unsigned int OpIdx1
- unsigned int OpIdx2
¶virtual llvm::MachineInstr* convertToThreeAddress(
llvm::MachineInstr& MI,
llvm::LiveVariables* LV,
llvm::LiveIntervals* LIS) const
virtual llvm::MachineInstr* convertToThreeAddress(
llvm::MachineInstr& MI,
llvm::LiveVariables* LV,
llvm::LiveIntervals* LIS) const
Description
This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target may be able to convert a two-address instruction into one or more true three-address instructions on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two-addressness. This method returns a null pointer if the transformation cannot be performed, otherwise it returns the last new instruction. If \p LIS is not nullptr, the LiveIntervals info should be updated for replacing \p MI with new instructions, even though this function does not remove MI.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:424
Parameters
¶virtual void copyPhysReg(
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator MI,
const llvm::DebugLoc& DL,
llvm::MCRegister DestReg,
llvm::MCRegister SrcReg,
bool KillSrc) const
virtual void copyPhysReg(
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator MI,
const llvm::DebugLoc& DL,
llvm::MCRegister DestReg,
llvm::MCRegister SrcReg,
bool KillSrc) const
Description
Emit instructions to copy a pair of physical registers. This function should support copies within any legal register class as well as any cross-class copies created during instruction selection. The source and destination registers may overlap, which may require a careful implementation when multiple copy instructions are required for large registers. See for example the ARM target.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:973
Parameters
- llvm::MachineBasicBlock& MBB
- MachineBasicBlock::iterator MI
- const llvm::DebugLoc& DL
- llvm::MCRegister DestReg
- llvm::MCRegister SrcReg
- bool KillSrc
¶virtual std::string createMIROperandComment(
const llvm::MachineInstr& MI,
const llvm::MachineOperand& Op,
unsigned int OpIdx,
const llvm::TargetRegisterInfo* TRI) const
virtual std::string createMIROperandComment(
const llvm::MachineInstr& MI,
const llvm::MachineOperand& Op,
unsigned int OpIdx,
const llvm::TargetRegisterInfo* TRI) const
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1435
Parameters
- const llvm::MachineInstr& MI
- const llvm::MachineOperand& Op
- unsigned int OpIdx
- const llvm::TargetRegisterInfo* TRI
¶virtual llvm::MachineInstr*
createPHIDestinationCopy(
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator InsPt,
const llvm::DebugLoc& DL,
llvm::Register Src,
llvm::Register Dst) const
virtual llvm::MachineInstr*
createPHIDestinationCopy(
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator InsPt,
const llvm::DebugLoc& DL,
llvm::Register Src,
llvm::Register Dst) const
Description
During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destination register in a target specific manner.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1891
Parameters
- llvm::MachineBasicBlock& MBB
- MachineBasicBlock::iterator InsPt
- const llvm::DebugLoc& DL
- llvm::Register Src
- llvm::Register Dst
¶virtual llvm::MachineInstr* createPHISourceCopy(
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator InsPt,
const llvm::DebugLoc& DL,
llvm::Register Src,
unsigned int SrcSubReg,
llvm::Register Dst) const
virtual llvm::MachineInstr* createPHISourceCopy(
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator InsPt,
const llvm::DebugLoc& DL,
llvm::Register Src,
unsigned int SrcSubReg,
llvm::Register Dst) const
Description
During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destination register in a target specific manner.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1901
Parameters
- llvm::MachineBasicBlock& MBB
- MachineBasicBlock::iterator InsPt
- const llvm::DebugLoc& DL
- llvm::Register Src
- unsigned int SrcSubReg
- llvm::Register Dst
¶virtual std::pair<unsigned int, unsigned int>
decomposeMachineOperandsTargetFlags(
unsigned int) const
virtual std::pair<unsigned int, unsigned int>
decomposeMachineOperandsTargetFlags(
unsigned int) const
Description
Decompose the machine operand's target flags into two values - the direct target flag value and any of bit flags that are applied.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1840
Parameters
- unsigned int
¶unsigned int defaultDefLatency(
const llvm::MCSchedModel& SchedModel,
const llvm::MachineInstr& DefMI) const
unsigned int defaultDefLatency(
const llvm::MCSchedModel& SchedModel,
const llvm::MachineInstr& DefMI) const
Description
Return the default expected latency for a def based on its opcode.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1630
Parameters
- const llvm::MCSchedModel& SchedModel
- const llvm::MachineInstr& DefMI
¶virtual Optional<llvm::ParamLoadedValue>
describeLoadedValue(const llvm::MachineInstr& MI,
llvm::Register Reg) const
virtual Optional<llvm::ParamLoadedValue>
describeLoadedValue(const llvm::MachineInstr& MI,
llvm::Register Reg) const
Description
Produce the expression describing the \p MI loading a value into the physical register \p Reg. This hook should only be used with\p MIs belonging to VReg-less functions.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1972
Parameters
- const llvm::MachineInstr& MI
- llvm::Register Reg
¶virtual llvm::MachineInstr& duplicate(
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator InsertBefore,
const llvm::MachineInstr& Orig) const
virtual llvm::MachineInstr& duplicate(
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator InsertBefore,
const llvm::MachineInstr& Orig) const
Description
Clones instruction or the whole instruction bundle \p Orig and insert into \p MBB before \p InsertBefore. The target may update operands that are required to be unique. \p Orig must not return true for MachineInstr::isNotDuplicable().
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:407
Parameters
- llvm::MachineBasicBlock& MBB
- MachineBasicBlock::iterator InsertBefore
- const llvm::MachineInstr& Orig
¶virtual bool expandPostRAPseudo(
llvm::MachineInstr& MI) const
virtual bool expandPostRAPseudo(
llvm::MachineInstr& MI) const
Description
This function is called for all pseudo instructions that remain after register allocation. Many pseudo instructions are created to help register allocation. This is the place to convert them into real instructions. The target can edit MI in place, or it can insert new instructions and erase MI. The function should return true if anything was changed.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1077
Parameters
¶virtual unsigned int
extraSizeToPredicateInstructions(
const llvm::MachineFunction& MF,
unsigned int NumInsts) const
virtual unsigned int
extraSizeToPredicateInstructions(
const llvm::MachineFunction& MF,
unsigned int NumInsts) const
Description
Return the increase in code size needed to predicate a contiguous run of NumInsts instructions.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:842
Parameters
- const llvm::MachineFunction& MF
- unsigned int NumInsts
¶virtual void finalizeInsInstrs(
llvm::MachineInstr& Root,
llvm::MachineCombinerPattern& P,
SmallVectorImpl<llvm::MachineInstr*>&
InsInstrs) const
virtual void finalizeInsInstrs(
llvm::MachineInstr& Root,
llvm::MachineCombinerPattern& P,
SmallVectorImpl<llvm::MachineInstr*>&
InsInstrs) const
Description
Fix up the placeholder we may add in genAlternativeCodeSequence().
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1144
Parameters
- llvm::MachineInstr& Root
- llvm::MachineCombinerPattern& P
- SmallVectorImpl<llvm::MachineInstr*>& InsInstrs
¶virtual bool findCommutedOpIndices(
const llvm::MachineInstr& MI,
unsigned int& SrcOpIdx1,
unsigned int& SrcOpIdx2) const
virtual bool findCommutedOpIndices(
const llvm::MachineInstr& MI,
unsigned int& SrcOpIdx1,
unsigned int& SrcOpIdx2) const
Description
Returns true iff the routine could find two commutable operands in the given machine instruction. The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. If any of the INPUT values is set to the special value 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable operand, then returns its index in the corresponding argument. If both of INPUT values are set to 'CommuteAnyOperandIndex' then method looks for 2 commutable operands. If INPUT values refer to some operands of MI, then the method simply returns true if the corresponding operands are commutable and returns false otherwise. For example, calling this method this way: unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; findCommutedOpIndices(MI, Op1, Op2); can be interpreted as a query asking to find an operand that would be commutable with the operand#1.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:474
Parameters
- const llvm::MachineInstr& MI
- unsigned int& SrcOpIdx1
- unsigned int& SrcOpIdx2
¶static bool fixCommutedOpIndices(
unsigned int& ResultIdx1,
unsigned int& ResultIdx2,
unsigned int CommutableOpIdx1,
unsigned int CommutableOpIdx2)
static bool fixCommutedOpIndices(
unsigned int& ResultIdx1,
unsigned int& ResultIdx2,
unsigned int CommutableOpIdx1,
unsigned int CommutableOpIdx2)
Description
Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1, ResultIdx2). One or both input values of the pair: (ResultIdx1, ResultIdx2) may be predefined to some indices or be undefined (designated by the special value 'CommuteAnyOperandIndex'). The predefined result indices cannot be re-defined. The function returns true iff after the result pair redefinition the fixed result pair is equal to or equivalent to the source pair of indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that the pairs (x,y) and (y,x) are equivalent.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:177
Parameters
- unsigned int& ResultIdx1
- unsigned int& ResultIdx2
- unsigned int CommutableOpIdx1
- unsigned int CommutableOpIdx2
¶llvm::MachineInstr* foldMemoryOperand(
llvm::MachineInstr& MI,
ArrayRef<unsigned int> Ops,
int FI,
llvm::LiveIntervals* LIS = nullptr,
llvm::VirtRegMap* VRM = nullptr) const
llvm::MachineInstr* foldMemoryOperand(
llvm::MachineInstr& MI,
ArrayRef<unsigned int> Ops,
int FI,
llvm::LiveIntervals* LIS = nullptr,
llvm::VirtRegMap* VRM = nullptr) const
Description
Attempt to fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s). If this is possible, a new instruction is returned with the specified operand folded, otherwise NULL is returned. The new instruction is inserted before MI, and the client is responsible for removing the old instruction. If VRM is passed, the assigned physregs can be inspected by target to decide on using an opcode (note that those assignments can still change).
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1111
Parameters
- llvm::MachineInstr& MI
- ArrayRef<unsigned int> Ops
- int FI
- llvm::LiveIntervals* LIS = nullptr
- llvm::VirtRegMap* VRM = nullptr
¶llvm::MachineInstr* foldMemoryOperand(
llvm::MachineInstr& MI,
ArrayRef<unsigned int> Ops,
llvm::MachineInstr& LoadMI,
llvm::LiveIntervals* LIS = nullptr) const
llvm::MachineInstr* foldMemoryOperand(
llvm::MachineInstr& MI,
ArrayRef<unsigned int> Ops,
llvm::MachineInstr& LoadMI,
llvm::LiveIntervals* LIS = nullptr) const
Description
Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1118
Parameters
- llvm::MachineInstr& MI
- ArrayRef<unsigned int> Ops
- llvm::MachineInstr& LoadMI
- llvm::LiveIntervals* LIS = nullptr
¶virtual llvm::MachineInstr* foldMemoryOperandImpl(
llvm::MachineFunction& MF,
llvm::MachineInstr& MI,
ArrayRef<unsigned int> Ops,
MachineBasicBlock::iterator InsertPt,
int FrameIndex,
llvm::LiveIntervals* LIS = nullptr,
llvm::VirtRegMap* VRM = nullptr) const
virtual llvm::MachineInstr* foldMemoryOperandImpl(
llvm::MachineFunction& MF,
llvm::MachineInstr& MI,
ArrayRef<unsigned int> Ops,
MachineBasicBlock::iterator InsertPt,
int FrameIndex,
llvm::LiveIntervals* LIS = nullptr,
llvm::VirtRegMap* VRM = nullptr) const
Description
Target-dependent implementation for foldMemoryOperand. Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction. The instruction and any auxiliary instructions necessary will be inserted at InsertPt.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1218
Parameters
- llvm::MachineFunction& MF
- llvm::MachineInstr& MI
- ArrayRef<unsigned int> Ops
- MachineBasicBlock::iterator InsertPt
- int FrameIndex
- llvm::LiveIntervals* LIS = nullptr
- llvm::VirtRegMap* VRM = nullptr
¶virtual llvm::MachineInstr* foldMemoryOperandImpl(
llvm::MachineFunction& MF,
llvm::MachineInstr& MI,
ArrayRef<unsigned int> Ops,
MachineBasicBlock::iterator InsertPt,
llvm::MachineInstr& LoadMI,
llvm::LiveIntervals* LIS = nullptr) const
virtual llvm::MachineInstr* foldMemoryOperandImpl(
llvm::MachineFunction& MF,
llvm::MachineInstr& MI,
ArrayRef<unsigned int> Ops,
MachineBasicBlock::iterator InsertPt,
llvm::MachineInstr& LoadMI,
llvm::LiveIntervals* LIS = nullptr) const
Description
Target-dependent implementation for foldMemoryOperand. Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction. The instruction and any auxiliary instructions necessary will be inserted at InsertPt.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1231
Parameters
- llvm::MachineFunction& MF
- llvm::MachineInstr& MI
- ArrayRef<unsigned int> Ops
- MachineBasicBlock::iterator InsertPt
- llvm::MachineInstr& LoadMI
- llvm::LiveIntervals* LIS = nullptr
¶virtual void genAlternativeCodeSequence(
llvm::MachineInstr& Root,
llvm::MachineCombinerPattern Pattern,
SmallVectorImpl<llvm::MachineInstr*>&
InsInstrs,
SmallVectorImpl<llvm::MachineInstr*>&
DelInstrs,
DenseMap<unsigned int, unsigned int>&
InstIdxForVirtReg) const
virtual void genAlternativeCodeSequence(
llvm::MachineInstr& Root,
llvm::MachineCombinerPattern Pattern,
SmallVectorImpl<llvm::MachineInstr*>&
InsInstrs,
SmallVectorImpl<llvm::MachineInstr*>&
DelInstrs,
DenseMap<unsigned int, unsigned int>&
InstIdxForVirtReg) const
Description
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could replace the original code sequence. The client has to decide whether the actual replacement is beneficial or not.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1181
Parameters
- llvm::MachineInstr& Root
- - Instruction that could be combined with one of its operands
- llvm::MachineCombinerPattern Pattern
- - Combination pattern for Root
- SmallVectorImpl<llvm::MachineInstr*>& InsInstrs
- - Vector of new instructions that implement P
- SmallVectorImpl<llvm::MachineInstr*>& DelInstrs
- - Old instructions, including Root, that could be replaced by InsInstr
- DenseMap<unsigned int, unsigned int>& InstIdxForVirtReg
- - map of virtual register to instruction in InsInstr that defines it
¶virtual Optional<llvm::ExtAddrMode>
getAddrModeFromMemoryOp(
const llvm::MachineInstr& MemI,
const llvm::TargetRegisterInfo* TRI) const
virtual Optional<llvm::ExtAddrMode>
getAddrModeFromMemoryOp(
const llvm::MachineInstr& MemI,
const llvm::TargetRegisterInfo* TRI) const
Description
Target dependent implementation to get the values constituting the address MachineInstr that is accessing memory. These values are returned as a struct ExtAddrMode which contains all relevant information to make up the address.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1369
Parameters
- const llvm::MachineInstr& MemI
- const llvm::TargetRegisterInfo* TRI
¶virtual bool getBaseAndOffsetPosition(
const llvm::MachineInstr& MI,
unsigned int& BasePos,
unsigned int& OffsetPos) const
virtual bool getBaseAndOffsetPosition(
const llvm::MachineInstr& MI,
unsigned int& BasePos,
unsigned int& OffsetPos) const
Description
Return true if the instruction contains a base register and offset. If true, the function also sets the operand position in the instruction for the base register and offset.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1358
Parameters
- const llvm::MachineInstr& MI
- unsigned int& BasePos
- unsigned int& OffsetPos
¶virtual llvm::MachineBasicBlock*
getBranchDestBlock(
const llvm::MachineInstr& MI) const
virtual llvm::MachineBasicBlock*
getBranchDestBlock(
const llvm::MachineInstr& MI) const
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:591
Parameters
- const llvm::MachineInstr& MI
Returns
The block that branch instruction \p MI jumps to.
¶unsigned int getCallFrameDestroyOpcode() const
unsigned int getCallFrameDestroyOpcode() const
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:195
¶unsigned int getCallFrameSetupOpcode() const
unsigned int getCallFrameSetupOpcode() const
Description
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise). Some targets use pseudo instructions in order to abstract away the difference between operating with a frame pointer and operating without, through the use of these two instructions.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:194
¶virtual const llvm::MachineOperand&
getCalleeOperand(
const llvm::MachineInstr& MI) const
virtual const llvm::MachineOperand&
getCalleeOperand(
const llvm::MachineInstr& MI) const
Description
Returns the callee operand from the given \p MI.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1999
Parameters
- const llvm::MachineInstr& MI
¶unsigned int getCatchReturnOpcode() const
unsigned int getCatchReturnOpcode() const
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:234
¶virtual bool getConstValDefinedInReg(
const llvm::MachineInstr& MI,
const llvm::Register Reg,
int64_t& ImmVal) const
virtual bool getConstValDefinedInReg(
const llvm::MachineInstr& MI,
const llvm::Register Reg,
int64_t& ImmVal) const
Description
Returns true if MI is an instruction that defines Reg to have a constant value and the value is recorded in ImmVal. The ImmVal is a result that should be interpreted as modulo size of Reg.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1040
Parameters
- const llvm::MachineInstr& MI
- const llvm::Register Reg
- int64_t& ImmVal
¶virtual std::pair<uint16_t, uint16_t>
getExecutionDomain(
const llvm::MachineInstr& MI) const
virtual std::pair<uint16_t, uint16_t>
getExecutionDomain(
const llvm::MachineInstr& MI) const
Description
Return the current execution domain and bit mask of possible domains for instruction. Some micro-architectures have multiple execution domains, and multiple opcodes that perform the same operation in different domains. For example, the x86 architecture provides the por, orps, and orpd instructions that all do the same thing. There is a latency penalty if a register is written in one domain and read in another. This function returns a pair (domain, mask) containing the execution domain of MI, and a bit mask of possible domains. The setExecutionDomain function can be used to change the opcode to one of the domains in the bit mask. Instructions whose execution domain can't be changed should return a 0 mask. The execution domain numbers don't have any special meaning except domain 0 is used for instructions that are not associated with any interesting execution domain.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1681
Parameters
- const llvm::MachineInstr& MI
¶virtual int getExtendResourceLenLimit() const
virtual int getExtendResourceLenLimit() const
Description
The limit on resource length extension we accept in MachineCombiner Pass.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1196
¶bool getExtractSubregInputs(
const llvm::MachineInstr& MI,
unsigned int DefIdx,
llvm::TargetInstrInfo::RegSubRegPairAndIdx&
InputReg) const
bool getExtractSubregInputs(
const llvm::MachineInstr& MI,
unsigned int DefIdx,
llvm::TargetInstrInfo::RegSubRegPairAndIdx&
InputReg) const
Description
Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI and \p DefIdx. \p [out] InputReg of the equivalent EXTRACT_SUBREG. E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce: - %1:sub1, sub0
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:550
Parameters
- const llvm::MachineInstr& MI
- unsigned int DefIdx
- llvm::TargetInstrInfo::RegSubRegPairAndIdx& InputReg
Returns
true if it is possible to build such an input sequence with the pair \p MI, \p DefIdx and the operand has no undef flag set. False otherwise.
¶virtual bool getExtractSubregLikeInputs(
const llvm::MachineInstr& MI,
unsigned int DefIdx,
llvm::TargetInstrInfo::RegSubRegPairAndIdx&
InputReg) const
virtual bool getExtractSubregLikeInputs(
const llvm::MachineInstr& MI,
unsigned int DefIdx,
llvm::TargetInstrInfo::RegSubRegPairAndIdx&
InputReg) const
Description
Target-dependent implementation of getExtractSubregInputs.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1260
Parameters
- const llvm::MachineInstr& MI
- unsigned int DefIdx
- llvm::TargetInstrInfo::RegSubRegPairAndIdx& InputReg
Returns
true if it is possible to build the equivalent EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
¶int64_t getFrameSize(
const llvm::MachineInstr& I) const
int64_t getFrameSize(
const llvm::MachineInstr& I) const
Description
Returns size of the frame associated with the given frame instruction. For frame setup instruction this is frame that is set up space set up after the instruction. For frame destroy instruction this is the frame freed by the caller. Note, in some cases a call frame (or a part of it) may be prepared prior to the frame setup instruction. It occurs in the calls that involve inalloca arguments. This function reports only the size of the frame part that is set up between the frame setup and destroy pseudo instructions.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:216
Parameters
- const llvm::MachineInstr& I
¶int64_t getFrameTotalSize(
const llvm::MachineInstr& I) const
int64_t getFrameTotalSize(
const llvm::MachineInstr& I) const
Description
Returns the total frame size, which is made up of the space set up inside the pair of frame start-stop instructions and the space that is set up prior to the pair.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:225
Parameters
- const llvm::MachineInstr& I
¶virtual bool getIncrementValue(
const llvm::MachineInstr& MI,
int& Value) const
virtual bool getIncrementValue(
const llvm::MachineInstr& MI,
int& Value) const
Description
If the instruction is an increment of a constant value, return the amount.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1386
Parameters
- const llvm::MachineInstr& MI
- int& Value
¶virtual unsigned int getInlineAsmLength(
const char* Str,
const llvm::MCAsmInfo& MAI,
const llvm::TargetSubtargetInfo* STI =
nullptr) const
virtual unsigned int getInlineAsmLength(
const char* Str,
const llvm::MCAsmInfo& MAI,
const llvm::TargetSubtargetInfo* STI =
nullptr) const
Description
Measure the specified inline asm to determine an approximation of its length.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1506
Parameters
- const char* Str
- const llvm::MCAsmInfo& MAI
- const llvm::TargetSubtargetInfo* STI = nullptr
¶bool getInsertSubregInputs(
const llvm::MachineInstr& MI,
unsigned int DefIdx,
llvm::TargetInstrInfo::RegSubRegPair& BaseReg,
llvm::TargetInstrInfo::RegSubRegPairAndIdx&
InsertedReg) const
bool getInsertSubregInputs(
const llvm::MachineInstr& MI,
unsigned int DefIdx,
llvm::TargetInstrInfo::RegSubRegPair& BaseReg,
llvm::TargetInstrInfo::RegSubRegPairAndIdx&
InsertedReg) const
Description
Build the equivalent inputs of a INSERT_SUBREG for the given \p MI and \p DefIdx. \p [out] BaseReg and \p [out] InsertedReg contain the equivalent inputs of INSERT_SUBREG. E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce: - BaseReg: %0:sub0 - InsertedReg: %1:sub1, sub3
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:570
Parameters
- const llvm::MachineInstr& MI
- unsigned int DefIdx
- llvm::TargetInstrInfo::RegSubRegPair& BaseReg
- llvm::TargetInstrInfo::RegSubRegPairAndIdx& InsertedReg
Returns
true if it is possible to build such an input sequence with the pair \p MI, \p DefIdx and the operand has no undef flag set. False otherwise.
¶virtual bool getInsertSubregLikeInputs(
const llvm::MachineInstr& MI,
unsigned int DefIdx,
llvm::TargetInstrInfo::RegSubRegPair& BaseReg,
llvm::TargetInstrInfo::RegSubRegPairAndIdx&
InsertedReg) const
virtual bool getInsertSubregLikeInputs(
const llvm::MachineInstr& MI,
unsigned int DefIdx,
llvm::TargetInstrInfo::RegSubRegPair& BaseReg,
llvm::TargetInstrInfo::RegSubRegPairAndIdx&
InsertedReg) const
Description
Target-dependent implementation of getInsertSubregInputs.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1275
Parameters
- const llvm::MachineInstr& MI
- unsigned int DefIdx
- llvm::TargetInstrInfo::RegSubRegPair& BaseReg
- llvm::TargetInstrInfo::RegSubRegPairAndIdx& InsertedReg
Returns
true if it is possible to build the equivalent INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
¶virtual unsigned int getInstSizeInBytes(
const llvm::MachineInstr& MI) const
virtual unsigned int getInstSizeInBytes(
const llvm::MachineInstr& MI) const
Description
Returns the size in bytes of the specified MachineInstr, or ~0U when this function is not implemented by a target.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:362
Parameters
- const llvm::MachineInstr& MI
¶virtual int getInstrLatency(
const llvm::InstrItineraryData* ItinData,
llvm::SDNode* Node) const
virtual int getInstrLatency(
const llvm::InstrItineraryData* ItinData,
llvm::SDNode* Node) const
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1626
Parameters
- const llvm::InstrItineraryData* ItinData
- llvm::SDNode* Node
¶virtual unsigned int getInstrLatency(
const llvm::InstrItineraryData* ItinData,
const llvm::MachineInstr& MI,
unsigned int* PredCost = nullptr) const
virtual unsigned int getInstrLatency(
const llvm::InstrItineraryData* ItinData,
const llvm::MachineInstr& MI,
unsigned int* PredCost = nullptr) const
Description
Compute the instruction latency of a given instruction. If the instruction has higher cost when predicated, it's returned via PredCost.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1620
Parameters
- const llvm::InstrItineraryData* ItinData
- const llvm::MachineInstr& MI
- unsigned int* PredCost = nullptr
¶virtual const llvm::MIRFormatter*
getMIRFormatter() const
virtual const llvm::MIRFormatter*
getMIRFormatter() const
Description
Return MIR formatter to format/parse MIR operands. Target can override this virtual function and return target specific MIR formatter.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1985
¶virtual unsigned int getMachineCSELookAheadLimit()
const
virtual unsigned int getMachineCSELookAheadLimit()
const
Description
Return the value to use for the MachineCSE's LookAheadLimit, which is a heuristic used for CSE'ing phys reg defs.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1806
¶virtual bool getMachineCombinerPatterns(
llvm::MachineInstr& Root,
SmallVectorImpl<llvm::MachineCombinerPattern>&
Patterns,
bool DoRegPressureReduce) const
virtual bool getMachineCombinerPatterns(
llvm::MachineInstr& Root,
SmallVectorImpl<llvm::MachineCombinerPattern>&
Patterns,
bool DoRegPressureReduce) const
Description
Return true when there is potentially a faster code sequence for an instruction chain ending in \p Root. All potential patterns are returned in the \p Pattern vector. Pattern should be sorted in priority order since the pattern evaluator stops checking as soon as it finds a faster sequence.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1130
Parameters
- llvm::MachineInstr& Root
- - Instruction that could be combined with one of its operands
- SmallVectorImpl<llvm::MachineCombinerPattern>& Patterns
- - Vector of possible combination patterns
- bool DoRegPressureReduce
¶virtual unsigned int getMemOperandAACheckLimit()
const
virtual unsigned int getMemOperandAACheckLimit()
const
Description
Return the maximal number of alias checks on memory operands. For instructions with more than one memory operands, the alias check on a single MachineInstr pair has quadratic overhead and results in unacceptable performance in the worst case. The limit here is to clamp that maximal checks performed. Usually, that's the product of memory operand numbers from that pair of MachineInstr to be checked. For instance, with two MachineInstrs with 4 and 5 memory operands correspondingly, a total of 20 checks are required. With this limit set to 16, their alias check is skipped. We choose to limit the product instead of the individual instruction as targets may have special MachineInstrs with a considerably high number of memory operands, such as `ldm` in ARM. Setting this limit per MachineInstr would result in either too high overhead or too rigid restriction.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1825
¶bool getMemOperandWithOffset(
const llvm::MachineInstr& MI,
const llvm::MachineOperand*& BaseOp,
int64_t& Offset,
bool& OffsetIsScalable,
const llvm::TargetRegisterInfo* TRI) const
bool getMemOperandWithOffset(
const llvm::MachineInstr& MI,
const llvm::MachineOperand*& BaseOp,
int64_t& Offset,
bool& OffsetIsScalable,
const llvm::TargetRegisterInfo* TRI) const
Description
Get the base operand and byte offset of an instruction that reads/writes memory. This is a convenience function for callers that are only prepared to handle a single base operand.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1336
Parameters
- const llvm::MachineInstr& MI
- const llvm::MachineOperand*& BaseOp
- int64_t& Offset
- bool& OffsetIsScalable
- const llvm::TargetRegisterInfo* TRI
¶virtual bool getMemOperandsWithOffsetWidth(
const llvm::MachineInstr& MI,
SmallVectorImpl<const llvm::MachineOperand*>&
BaseOps,
int64_t& Offset,
bool& OffsetIsScalable,
unsigned int& Width,
const llvm::TargetRegisterInfo* TRI) const
virtual bool getMemOperandsWithOffsetWidth(
const llvm::MachineInstr& MI,
SmallVectorImpl<const llvm::MachineOperand*>&
BaseOps,
int64_t& Offset,
bool& OffsetIsScalable,
unsigned int& Width,
const llvm::TargetRegisterInfo* TRI) const
Description
Get zero or more base operands and the byte offset of an instruction that reads/writes memory. Note that there may be zero base operands if the instruction accesses a constant address. It returns false if MI does not read/write memory. It returns false if base operands and offset could not be determined. It is not guaranteed to always recognize base operands and offsets in all cases.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1348
Parameters
- const llvm::MachineInstr& MI
- SmallVectorImpl<const llvm::MachineOperand*>& BaseOps
- int64_t& Offset
- bool& OffsetIsScalable
- unsigned int& Width
- const llvm::TargetRegisterInfo* TRI
¶virtual llvm::MCInst getNop() const
virtual llvm::MCInst getNop() const
Description
Return the noop instruction to use for a noop.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1425
¶virtual unsigned int getNumMicroOps(
const llvm::InstrItineraryData* ItinData,
const llvm::MachineInstr& MI) const
virtual unsigned int getNumMicroOps(
const llvm::InstrItineraryData* ItinData,
const llvm::MachineInstr& MI) const
Description
Return the number of u-operations the given machine instruction will be decoded to on the target cpu. The itinerary's IssueWidth is the number of microops that can be dispatched each cycle. An instruction with zero microops takes no dispatch resources.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1589
Parameters
- const llvm::InstrItineraryData* ItinData
- const llvm::MachineInstr& MI
¶virtual unsigned int getOpcodeAfterMemoryUnfold(
unsigned int Opc,
bool UnfoldLoad,
bool UnfoldStore,
unsigned int* LoadRegIndex = nullptr) const
virtual unsigned int getOpcodeAfterMemoryUnfold(
unsigned int Opc,
bool UnfoldLoad,
bool UnfoldStore,
unsigned int* LoadRegIndex = nullptr) const
Description
Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode. It returns zero if the specified unfolding is not possible. If LoadRegIndex is non-null, it is filled in with the operand index of the operand which will hold the register holding the loaded value.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1304
Parameters
- unsigned int Opc
- bool UnfoldLoad
- bool UnfoldStore
- unsigned int* LoadRegIndex = nullptr
¶virtual int getOperandLatency(
const llvm::InstrItineraryData* ItinData,
const llvm::MachineInstr& DefMI,
unsigned int DefIdx,
const llvm::MachineInstr& UseMI,
unsigned int UseIdx) const
virtual int getOperandLatency(
const llvm::InstrItineraryData* ItinData,
const llvm::MachineInstr& DefMI,
unsigned int DefIdx,
const llvm::MachineInstr& UseMI,
unsigned int UseIdx) const
Description
Compute and return the use operand latency of a given pair of def and use. In most cases, the static scheduling itinerary was enough to determine the operand latency. But it may not be possible for instructions with variable number of defs / uses. This is a raw interface to the itinerary that may be directly overridden by a target. Use computeOperandLatency to get the best estimate of latency.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1612
Parameters
- const llvm::InstrItineraryData* ItinData
- const llvm::MachineInstr& DefMI
- unsigned int DefIdx
- const llvm::MachineInstr& UseMI
- unsigned int UseIdx
¶virtual int getOperandLatency(
const llvm::InstrItineraryData* ItinData,
llvm::SDNode* DefNode,
unsigned int DefIdx,
llvm::SDNode* UseNode,
unsigned int UseIdx) const
virtual int getOperandLatency(
const llvm::InstrItineraryData* ItinData,
llvm::SDNode* DefNode,
unsigned int DefIdx,
llvm::SDNode* UseNode,
unsigned int UseIdx) const
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1600
Parameters
- const llvm::InstrItineraryData* ItinData
- llvm::SDNode* DefNode
- unsigned int DefIdx
- llvm::SDNode* UseNode
- unsigned int UseIdx
¶virtual outliner::OutlinedFunction
getOutliningCandidateInfo(
std::vector<outliner::Candidate>&
RepeatedSequenceLocs) const
virtual outliner::OutlinedFunction
getOutliningCandidateInfo(
std::vector<outliner::Candidate>&
RepeatedSequenceLocs) const
Description
Returns a \p outliner::OutlinedFunction struct containing target-specific information for a set of outlining candidates.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1912
Parameters
- std::vector<outliner::Candidate>& RepeatedSequenceLocs
¶virtual outliner::InstrType getOutliningType(
MachineBasicBlock::iterator& MIT,
unsigned int Flags) const
virtual outliner::InstrType getOutliningType(
MachineBasicBlock::iterator& MIT,
unsigned int Flags) const
Description
Returns how or if \p MI should be outlined.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1926
Parameters
- MachineBasicBlock::iterator& MIT
- unsigned int Flags
¶virtual unsigned int getPartialRegUpdateClearance(
const llvm::MachineInstr& MI,
unsigned int OpNum,
const llvm::TargetRegisterInfo* TRI) const
virtual unsigned int getPartialRegUpdateClearance(
const llvm::MachineInstr& MI,
unsigned int OpNum,
const llvm::TargetRegisterInfo* TRI) const
Description
Returns the preferred minimum clearance before an instruction with an unwanted partial register update. Some instructions only write part of a register, and implicitly need to read the other parts of the register. This may cause unwanted stalls preventing otherwise unrelated instructions from executing in parallel in an out-of-order CPU. For example, the x86 instruction cvtsi2ss writes its result to bits [31:0] of the destination xmm register. Bits [127:32] are unaffected, so the instruction needs to wait for the old value of the register to become available: addps %xmm1, %xmm0 movaps %xmm0, (%rax) cvtsi2ss %rbx, %xmm0 In the code above, the cvtsi2ss instruction needs to wait for the addps instruction before it can issue, even though the high bits of %xmm0 probably aren't needed. This hook returns the preferred clearance before MI, measured in instructions. Other defs of MI's operand OpNum are avoided in the last N instructions before MI. It should only return a positive value for unwanted dependencies. If the old bits of the defined register have useful values, or if MI is determined to otherwise read the dependency, the hook should return 0. The unwanted dependency may be handled by: 1. Allocating the same register for an MI def and use. That makes the unwanted dependency identical to a required dependency. 2. Allocating a register for the def that has no defs in the previous N instructions. 3. Calling breakPartialRegDependency() with the same arguments. This allows the target to insert a dependency breaking instruction.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1731
Parameters
- const llvm::MachineInstr& MI
- unsigned int OpNum
- const llvm::TargetRegisterInfo* TRI
¶virtual std::pair<unsigned int, unsigned int>
getPatchpointUnfoldableRange(
const llvm::MachineInstr& MI) const
virtual std::pair<unsigned int, unsigned int>
getPatchpointUnfoldableRange(
const llvm::MachineInstr& MI) const
Description
For a patchpoint, stackmap, or statepoint intrinsic, return the range of operands which can't be folded into stack references. Operands outside of the range are most likely foldable but it is not guaranteed. These instructions are unique in that stack references for some operands have the same execution cost (e.g. none) as the unfolded register forms. The ranged return is guaranteed to include all operands which can't be folded at zero cost.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1101
Parameters
- const llvm::MachineInstr& MI
¶virtual unsigned int getPredicationCost(
const llvm::MachineInstr& MI) const
virtual unsigned int getPredicationCost(
const llvm::MachineInstr& MI) const
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1624
Parameters
- const llvm::MachineInstr& MI
¶virtual const llvm::TargetRegisterClass*
getRegClass(const llvm::MCInstrDesc& MCID,
unsigned int OpNum,
const llvm::TargetRegisterInfo* TRI,
const llvm::MachineFunction& MF) const
virtual const llvm::TargetRegisterClass*
getRegClass(const llvm::MCInstrDesc& MCID,
unsigned int OpNum,
const llvm::TargetRegisterInfo* TRI,
const llvm::MachineFunction& MF) const
Description
Given a machine instruction descriptor, returns the register class constraint for OpNum, or NULL.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:114
Parameters
- const llvm::MCInstrDesc& MCID
- unsigned int OpNum
- const llvm::TargetRegisterInfo* TRI
- const llvm::MachineFunction& MF
¶bool getRegSequenceInputs(
const llvm::MachineInstr& MI,
unsigned int DefIdx,
SmallVectorImpl<llvm::TargetInstrInfo::
RegSubRegPairAndIdx>&
InputRegs) const
bool getRegSequenceInputs(
const llvm::MachineInstr& MI,
unsigned int DefIdx,
SmallVectorImpl<llvm::TargetInstrInfo::
RegSubRegPairAndIdx>&
InputRegs) const
Description
Build the equivalent inputs of a REG_SEQUENCE for the given \p MI and \p DefIdx. \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of the list is modeled as <Reg :SubReg, SubIdx>. Operands with the undef flag are not added to this list. E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce two elements: - %1:sub1, sub0 - %2 < :0>, sub1
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:532
Parameters
- const llvm::MachineInstr& MI
- unsigned int DefIdx
- SmallVectorImpl< llvm::TargetInstrInfo::RegSubRegPairAndIdx>& InputRegs
Returns
true if it is possible to build such an input sequence with the pair \p MI, \p DefIdx. False otherwise.
¶virtual bool getRegSequenceLikeInputs(
const llvm::MachineInstr& MI,
unsigned int DefIdx,
SmallVectorImpl<llvm::TargetInstrInfo::
RegSubRegPairAndIdx>&
InputRegs) const
virtual bool getRegSequenceLikeInputs(
const llvm::MachineInstr& MI,
unsigned int DefIdx,
SmallVectorImpl<llvm::TargetInstrInfo::
RegSubRegPairAndIdx>&
InputRegs) const
Description
Target-dependent implementation of getRegSequenceInputs.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1246
Parameters
- const llvm::MachineInstr& MI
- unsigned int DefIdx
- SmallVectorImpl< llvm::TargetInstrInfo::RegSubRegPairAndIdx>& InputRegs
Returns
true if it is possible to build the equivalent REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
¶unsigned int getReturnOpcode() const
unsigned int getReturnOpcode() const
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:235
¶virtual int getSPAdjust(
const llvm::MachineInstr& MI) const
virtual int getSPAdjust(
const llvm::MachineInstr& MI) const
Description
Returns the actual stack pointer adjustment made by an instruction as part of a call sequence. By default, only call frame setup/destroy instructions adjust the stack, but targets may want to override this to enable more fine-grained adjustment, or adjust by a different value.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:241
Parameters
- const llvm::MachineInstr& MI
¶virtual ArrayRef<
std::pair<unsigned int, const char*>>
getSerializableBitmaskMachineOperandTargetFlags()
const
virtual ArrayRef<
std::pair<unsigned int, const char*>>
getSerializableBitmaskMachineOperandTargetFlags()
const
Description
Return an array that contains the bitmask target flag values and their names. MIR Serialization is able to serialize only the target flags that are defined by this method.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1860
¶virtual ArrayRef<
std::pair<unsigned int, const char*>>
getSerializableDirectMachineOperandTargetFlags()
const
virtual ArrayRef<
std::pair<unsigned int, const char*>>
getSerializableDirectMachineOperandTargetFlags()
const
Description
Return an array that contains the direct target flag values and their names. MIR Serialization is able to serialize only the target flags that are defined by this method.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1850
¶virtual ArrayRef<
std::pair<MachineMemOperand::Flags,
const char*>>
getSerializableMachineMemOperandTargetFlags()
const
virtual ArrayRef<
std::pair<MachineMemOperand::Flags,
const char*>>
getSerializableMachineMemOperandTargetFlags()
const
Description
Return an array that contains the MMO target flag values and their names. MIR Serialization is able to serialize only the MMO target flags that are defined by this method.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1870
¶virtual ArrayRef<std::pair<int, const char*>>
getSerializableTargetIndices() const
virtual ArrayRef<std::pair<int, const char*>>
getSerializableTargetIndices() const
Description
Return an array that contains the ids of the target indices (used for the TargetIndex machine operand) and their names. MIR Serialization is able to serialize only the target indices that are defined by this method.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1833
¶virtual bool getStackSlotRange(
const llvm::TargetRegisterClass* RC,
unsigned int SubIdx,
unsigned int& Size,
unsigned int& Offset,
const llvm::MachineFunction& MF) const
virtual bool getStackSlotRange(
const llvm::TargetRegisterClass* RC,
unsigned int SubIdx,
unsigned int& Size,
unsigned int& Offset,
const llvm::MachineFunction& MF) const
Description
Compute the size in bytes and offset within a stack slot of a spilled register or subregister. Not all subregisters have computable spill slots. For example, subregisters registers may not be byte-sized, and a pair of discontiguous subregisters has no single offset. Targets with nontrivial bigendian implementations may need to override this, particularly to support spilled vector registers.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:350
Parameters
- const llvm::TargetRegisterClass* RC
- unsigned int SubIdx
- unsigned int& Size
- in bytes of the spilled value.
- unsigned int& Offset
- in bytes within the stack slot.
- const llvm::MachineFunction& MF
Returns
true if both Size and Offset are successfully computed.
¶virtual unsigned int getTailDuplicateSize(
CodeGenOpt::Level OptLevel) const
virtual unsigned int getTailDuplicateSize(
CodeGenOpt::Level OptLevel) const
Description
Returns the target-specific default value for tail duplication. This value will be used if the tail-dup-placement-threshold argument is not provided.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1994
Parameters
- CodeGenOpt::Level OptLevel
¶virtual unsigned int getUndefRegClearance(
const llvm::MachineInstr& MI,
unsigned int OpNum,
const llvm::TargetRegisterInfo* TRI) const
virtual unsigned int getUndefRegClearance(
const llvm::MachineInstr& MI,
unsigned int OpNum,
const llvm::TargetRegisterInfo* TRI) const
Description
Return the minimum clearance before an instruction that reads an unused register. For example, AVX instructions may copy part of a register operand into the unused high bits of the destination register. vcvtsi2sdq %rax, undef %xmm0, %xmm14 In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a false dependence on any previous write to %xmm0. This hook works similarly to getPartialRegUpdateClearance, except that it does not take an operand index. Instead sets \p OpNum to the index of the unused register.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1751
Parameters
- const llvm::MachineInstr& MI
- unsigned int OpNum
- const llvm::TargetRegisterInfo* TRI
¶virtual bool hasCommutePreference(
llvm::MachineInstr& MI,
bool& Commute) const
virtual bool hasCommutePreference(
llvm::MachineInstr& MI,
bool& Commute) const
Description
Returns true if the target has a preference on the operands order of the given machine instruction. And specify if \p Commute is required to get the desired operands order.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:481
Parameters
- llvm::MachineInstr& MI
- bool& Commute
¶virtual bool hasHighOperandLatency(
const llvm::TargetSchedModel& SchedModel,
const llvm::MachineRegisterInfo* MRI,
const llvm::MachineInstr& DefMI,
unsigned int DefIdx,
const llvm::MachineInstr& UseMI,
unsigned int UseIdx) const
virtual bool hasHighOperandLatency(
const llvm::TargetSchedModel& SchedModel,
const llvm::MachineRegisterInfo* MRI,
const llvm::MachineInstr& DefMI,
unsigned int DefIdx,
const llvm::MachineInstr& UseMI,
unsigned int UseIdx) const
Description
Compute operand latency between a def of 'Reg' and a use in the current loop. Return true if the target considered it 'high'. This is used by optimization passes such as machine LICM to determine whether it makes sense to hoist an instruction out even in a high register pressure situation.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1641
Parameters
- const llvm::TargetSchedModel& SchedModel
- const llvm::MachineRegisterInfo* MRI
- const llvm::MachineInstr& DefMI
- unsigned int DefIdx
- const llvm::MachineInstr& UseMI
- unsigned int UseIdx
¶virtual bool hasLoadFromStackSlot(
const llvm::MachineInstr& MI,
SmallVectorImpl<
const llvm::MachineMemOperand*>& Accesses)
const
virtual bool hasLoadFromStackSlot(
const llvm::MachineInstr& MI,
SmallVectorImpl<
const llvm::MachineMemOperand*>& Accesses)
const
Description
If the specified machine instruction has a load from a stack slot, return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference. If not, return false. Unlike isLoadFromStackSlot, this returns true for any instructions that loads from the stack. This is just a hint, as some cases may be missed.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:287
Parameters
- const llvm::MachineInstr& MI
- SmallVectorImpl<const llvm::MachineMemOperand*>& Accesses
¶virtual bool hasLowDefLatency(
const llvm::TargetSchedModel& SchedModel,
const llvm::MachineInstr& DefMI,
unsigned int DefIdx) const
virtual bool hasLowDefLatency(
const llvm::TargetSchedModel& SchedModel,
const llvm::MachineInstr& DefMI,
unsigned int DefIdx) const
Description
Compute operand latency of a def of 'Reg'. Return true if the target considered it 'low'.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1651
Parameters
- const llvm::TargetSchedModel& SchedModel
- const llvm::MachineInstr& DefMI
- unsigned int DefIdx
¶virtual bool hasReassociableOperands(
const llvm::MachineInstr& Inst,
const llvm::MachineBasicBlock* MBB) const
virtual bool hasReassociableOperands(
const llvm::MachineInstr& Inst,
const llvm::MachineBasicBlock* MBB) const
Description
Return true when \PInst has reassociable operands in the same \PMBB.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1165
Parameters
- const llvm::MachineInstr& Inst
- const llvm::MachineBasicBlock* MBB
¶bool hasReassociableSibling(
const llvm::MachineInstr& Inst,
bool& Commuted) const
bool hasReassociableSibling(
const llvm::MachineInstr& Inst,
bool& Commuted) const
Description
Return true when \PInst has reassociable sibling.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1169
Parameters
- const llvm::MachineInstr& Inst
- bool& Commuted
¶virtual bool hasStoreToStackSlot(
const llvm::MachineInstr& MI,
SmallVectorImpl<
const llvm::MachineMemOperand*>& Accesses)
const
virtual bool hasStoreToStackSlot(
const llvm::MachineInstr& MI,
SmallVectorImpl<
const llvm::MachineMemOperand*>& Accesses)
const
Description
If the specified machine instruction has a store to a stack slot, return true along with the FrameIndices of the loaded stack slot and the machine mem operands containing the reference. If not, return false. Unlike isStoreToStackSlot, this returns true for any instructions that stores to the stack. This is just a hint, as some cases may be missed.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:325
Parameters
- const llvm::MachineInstr& MI
- SmallVectorImpl<const llvm::MachineMemOperand*>& Accesses
¶virtual unsigned int insertBranch(
llvm::MachineBasicBlock& MBB,
llvm::MachineBasicBlock* TBB,
llvm::MachineBasicBlock* FBB,
ArrayRef<llvm::MachineOperand> Cond,
const llvm::DebugLoc& DL,
int* BytesAdded = nullptr) const
virtual unsigned int insertBranch(
llvm::MachineBasicBlock& MBB,
llvm::MachineBasicBlock* TBB,
llvm::MachineBasicBlock* FBB,
ArrayRef<llvm::MachineOperand> Cond,
const llvm::DebugLoc& DL,
int* BytesAdded = nullptr) const
Description
Insert branch code into the end of the specified MachineBasicBlock. The operands to this method are the same as those returned by analyzeBranch. This is only invoked in cases where analyzeBranch returns success. It returns the number of instructions inserted. If \p BytesAdded is non-null, report the change in code size from the added instructions. It is also invoked by tail merging to add unconditional branches in cases where analyzeBranch doesn't apply because there was no original branch to analyze. At least this much must be implemented, else tail merging needs to be disabled. The CFG information in MBB.Predecessors and MBB.Successors must be valid before calling this function.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:705
Parameters
- llvm::MachineBasicBlock& MBB
- llvm::MachineBasicBlock* TBB
- llvm::MachineBasicBlock* FBB
- ArrayRef<llvm::MachineOperand> Cond
- const llvm::DebugLoc& DL
- int* BytesAdded = nullptr
¶virtual void insertIndirectBranch(
llvm::MachineBasicBlock& MBB,
llvm::MachineBasicBlock& NewDestBB,
llvm::MachineBasicBlock& RestoreBB,
const llvm::DebugLoc& DL,
int64_t BrOffset = 0,
llvm::RegScavenger* RS = nullptr) const
virtual void insertIndirectBranch(
llvm::MachineBasicBlock& MBB,
llvm::MachineBasicBlock& NewDestBB,
llvm::MachineBasicBlock& RestoreBB,
const llvm::DebugLoc& DL,
int64_t BrOffset = 0,
llvm::RegScavenger* RS = nullptr) const
Description
Insert an unconditional indirect branch at the end of \p MBB to \p NewDestBB. Optionally, insert the clobbered register restoring in \p RestoreBB. \p BrOffset indicates the offset of \p NewDestBB relative to the offset of the position to insert the new branch.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:599
Parameters
- llvm::MachineBasicBlock& MBB
- llvm::MachineBasicBlock& NewDestBB
- llvm::MachineBasicBlock& RestoreBB
- const llvm::DebugLoc& DL
- int64_t BrOffset = 0
- llvm::RegScavenger* RS = nullptr
¶virtual void insertNoop(
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator MI) const
virtual void insertNoop(
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator MI) const
Description
Insert a noop into the instruction stream at the specified point.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1416
Parameters
¶virtual void insertNoops(
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator MI,
unsigned int Quantity) const
virtual void insertNoops(
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator MI,
unsigned int Quantity) const
Description
Insert noops into the instruction stream at the specified point.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1420
Parameters
- llvm::MachineBasicBlock& MBB
- MachineBasicBlock::iterator MI
- unsigned int Quantity
¶virtual MachineBasicBlock::iterator
insertOutlinedCall(
llvm::Module& M,
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator& It,
llvm::MachineFunction& MF,
outliner::Candidate& C) const
virtual MachineBasicBlock::iterator
insertOutlinedCall(
llvm::Module& M,
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator& It,
llvm::MachineFunction& MF,
outliner::Candidate& C) const
Description
Insert a call to an outlined function into the program. Returns an iterator to the spot where we inserted the call. This must be implemented by the target.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1947
Parameters
- llvm::Module& M
- llvm::MachineBasicBlock& MBB
- MachineBasicBlock::iterator& It
- llvm::MachineFunction& MF
- outliner::Candidate& C
¶virtual void insertSelect(
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator I,
const llvm::DebugLoc& DL,
llvm::Register DstReg,
ArrayRef<llvm::MachineOperand> Cond,
llvm::Register TrueReg,
llvm::Register FalseReg) const
virtual void insertSelect(
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator I,
const llvm::DebugLoc& DL,
llvm::Register DstReg,
ArrayRef<llvm::MachineOperand> Cond,
llvm::Register TrueReg,
llvm::Register FalseReg) const
Description
Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when Cond is false. This function can only be called after canInsertSelect() returned true. The condition in Cond comes from analyzeBranch, and it can be assumed that the same flags or registers required by Cond are available at the insertion point.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:910
Parameters
- llvm::MachineBasicBlock& MBB
- Block where select instruction should be inserted.
- MachineBasicBlock::iterator I
- Insertion point.
- const llvm::DebugLoc& DL
- Source location for debugging.
- llvm::Register DstReg
- Virtual register to be defined by select instruction.
- ArrayRef<llvm::MachineOperand> Cond
- Condition as computed by analyzeBranch.
- llvm::Register TrueReg
- Virtual register to copy when Cond is true.
- llvm::Register FalseReg
- Virtual register to copy when Cons is false.
¶unsigned int insertUnconditionalBranch(
llvm::MachineBasicBlock& MBB,
llvm::MachineBasicBlock* DestBB,
const llvm::DebugLoc& DL,
int* BytesAdded = nullptr) const
unsigned int insertUnconditionalBranch(
llvm::MachineBasicBlock& MBB,
llvm::MachineBasicBlock* DestBB,
const llvm::DebugLoc& DL,
int* BytesAdded = nullptr) const
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:713
Parameters
- llvm::MachineBasicBlock& MBB
- llvm::MachineBasicBlock* DestBB
- const llvm::DebugLoc& DL
- int* BytesAdded = nullptr
¶virtual Optional<llvm::RegImmPair> isAddImmediate(
const llvm::MachineInstr& MI,
llvm::Register Reg) const
virtual Optional<llvm::RegImmPair> isAddImmediate(
const llvm::MachineInstr& MI,
llvm::Register Reg) const
Description
If the specific machine instruction is an instruction that adds an immediate value and a physical register, and stores the result in the given physical register \c Reg, return a pair of the source register and the offset which has been added.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1032
Parameters
- const llvm::MachineInstr& MI
- llvm::Register Reg
¶virtual bool isAsCheapAsAMove(
const llvm::MachineInstr& MI) const
virtual bool isAsCheapAsAMove(
const llvm::MachineInstr& MI) const
Description
Return true if the instruction is as cheap as a move instruction. Targets for different archs need to override this, and different micro-architectures can also be finely tuned inside.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:370
Parameters
- const llvm::MachineInstr& MI
¶virtual bool isAssociativeAndCommutative(
const llvm::MachineInstr& Inst) const
virtual bool isAssociativeAndCommutative(
const llvm::MachineInstr& Inst) const
Description
Return true when \PInst is both associative and commutative.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1160
Parameters
- const llvm::MachineInstr& Inst
¶virtual bool isBasicBlockPrologue(
const llvm::MachineInstr& MI) const
virtual bool isBasicBlockPrologue(
const llvm::MachineInstr& MI) const
Description
True if the instruction is bound to the top of its basic block and no other instructions shall be inserted before it. This can be implemented to prevent register allocator to insert spills before such instructions.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1884
Parameters
- const llvm::MachineInstr& MI
¶virtual bool isBranchOffsetInRange(
unsigned int BranchOpc,
int64_t BrOffset) const
virtual bool isBranchOffsetInRange(
unsigned int BranchOpc,
int64_t BrOffset) const
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:585
Parameters
- unsigned int BranchOpc
- int64_t BrOffset
Returns
true if a branch from an instruction with opcode \p BranchOpc bytes is capable of jumping to a position \p BrOffset bytes away.
¶virtual bool isCoalescableExtInstr(
const llvm::MachineInstr& MI,
llvm::Register& SrcReg,
llvm::Register& DstReg,
unsigned int& SubIdx) const
virtual bool isCoalescableExtInstr(
const llvm::MachineInstr& MI,
llvm::Register& SrcReg,
llvm::Register& DstReg,
unsigned int& SubIdx) const
Description
Return true if the instruction is a "coalescable" extension instruction. That is, it's like a copy where it's legal for the source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns true, then it's expected the pre-extension value is available as a subreg of the result register. This also returns the sub-register index in SubIdx.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:248
Parameters
- const llvm::MachineInstr& MI
- llvm::Register& SrcReg
- llvm::Register& DstReg
- unsigned int& SubIdx
¶Optional<llvm::DestSourcePair> isCopyInstr(
const llvm::MachineInstr& MI) const
Optional<llvm::DestSourcePair> isCopyInstr(
const llvm::MachineInstr& MI) const
Description
If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands. For COPY-instruction the method naturally returns destination and source registers as machine operands, for all other instructions the method calls target-dependent implementation.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1021
Parameters
- const llvm::MachineInstr& MI
¶virtual Optional<llvm::DestSourcePair>
isCopyInstrImpl(
const llvm::MachineInstr& MI) const
virtual Optional<llvm::DestSourcePair>
isCopyInstrImpl(
const llvm::MachineInstr& MI) const
Description
Target-dependent implementation for IsCopyInstr. If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:999
Parameters
- const llvm::MachineInstr& MI
¶virtual bool isExtendLikelyToBeFolded(
llvm::MachineInstr& ExtMI,
llvm::MachineRegisterInfo& MRI) const
virtual bool isExtendLikelyToBeFolded(
llvm::MachineInstr& ExtMI,
llvm::MachineRegisterInfo& MRI) const
Description
Given the generic extension instruction \p ExtMI, returns true if this extension is a likely candidate for being folded into an another instruction.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1978
Parameters
- llvm::MachineInstr& ExtMI
- llvm::MachineRegisterInfo& MRI
¶bool isFrameInstr(
const llvm::MachineInstr& I) const
bool isFrameInstr(
const llvm::MachineInstr& I) const
Description
Returns true if the argument is a frame pseudo instruction.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:198
Parameters
- const llvm::MachineInstr& I
¶bool isFrameSetup(
const llvm::MachineInstr& I) const
bool isFrameSetup(
const llvm::MachineInstr& I) const
Description
Returns true if the argument is a frame setup pseudo instruction.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:204
Parameters
- const llvm::MachineInstr& I
¶virtual bool isFunctionSafeToOutlineFrom(
llvm::MachineFunction& MF,
bool OutlineFromLinkOnceODRs) const
virtual bool isFunctionSafeToOutlineFrom(
llvm::MachineFunction& MF,
bool OutlineFromLinkOnceODRs) const
Description
Return true if the function can safely be outlined from. A function \p MF is considered safe for outlining if an outlined function produced from instructions in F will produce a program which produces the same output for any set of given inputs.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1958
Parameters
- llvm::MachineFunction& MF
- bool OutlineFromLinkOnceODRs
¶static bool isGenericOpcode(unsigned int Opc)
static bool isGenericOpcode(unsigned int Opc)
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:107
Parameters
- unsigned int Opc
¶virtual bool isHighLatencyDef(int opc) const
virtual bool isHighLatencyDef(int opc) const
Description
Return true if this opcode has high latency to its result.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1634
Parameters
- int opc
¶virtual bool isIgnorableUse(
const llvm::MachineOperand& MO) const
virtual bool isIgnorableUse(
const llvm::MachineOperand& MO) const
Description
Given \p MO is a PhysReg use return if it can be ignored for the purpose of instruction rematerialization or sinking.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:132
Parameters
- const llvm::MachineOperand& MO
¶virtual bool isLegalToSplitMBBAt(
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator MBBI) const
virtual bool isLegalToSplitMBBAt(
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator MBBI) const
Description
Return true if it's legal to split the given basic block at the specified instruction (i.e. instruction would be the start of a new basic block).
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:798
Parameters
¶virtual unsigned int isLoadFromStackSlot(
const llvm::MachineInstr& MI,
int& FrameIndex) const
virtual unsigned int isLoadFromStackSlot(
const llvm::MachineInstr& MI,
int& FrameIndex) const
Description
If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:258
Parameters
- const llvm::MachineInstr& MI
- int& FrameIndex
¶virtual unsigned int isLoadFromStackSlot(
const llvm::MachineInstr& MI,
int& FrameIndex,
unsigned int& MemBytes) const
virtual unsigned int isLoadFromStackSlot(
const llvm::MachineInstr& MI,
int& FrameIndex,
unsigned int& MemBytes) const
Description
Optional extension of isLoadFromStackSlot that returns the number of bytes loaded from the stack. This must be implemented if a backend supports partial stack slot spills/loads to further disambiguate what the load does.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:267
Parameters
- const llvm::MachineInstr& MI
- int& FrameIndex
- unsigned int& MemBytes
¶virtual unsigned int isLoadFromStackSlotPostFE(
const llvm::MachineInstr& MI,
int& FrameIndex) const
virtual unsigned int isLoadFromStackSlotPostFE(
const llvm::MachineInstr& MI,
int& FrameIndex) const
Description
Check for post-frame ptr elimination stack locations as well. This uses a heuristic so it isn't reliable for correctness.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:276
Parameters
- const llvm::MachineInstr& MI
- int& FrameIndex
¶virtual bool isMBBSafeToOutlineFrom(
llvm::MachineBasicBlock& MBB,
unsigned int& Flags) const
virtual bool isMBBSafeToOutlineFrom(
llvm::MachineBasicBlock& MBB,
unsigned int& Flags) const
Description
Optional target hook that returns true if \p MBB is safe to outline from, and returns any target-specific information in \p Flags.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1933
Parameters
- llvm::MachineBasicBlock& MBB
- unsigned int& Flags
¶virtual bool isPCRelRegisterOperandLegal(
const llvm::MachineOperand& MO) const
virtual bool isPCRelRegisterOperandLegal(
const llvm::MachineOperand& MO) const
Description
Allow targets to tell MachineVerifier whether a specific register MachineOperand can be used as part of PC-relative addressing. PC-relative addressing modes in many CISC architectures contain (non-PC) registers as offsets or scaling values, which inherently tags the corresponding MachineOperand with OPERAND_PCREL.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:989
Parameters
- const llvm::MachineOperand& MO
- The MachineOperand in question. MO.isReg() should always be true.
Returns
Whether this operand is allowed to be used PC-relatively.
¶virtual bool isPostIncrement(
const llvm::MachineInstr& MI) const
virtual bool isPostIncrement(
const llvm::MachineInstr& MI) const
Description
Return true for post-incremented instructions.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1428
Parameters
- const llvm::MachineInstr& MI
¶virtual bool isPredicable(
const llvm::MachineInstr& MI) const
virtual bool isPredicable(
const llvm::MachineInstr& MI) const
Description
Return true if the specified instruction can be predicated. By default, this returns true for every instruction with a PredicateOperand.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1488
Parameters
- const llvm::MachineInstr& MI
¶virtual bool isPredicated(
const llvm::MachineInstr& MI) const
virtual bool isPredicated(
const llvm::MachineInstr& MI) const
Description
Returns true if the instruction is already predicated.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1431
Parameters
- const llvm::MachineInstr& MI
¶virtual bool isProfitableToDupForIfCvt(
llvm::MachineBasicBlock& MBB,
unsigned int NumCycles,
llvm::BranchProbability Probability) const
virtual bool isProfitableToDupForIfCvt(
llvm::MachineBasicBlock& MBB,
unsigned int NumCycles,
llvm::BranchProbability Probability) const
Description
Return true if it's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion. The probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:834
Parameters
- llvm::MachineBasicBlock& MBB
- unsigned int NumCycles
- llvm::BranchProbability Probability
¶virtual bool isProfitableToIfCvt(
llvm::MachineBasicBlock& MBB,
unsigned int NumCycles,
unsigned int ExtraPredCycles,
llvm::BranchProbability Probability) const
virtual bool isProfitableToIfCvt(
llvm::MachineBasicBlock& MBB,
unsigned int NumCycles,
unsigned int ExtraPredCycles,
llvm::BranchProbability Probability) const
Description
Return true if it's profitable to predicate instructions with accumulated instruction latency of "NumCycles" of the specified basic block, where the probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:808
Parameters
- llvm::MachineBasicBlock& MBB
- unsigned int NumCycles
- unsigned int ExtraPredCycles
- llvm::BranchProbability Probability
¶virtual bool isProfitableToIfCvt(
llvm::MachineBasicBlock& TMBB,
unsigned int NumTCycles,
unsigned int ExtraTCycles,
llvm::MachineBasicBlock& FMBB,
unsigned int NumFCycles,
unsigned int ExtraFCycles,
llvm::BranchProbability Probability) const
virtual bool isProfitableToIfCvt(
llvm::MachineBasicBlock& TMBB,
unsigned int NumTCycles,
unsigned int ExtraTCycles,
llvm::MachineBasicBlock& FMBB,
unsigned int NumFCycles,
unsigned int ExtraFCycles,
llvm::BranchProbability Probability) const
Description
Second variant of isProfitableToIfCvt. This one checks for the case where two basic blocks from true and false path of a if-then-else (diamond) are predicated on mutually exclusive predicates, where the probability of the true path being taken is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:820
Parameters
- llvm::MachineBasicBlock& TMBB
- unsigned int NumTCycles
- unsigned int ExtraTCycles
- llvm::MachineBasicBlock& FMBB
- unsigned int NumFCycles
- unsigned int ExtraFCycles
- llvm::BranchProbability Probability
¶virtual bool isProfitableToUnpredicate(
llvm::MachineBasicBlock& TMBB,
llvm::MachineBasicBlock& FMBB) const
virtual bool isProfitableToUnpredicate(
llvm::MachineBasicBlock& TMBB,
llvm::MachineBasicBlock& FMBB) const
Description
Return true if it's profitable to unpredicate one side of a 'diamond', i.e. two sides of if-else predicated on mutually exclusive predicates. e.g. subeq r0, r1, #1 addne r0, r1, #1 => sub r0, r1, #1 addne r0, r1, #1 This may be profitable is conditional instructions are always executed.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:864
Parameters
- llvm::MachineBasicBlock& TMBB
- llvm::MachineBasicBlock& FMBB
¶virtual bool isReallyTriviallyReMaterializable(
const llvm::MachineInstr& MI) const
virtual bool isReallyTriviallyReMaterializable(
const llvm::MachineInstr& MI) const
Description
For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target specify whether the instruction is actually trivially rematerializable, taking into consideration its operands. This predicate must return false if the instruction has any side effects other than producing a value, or if it requres any address registers that are not always available. Requirements must be check as stated in isTriviallyReMaterializable() .
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:144
Parameters
- const llvm::MachineInstr& MI
¶bool isReallyTriviallyReMaterializableGeneric(
const llvm::MachineInstr& MI) const
bool isReallyTriviallyReMaterializableGeneric(
const llvm::MachineInstr& MI) const
Description
For instructions with opcodes for which the M_REMATERIALIZABLE flag is set and the target hook isReallyTriviallyReMaterializable returns false, this function does target-independent tests to determine if the instruction is really trivially rematerializable.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:186
Parameters
- const llvm::MachineInstr& MI
¶bool isReassociationCandidate(
const llvm::MachineInstr& Inst,
bool& Commuted) const
bool isReassociationCandidate(
const llvm::MachineInstr& Inst,
bool& Commuted) const
Description
Return true if the input \PInst is part of a chain of dependent ops that are suitable for reassociation, otherwise return false. If the instruction's operands must be commuted to have a previous instruction of the same type define the first source operand, \PCommuted will be set to true.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1157
Parameters
- const llvm::MachineInstr& Inst
- bool& Commuted
¶virtual bool isSafeToMoveRegClassDefs(
const llvm::TargetRegisterClass* RC) const
virtual bool isSafeToMoveRegClassDefs(
const llvm::TargetRegisterClass* RC) const
Description
Return true if it's safe to move a machine instruction that defines the specified register class.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1494
Parameters
- const llvm::TargetRegisterClass* RC
¶virtual bool isSchedulingBoundary(
const llvm::MachineInstr& MI,
const llvm::MachineBasicBlock* MBB,
const llvm::MachineFunction& MF) const
virtual bool isSchedulingBoundary(
const llvm::MachineInstr& MI,
const llvm::MachineBasicBlock* MBB,
const llvm::MachineFunction& MF) const
Description
Test if the given instruction should be considered a scheduling boundary. This primarily includes labels and terminators.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1500
Parameters
- const llvm::MachineInstr& MI
- const llvm::MachineBasicBlock* MBB
- const llvm::MachineFunction& MF
¶virtual bool isStackSlotCopy(
const llvm::MachineInstr& MI,
int& DestFrameIndex,
int& SrcFrameIndex) const
virtual bool isStackSlotCopy(
const llvm::MachineInstr& MI,
int& DestFrameIndex,
int& SrcFrameIndex) const
Description
Return true if the specified machine instruction is a copy of one stack slot to another and has no other effect. Provide the identity of the two frame indices.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:332
Parameters
- const llvm::MachineInstr& MI
- int& DestFrameIndex
- int& SrcFrameIndex
¶virtual unsigned int isStoreToStackSlot(
const llvm::MachineInstr& MI,
int& FrameIndex) const
virtual unsigned int isStoreToStackSlot(
const llvm::MachineInstr& MI,
int& FrameIndex) const
Description
If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:296
Parameters
- const llvm::MachineInstr& MI
- int& FrameIndex
¶virtual unsigned int isStoreToStackSlot(
const llvm::MachineInstr& MI,
int& FrameIndex,
unsigned int& MemBytes) const
virtual unsigned int isStoreToStackSlot(
const llvm::MachineInstr& MI,
int& FrameIndex,
unsigned int& MemBytes) const
Description
Optional extension of isStoreToStackSlot that returns the number of bytes stored to the stack. This must be implemented if a backend supports partial stack slot spills/loads to further disambiguate what the store does.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:305
Parameters
- const llvm::MachineInstr& MI
- int& FrameIndex
- unsigned int& MemBytes
¶virtual unsigned int isStoreToStackSlotPostFE(
const llvm::MachineInstr& MI,
int& FrameIndex) const
virtual unsigned int isStoreToStackSlotPostFE(
const llvm::MachineInstr& MI,
int& FrameIndex) const
Description
Check for post-frame ptr elimination stack locations as well. This uses a heuristic, so it isn't reliable for correctness.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:314
Parameters
- const llvm::MachineInstr& MI
- int& FrameIndex
¶virtual bool isSubregFoldable() const
virtual bool isSubregFoldable() const
Description
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds a store). For example, X86 may want to return true if it can fold movl (%esp), %eax subb, %al, ... Into: subb (%esp), ... Ideally, we'd like the target implementation of foldMemoryOperand() to reject subregs - but since this behavior used to be enforced in the target-independent code, moving this responsibility to the targets has the potential of causing nasty silent breakage in out-of-tree targets.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1091
¶virtual bool isTailCall(
const llvm::MachineInstr& Inst) const
virtual bool isTailCall(
const llvm::MachineInstr& Inst) const
Description
Determines whether \p Inst is a tail call instruction. Override this method on targets that do not properly set MCID::Return and MCID::Call on tail call instructions."
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1877
Parameters
- const llvm::MachineInstr& Inst
¶virtual bool isThroughputPattern(
llvm::MachineCombinerPattern Pattern) const
virtual bool isThroughputPattern(
llvm::MachineCombinerPattern Pattern) const
Description
Return true when a code sequence can improve throughput. It should be called only for instructions in loops.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1150
Parameters
- llvm::MachineCombinerPattern Pattern
- - combiner pattern
¶bool isTriviallyReMaterializable(
const llvm::MachineInstr& MI) const
bool isTriviallyReMaterializable(
const llvm::MachineInstr& MI) const
Description
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requires no operands that aren't always available. This means the only allowed uses are constants and unallocatable physical registers so that the instructions result is independent of the place in the function.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:123
Parameters
- const llvm::MachineInstr& MI
¶virtual bool isUnconditionalTailCall(
const llvm::MachineInstr& MI) const
virtual bool isUnconditionalTailCall(
const llvm::MachineInstr& MI) const
Description
Returns true if MI is an unconditional tail call.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1443
Parameters
- const llvm::MachineInstr& MI
¶bool isUnpredicatedTerminator(
const llvm::MachineInstr& MI) const
bool isUnpredicatedTerminator(
const llvm::MachineInstr& MI) const
Description
Returns true if the instruction is a terminator instruction that has not been predicated.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1440
Parameters
- const llvm::MachineInstr& MI
¶bool isUnspillableTerminator(
const llvm::MachineInstr* MI) const
bool isUnspillableTerminator(
const llvm::MachineInstr* MI) const
Description
Return true if the given instruction is terminator that is unspillable, according to isUnspillableTerminatorImpl.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:356
Parameters
- const llvm::MachineInstr* MI
¶virtual bool isUnspillableTerminatorImpl(
const llvm::MachineInstr* MI) const
virtual bool isUnspillableTerminatorImpl(
const llvm::MachineInstr* MI) const
Description
Return true if the given terminator MI is not expected to spill. This sets the live interval as not spillable and adjusts phi node lowering to not introduce copies after the terminator. Use with care, these are currently used for hardware loop intrinsics in very controlled situations, created prior to registry allocation in loops that only have single phi users for the terminators value. They may run out of registers if not used carefully.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1010
Parameters
- const llvm::MachineInstr* MI
¶bool isZeroCost(unsigned int Opcode) const
bool isZeroCost(unsigned int Opcode) const
Description
Return true for pseudo instructions that don't consume any machine resources in their current form. These are common cases that the scheduler should consider free, rather than conservatively handling them as instructions with no itinerary.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1596
Parameters
- unsigned int Opcode
¶virtual void loadRegFromStackSlot(
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator MI,
llvm::Register DestReg,
int FrameIndex,
const llvm::TargetRegisterClass* RC,
const llvm::TargetRegisterInfo* TRI) const
virtual void loadRegFromStackSlot(
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator MI,
llvm::Register DestReg,
int FrameIndex,
const llvm::TargetRegisterClass* RC,
const llvm::TargetRegisterInfo* TRI) const
Description
Load the specified register of the given register class from the specified stack frame index. The load instruction is to be added to the given machine basic block before the specified machine instruction.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1062
Parameters
- llvm::MachineBasicBlock& MBB
- MachineBasicBlock::iterator MI
- llvm::Register DestReg
- int FrameIndex
- const llvm::TargetRegisterClass* RC
- const llvm::TargetRegisterInfo* TRI
¶virtual void mergeOutliningCandidateAttributes(
llvm::Function& F,
std::vector<outliner::Candidate>& Candidates)
const
virtual void mergeOutliningCandidateAttributes(
llvm::Function& F,
std::vector<outliner::Candidate>& Candidates)
const
Description
Optional target hook to create the LLVM IR attributes for the outlined function. If overridden, the overriding function must call the default implementation.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1921
Parameters
- llvm::Function& F
- std::vector<outliner::Candidate>& Candidates
¶virtual bool optimizeCompareInstr(
llvm::MachineInstr& CmpInstr,
llvm::Register SrcReg,
llvm::Register SrcReg2,
int64_t Mask,
int64_t Value,
const llvm::MachineRegisterInfo* MRI) const
virtual bool optimizeCompareInstr(
llvm::MachineInstr& CmpInstr,
llvm::Register SrcReg,
llvm::Register SrcReg2,
int64_t Mask,
int64_t Value,
const llvm::MachineRegisterInfo* MRI) const
Description
See if the comparison instruction can be converted into something more efficient. E.g., on ARM most instructions can set the flags register, obviating the need for a separate CMP.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1552
Parameters
- llvm::MachineInstr& CmpInstr
- llvm::Register SrcReg
- llvm::Register SrcReg2
- int64_t Mask
- int64_t Value
- const llvm::MachineRegisterInfo* MRI
¶virtual bool optimizeCondBranch(
llvm::MachineInstr& MI) const
virtual bool optimizeCondBranch(
llvm::MachineInstr& MI) const
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1558
Parameters
¶virtual llvm::MachineInstr* optimizeLoadInstr(
llvm::MachineInstr& MI,
const llvm::MachineRegisterInfo* MRI,
llvm::Register& FoldAsLoadDefReg,
llvm::MachineInstr*& DefMI) const
virtual llvm::MachineInstr* optimizeLoadInstr(
llvm::MachineInstr& MI,
const llvm::MachineRegisterInfo* MRI,
llvm::Register& FoldAsLoadDefReg,
llvm::MachineInstr*& DefMI) const
Description
Try to remove the load by folding it to a register operand at the use. We fold the load instructions if and only if the def and use are in the same BB. We only look at one load and see whether it can be folded into MI. FoldAsLoadDefReg is the virtual register defined by the load we are trying to fold. DefMI returns the machine instruction that defines FoldAsLoadDefReg, and the function returns the machine instruction generated due to folding.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1567
Parameters
- llvm::MachineInstr& MI
- const llvm::MachineRegisterInfo* MRI
- llvm::Register& FoldAsLoadDefReg
- llvm::MachineInstr*& DefMI
¶virtual llvm::MachineInstr* optimizeSelect(
llvm::MachineInstr& MI,
SmallPtrSetImpl<llvm::MachineInstr*>& NewMIs,
bool PreferFalse = false) const
virtual llvm::MachineInstr* optimizeSelect(
llvm::MachineInstr& MI,
SmallPtrSetImpl<llvm::MachineInstr*>& NewMIs,
bool PreferFalse = false) const
Description
Given a select instruction that was understood by analyzeSelect and returned Optimizable = true, attempt to optimize MI by merging it with one of its operands. Returns NULL on failure. When successful, returns the new select instruction. The client is responsible for deleting MI. If both sides of the select can be optimized, PreferFalse is used to pick a side.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:958
Parameters
- llvm::MachineInstr& MI
- Optimizable select instruction.
- SmallPtrSetImpl<llvm::MachineInstr*>& NewMIs
- Set that record all MIs in the basic block up to \p MI. Has to be updated with any newly created MI or deleted ones.
- bool PreferFalse = false
- Try to optimize FalseOp instead of TrueOp.
Returns
Optimized instruction or NULL.
¶virtual unsigned int predictBranchSizeForIfCvt(
llvm::MachineInstr& MI) const
virtual unsigned int predictBranchSizeForIfCvt(
llvm::MachineInstr& MI) const
Description
Return an estimate for the code size reduction (in bytes) which will be caused by removing the given branch instruction during if-conversion.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:849
Parameters
¶virtual bool preservesZeroValueInReg(
const llvm::MachineInstr* MI,
const llvm::Register NullValueReg,
const llvm::TargetRegisterInfo* TRI) const
virtual bool preservesZeroValueInReg(
const llvm::MachineInstr* MI,
const llvm::Register NullValueReg,
const llvm::TargetRegisterInfo* TRI) const
Description
Returns true if MI's Def is NullValueReg, and the MI does not change the Zero value. i.e. cases such as rax = shr rax, X where NullValueReg = rax. Note that if the NullValueReg is non-zero, this function can return true even if becomes zero. Specifically cases such as NullValueReg = shl NullValueReg, 63.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1379
Parameters
- const llvm::MachineInstr* MI
- const llvm::Register NullValueReg
- const llvm::TargetRegisterInfo* TRI
¶virtual bool produceSameValue(
const llvm::MachineInstr& MI0,
const llvm::MachineInstr& MI1,
const llvm::MachineRegisterInfo* MRI =
nullptr) const
virtual bool produceSameValue(
const llvm::MachineInstr& MI0,
const llvm::MachineInstr& MI1,
const llvm::MachineRegisterInfo* MRI =
nullptr) const
Description
Return true if two machine instructions would produce identical values. By default, this is only true when the two instructions are deemed identical except for defs. If this function is called when the IR is still in SSA form, the caller can pass the MachineRegisterInfo for aggressive checks.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:579
Parameters
- const llvm::MachineInstr& MI0
- const llvm::MachineInstr& MI1
- const llvm::MachineRegisterInfo* MRI = nullptr
¶virtual void reMaterialize(
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator MI,
llvm::Register DestReg,
unsigned int SubIdx,
const llvm::MachineInstr& Orig,
const llvm::TargetRegisterInfo& TRI) const
virtual void reMaterialize(
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator MI,
llvm::Register DestReg,
unsigned int SubIdx,
const llvm::MachineInstr& Orig,
const llvm::TargetRegisterInfo& TRI) const
Description
Re-issue the specified 'original' instruction at the specific location targeting a new destination register. The register in Orig->getOperand(0).getReg() will be substituted by DestReg:SubIdx. Any existing subreg index is preserved or composed with SubIdx.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:397
Parameters
- llvm::MachineBasicBlock& MBB
- MachineBasicBlock::iterator MI
- llvm::Register DestReg
- unsigned int SubIdx
- const llvm::MachineInstr& Orig
- const llvm::TargetRegisterInfo& TRI
¶void reassociateOps(
llvm::MachineInstr& Root,
llvm::MachineInstr& Prev,
llvm::MachineCombinerPattern Pattern,
SmallVectorImpl<llvm::MachineInstr*>&
InsInstrs,
SmallVectorImpl<llvm::MachineInstr*>&
DelInstrs,
DenseMap<unsigned int, unsigned int>&
InstrIdxForVirtReg) const
void reassociateOps(
llvm::MachineInstr& Root,
llvm::MachineInstr& Prev,
llvm::MachineCombinerPattern Pattern,
SmallVectorImpl<llvm::MachineInstr*>&
InsInstrs,
SmallVectorImpl<llvm::MachineInstr*>&
DelInstrs,
DenseMap<unsigned int, unsigned int>&
InstrIdxForVirtReg) const
Description
Attempt to reassociate \PRoot and \PPrev according to \PPattern to reduce critical path length.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1189
Parameters
- llvm::MachineInstr& Root
- llvm::MachineInstr& Prev
- llvm::MachineCombinerPattern Pattern
- SmallVectorImpl<llvm::MachineInstr*>& InsInstrs
- SmallVectorImpl<llvm::MachineInstr*>& DelInstrs
- DenseMap<unsigned int, unsigned int>& InstrIdxForVirtReg
¶virtual unsigned int reduceLoopCount(
llvm::MachineBasicBlock& MBB,
llvm::MachineBasicBlock& PreHeader,
llvm::MachineInstr* IndVar,
llvm::MachineInstr& Cmp,
SmallVectorImpl<llvm::MachineOperand>& Cond,
SmallVectorImpl<llvm::MachineInstr*>&
PrevInsts,
unsigned int Iter,
unsigned int MaxIter) const
virtual unsigned int reduceLoopCount(
llvm::MachineBasicBlock& MBB,
llvm::MachineBasicBlock& PreHeader,
llvm::MachineInstr* IndVar,
llvm::MachineInstr& Cmp,
SmallVectorImpl<llvm::MachineOperand>& Cond,
SmallVectorImpl<llvm::MachineInstr*>&
PrevInsts,
unsigned int Iter,
unsigned int MaxIter) const
Description
Generate code to reduce the loop iteration by one and check if the loop is finished. Return the value/register of the new loop count. We need this function when peeling off one or more iterations of a loop. This function assumes the nth iteration is peeled first.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:781
Parameters
- llvm::MachineBasicBlock& MBB
- llvm::MachineBasicBlock& PreHeader
- llvm::MachineInstr* IndVar
- llvm::MachineInstr& Cmp
- SmallVectorImpl<llvm::MachineOperand>& Cond
- SmallVectorImpl<llvm::MachineInstr*>& PrevInsts
- unsigned int Iter
- unsigned int MaxIter
¶virtual unsigned int removeBranch(
llvm::MachineBasicBlock& MBB,
int* BytesRemoved = nullptr) const
virtual unsigned int removeBranch(
llvm::MachineBasicBlock& MBB,
int* BytesRemoved = nullptr) const
Description
Remove the branching code at the end of the specific MBB. This is only invoked in cases where analyzeBranch returns success. It returns the number of instructions that were removed. If \p BytesRemoved is non-null, report the change in code size from the removed instructions.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:687
Parameters
- llvm::MachineBasicBlock& MBB
- int* BytesRemoved = nullptr
¶virtual void replaceBranchWithTailCall(
llvm::MachineBasicBlock& MBB,
SmallVectorImpl<llvm::MachineOperand>& Cond,
const llvm::MachineInstr& TailCall) const
virtual void replaceBranchWithTailCall(
llvm::MachineBasicBlock& MBB,
SmallVectorImpl<llvm::MachineOperand>& Cond,
const llvm::MachineInstr& TailCall) const
Description
Replace the conditional branch in MBB with a conditional tail call.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1454
Parameters
- llvm::MachineBasicBlock& MBB
- SmallVectorImpl<llvm::MachineOperand>& Cond
- const llvm::MachineInstr& TailCall
¶virtual bool reverseBranchCondition(
SmallVectorImpl<llvm::MachineOperand>& Cond)
const
virtual bool reverseBranchCondition(
SmallVectorImpl<llvm::MachineOperand>& Cond)
const
Description
Reverses the branch condition of the specified condition list, returning false on success and true if it cannot be reversed.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1411
Parameters
- SmallVectorImpl<llvm::MachineOperand>& Cond
¶virtual void setExecutionDomain(
llvm::MachineInstr& MI,
unsigned int Domain) const
virtual void setExecutionDomain(
llvm::MachineInstr& MI,
unsigned int Domain) const
Description
Change the opcode of MI to execute in Domain. The bit (1 < < Domain) must be set in the mask returned from getExecutionDomain(MI).
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1689
Parameters
- llvm::MachineInstr& MI
- unsigned int Domain
¶virtual void setSpecialOperandAttr(
llvm::MachineInstr& OldMI1,
llvm::MachineInstr& OldMI2,
llvm::MachineInstr& NewMI1,
llvm::MachineInstr& NewMI2) const
virtual void setSpecialOperandAttr(
llvm::MachineInstr& OldMI1,
llvm::MachineInstr& OldMI2,
llvm::MachineInstr& NewMI1,
llvm::MachineInstr& NewMI2) const
Description
This is an architecture-specific helper function of reassociateOps. Set special operand attributes for new instructions after reassociation.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1200
Parameters
- llvm::MachineInstr& OldMI1
- llvm::MachineInstr& OldMI2
- llvm::MachineInstr& NewMI1
- llvm::MachineInstr& NewMI2
¶virtual bool shouldClusterMemOps(
ArrayRef<const llvm::MachineOperand*>
BaseOps1,
ArrayRef<const llvm::MachineOperand*>
BaseOps2,
unsigned int NumLoads,
unsigned int NumBytes) const
virtual bool shouldClusterMemOps(
ArrayRef<const llvm::MachineOperand*>
BaseOps1,
ArrayRef<const llvm::MachineOperand*>
BaseOps2,
unsigned int NumLoads,
unsigned int NumBytes) const
Description
Returns true if the two given memory operations should be scheduled adjacent. Note that you have to add: DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI)); or DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI)); to TargetPassConfig::createMachineScheduler() to have an effect. \p BaseOps1 and \p BaseOps2 are memory operands of two memory operations.\p NumLoads is the number of loads that will be in the cluster if this hook returns true.\p NumBytes is the number of bytes that will be loaded from all the clustered loads if this hook returns true.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1402
Parameters
- ArrayRef<const llvm::MachineOperand*> BaseOps1
- ArrayRef<const llvm::MachineOperand*> BaseOps2
- unsigned int NumLoads
- unsigned int NumBytes
¶virtual bool shouldHoist(
const llvm::MachineInstr& MI,
const llvm::MachineLoop* FromLoop) const
virtual bool shouldHoist(
const llvm::MachineInstr& MI,
const llvm::MachineLoop* FromLoop) const
Description
Return false if the instruction should not be hoisted by MachineLICM. MachineLICM determines on its own whether the instruction is safe to hoist; this gives the target a hook to extend this assessment and prevent an instruction being hoisted from a given loop for target specific reasons.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:387
Parameters
- const llvm::MachineInstr& MI
- const llvm::MachineLoop* FromLoop
¶virtual bool shouldOutlineFromFunctionByDefault(
llvm::MachineFunction& MF) const
virtual bool shouldOutlineFromFunctionByDefault(
llvm::MachineFunction& MF) const
Description
Return true if the function should be outlined from by default.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1965
Parameters
¶virtual bool shouldReduceRegisterPressure(
llvm::MachineBasicBlock* MBB,
llvm::RegisterClassInfo* RegClassInfo) const
virtual bool shouldReduceRegisterPressure(
llvm::MachineBasicBlock* MBB,
llvm::RegisterClassInfo* RegClassInfo) const
Description
Return true if target supports reassociation of instructions in machine combiner pass to reduce register pressure for a given BB.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1137
Parameters
- llvm::MachineBasicBlock* MBB
- llvm::RegisterClassInfo* RegClassInfo
¶virtual bool shouldScheduleLoadsNear(
llvm::SDNode* Load1,
llvm::SDNode* Load2,
int64_t Offset1,
int64_t Offset2,
unsigned int NumLoads) const
virtual bool shouldScheduleLoadsNear(
llvm::SDNode* Load1,
llvm::SDNode* Load2,
int64_t Offset1,
int64_t Offset2,
unsigned int NumLoads) const
Description
This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled together. On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1327
Parameters
- llvm::SDNode* Load1
- llvm::SDNode* Load2
- int64_t Offset1
- int64_t Offset2
- unsigned int NumLoads
¶virtual bool shouldSink(
const llvm::MachineInstr& MI) const
virtual bool shouldSink(
const llvm::MachineInstr& MI) const
Description
Return true if the instruction should be sunk by MachineSink. MachineSink determines on its own whether the instruction is safe to sink; this gives the target a hook to override the default behavior with regards to which instructions should be sunk.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:379
Parameters
- const llvm::MachineInstr& MI
¶virtual void storeRegToStackSlot(
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator MI,
llvm::Register SrcReg,
bool isKill,
int FrameIndex,
const llvm::TargetRegisterClass* RC,
const llvm::TargetRegisterInfo* TRI) const
virtual void storeRegToStackSlot(
llvm::MachineBasicBlock& MBB,
MachineBasicBlock::iterator MI,
llvm::Register SrcReg,
bool isKill,
int FrameIndex,
const llvm::TargetRegisterClass* RC,
const llvm::TargetRegisterInfo* TRI) const
Description
Store the specified register of the given register class to the specified stack frame index. The store instruction is to be added to the given machine basic block before the specified machine instruction. If isKill is true, the register operand is the last use and must be marked kill.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1050
Parameters
- llvm::MachineBasicBlock& MBB
- MachineBasicBlock::iterator MI
- llvm::Register SrcReg
- bool isKill
- int FrameIndex
- const llvm::TargetRegisterClass* RC
- const llvm::TargetRegisterInfo* TRI
¶virtual bool unfoldMemoryOperand(
llvm::SelectionDAG& DAG,
llvm::SDNode* N,
SmallVectorImpl<llvm::SDNode*>& NewNodes)
const
virtual bool unfoldMemoryOperand(
llvm::SelectionDAG& DAG,
llvm::SDNode* N,
SmallVectorImpl<llvm::SDNode*>& NewNodes)
const
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1292
Parameters
- llvm::SelectionDAG& DAG
- llvm::SDNode* N
- SmallVectorImpl<llvm::SDNode*>& NewNodes
¶virtual bool unfoldMemoryOperand(
llvm::MachineFunction& MF,
llvm::MachineInstr& MI,
unsigned int Reg,
bool UnfoldLoad,
bool UnfoldStore,
SmallVectorImpl<llvm::MachineInstr*>& NewMIs)
const
virtual bool unfoldMemoryOperand(
llvm::MachineFunction& MF,
llvm::MachineInstr& MI,
unsigned int Reg,
bool UnfoldLoad,
bool UnfoldStore,
SmallVectorImpl<llvm::MachineInstr*>& NewMIs)
const
Description
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction. If this is possible, returns true as well as the new instructions by reference.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1286
Parameters
- llvm::MachineFunction& MF
- llvm::MachineInstr& MI
- unsigned int Reg
- bool UnfoldLoad
- bool UnfoldStore
- SmallVectorImpl<llvm::MachineInstr*>& NewMIs
¶virtual bool useMachineCombiner() const
virtual bool useMachineCombiner() const
Description
Return true when a target supports MachineCombiner.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1205
¶bool usePreRAHazardRecognizer() const
bool usePreRAHazardRecognizer() const
Description
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1537
¶virtual bool verifyInstruction(
const llvm::MachineInstr& MI,
llvm::StringRef& ErrInfo) const
virtual bool verifyInstruction(
const llvm::MachineInstr& MI,
llvm::StringRef& ErrInfo) const
Description
Perform target-specific instruction verification.
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:1656
Parameters
- const llvm::MachineInstr& MI
- llvm::StringRef& ErrInfo
¶virtual ~TargetInstrInfo()
virtual ~TargetInstrInfo()
Declared at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:105