class X86RegisterInfo

Declaration

class X86RegisterInfo : public X86GenRegisterInfo { /* full declaration omitted */ };

Description

TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDesc objects that represent all of the machine registers that the target has. As such, we simply have to track a pointer to this array so that we can turn register number into a register descriptor.

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:24

Inherits from: X86GenRegisterInfo

Member Variables

private bool Is64Bit
Is64Bit - Is the target 64-bits.
private bool IsWin64
IsWin64 - Is the target on of win64 flavours
private unsigned int SlotSize
SlotSize - Stack slot size in bytes.
private unsigned int StackPtr
StackPtr - X86 physical register used as stack ptr.
private unsigned int FramePtr
FramePtr - X86 physical register used as frame ptr.
private unsigned int BasePtr
BasePtr - X86 physical register used as a base ptr in complex stack frames. I.e., when we need a 3rd base, not just SP and FP, due to variable size stack objects.

Method Overview

Inherited from X86GenRegisterInfo:

Inherited from TargetRegisterInfo:

Inherited from MCRegisterInfo:

Methods

X86RegisterInfo(const llvm::Triple& TT)

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:52

Parameters

const llvm::Triple& TT

void adjustStackMapLiveOutMask(
    uint32_t* Mask) const

Description

Prior to adding the live-out mask to a stackmap or patchpoint instruction, provide the target the opportunity to adjust it (mainly to remove pseudo-registers that should be ignored).

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:130

Parameters

uint32_t* Mask

bool canRealignStack(
    const llvm::MachineFunction& MF) const

Description

True if the stack can be realigned for the target.

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:134

Parameters

const llvm::MachineFunction& MF

void eliminateFrameIndex(
    MachineBasicBlock::iterator MI,
    int SPAdj,
    unsigned int FIOperandNum,
    llvm::RegScavenger* RS = nullptr) const

Description

This method must be overriden to eliminate abstract frame indices from instructions which may use them. The instruction referenced by the iterator contains an MO_FrameIndex operand which must be eliminated by this method. This method may modify or replace the specified instruction, as long as it keeps the iterator pointing at the finished product. SPAdj is the SP adjustment due to call frame setup instruction. FIOperandNum is the FI operand number.

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:136

Parameters

MachineBasicBlock::iterator MI
int SPAdj
unsigned int FIOperandNum
llvm::RegScavenger* RS = nullptr

unsigned int findDeadCallerSavedReg(
    llvm::MachineBasicBlock& MBB,
    MachineBasicBlock::iterator& MBBI) const

Description

findDeadCallerSavedReg - Return a caller-saved register that isn't live when it reaches the "return" instruction. We can then pop a stack object to this register without worry about clobbering it.

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:143

Parameters

llvm::MachineBasicBlock& MBB
MachineBasicBlock::iterator& MBBI

llvm::Register getBaseRegister() const

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:151

const uint32_t* getCallPreservedMask(
    const llvm::MachineFunction& MF,
    CallingConv::ID) const

Description

Return a mask of call-preserved registers for the given calling convention on the current function. The mask should include all call-preserved aliases. This is used by the register allocator to determine which registers can be live across a call. The mask is an array containing (TRI::getNumRegs()+31)/32 entries. A set bit indicates that all bits of the corresponding register are preserved across the function call. The bit mask is expected to be sub-register complete, i.e. if A is preserved, so are all its sub-registers. Bits are numbered from the LSB, so the bit for physical register Reg can be found as (Mask[Reg / 32] >> Reg % 32) & 1. A NULL pointer means that no register mask will be used, and call instructions should use implicit-def operands to indicate call clobbered registers.

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:104

Parameters

const llvm::MachineFunction& MF
CallingConv::ID 

const llvm::MCPhysReg* getCalleeSavedRegs(
    const llvm::MachineFunction* MF) const

Description

getCalleeSavedRegs - Return a null-terminated list of all of the callee-save registers on this target.

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:101

Parameters

const llvm::MachineFunction* MF

const llvm::MCPhysReg* getCalleeSavedRegsViaCopy(
    const llvm::MachineFunction* MF) const

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:103

Parameters

const llvm::MachineFunction* MF

const llvm::TargetRegisterClass*
getCrossCopyRegClass(
    const llvm::TargetRegisterClass* RC) const

Description

getCrossCopyRegClass - Returns a legal register class to copy a register in the specified class to or from. Returns NULL if it is possible to copy between a two registers of the specified class.

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:88

Parameters

const llvm::TargetRegisterClass* RC

const uint32_t* getDarwinTLSCallPreservedMask()
    const

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:110

llvm::Register getFramePtr() const

Description

Returns physical register used as frame pointer. This will always returns the frame pointer register, contrary to getFrameRegister() which returns the "base pointer" in situations involving a stack, frame and base pointer.

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:156

llvm::Register getFrameRegister(
    const llvm::MachineFunction& MF) const

Description

getFrameRegister - This method should return the register used as a base for values allocated in the current stack frame.

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:147

Parameters

const llvm::MachineFunction& MF

const llvm::TargetRegisterClass*
getGPRsForTailCall(
    const llvm::MachineFunction& MF) const

Description

getGPRsForTailCall - Returns a register class with registers that can be used in forming tail calls.

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:93

Parameters

const llvm::MachineFunction& MF

const llvm::TargetRegisterClass*
getLargestLegalSuperClass(
    const llvm::TargetRegisterClass* RC,
    const llvm::MachineFunction& MF) const

Description

Returns the largest super class of RC that is legal to use in the current sub-target and has the same spill size. The returned register class can be used to create virtual registers which means that all its registers can be copied and spilled.

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:70

Parameters

const llvm::TargetRegisterClass* RC
const llvm::MachineFunction& MF

const llvm::TargetRegisterClass*
getMatchingSuperRegClass(
    const llvm::TargetRegisterClass* A,
    const llvm::TargetRegisterClass* B,
    unsigned int Idx) const

Description

getMatchingSuperRegClass - Return a subclass of the specified register class A so that each register in it has a sub-register of the specified sub-register index which is in the specified register class B.

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:61

Parameters

const llvm::TargetRegisterClass* A
const llvm::TargetRegisterClass* B
unsigned int Idx

const uint32_t* getNoPreservedMask() const

Description

Return a register mask that clobbers everything.

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:106

const llvm::TargetRegisterClass*
getPointerRegClass(
    const llvm::MachineFunction& MF,
    unsigned int Kind = 0) const

Description

getPointerRegClass - Returns a TargetRegisterClass used for pointer values.

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:81

Parameters

const llvm::MachineFunction& MF
unsigned int Kind = 0

unsigned int getPtrSizedFrameRegister(
    const llvm::MachineFunction& MF) const

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:148

Parameters

const llvm::MachineFunction& MF

unsigned int getPtrSizedStackRegister(
    const llvm::MachineFunction& MF) const

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:149

Parameters

const llvm::MachineFunction& MF

bool getRegAllocationHints(
    llvm::Register VirtReg,
    ArrayRef<llvm::MCPhysReg> Order,
    SmallVectorImpl<llvm::MCPhysReg>& Hints,
    const llvm::MachineFunction& MF,
    const llvm::VirtRegMap* VRM,
    const llvm::LiveRegMatrix* Matrix) const

Description

Get a list of 'hint' registers that the register allocator should try first when allocating a physical register for the virtual register VirtReg. These registers are effectively moved to the front of the allocation order. If true is returned, regalloc will try to only use hints to the greatest extent possible even if it means spilling. The Order argument is the allocation order for VirtReg's register class as returned from RegisterClassInfo::getOrder(). The hint registers must come from Order, and they must not be reserved. The default implementation of this function will only add target independent register allocation hints. Targets that override this function should typically call this default implementation as well and expect to see generic copy hints added.

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:160

Parameters

llvm::Register VirtReg
ArrayRef<llvm::MCPhysReg> Order
SmallVectorImpl<llvm::MCPhysReg>& Hints
const llvm::MachineFunction& MF
const llvm::VirtRegMap* VRM
const llvm::LiveRegMatrix* Matrix

unsigned int getRegPressureLimit(
    const llvm::TargetRegisterClass* RC,
    llvm::MachineFunction& MF) const

Description

Return the register pressure "high water mark" for the specific register class. The scheduler is in high register pressure mode (for the specific register class) if it goes over the limit. Note: this is the old register pressure model that relies on a manually specified representative register class per value type.

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:95

Parameters

const llvm::TargetRegisterClass* RC
llvm::MachineFunction& MF

llvm::BitVector getReservedRegs(
    const llvm::MachineFunction& MF) const

Description

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times, e.g. SP, RA. This is used by register scavenger to determine what registers are free.

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:116

Parameters

const llvm::MachineFunction& MF

int getSEHRegNum(unsigned int i) const

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:55

Parameters

unsigned int i

unsigned int getSlotSize() const

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:158

llvm::Register getStackRegister() const

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:150

const llvm::TargetRegisterClass*
getSubClassWithSubReg(
    const llvm::TargetRegisterClass* RC,
    unsigned int Idx) const

Description

Returns the largest legal sub-class of RC that supports the sub-register index Idx. If no such sub-class exists, return NULL. If all registers in RC already have an Idx sub-register, return RC. TableGen generates a version of this function that is good enough in most cases. Targets can override if they have constraints that TableGen doesn't understand. For example, the x86 sub_8bit sub-register index is supported by the full GR32 register class in 64-bit mode, but only by the GR32_ABCD regiister class in 32-bit mode. TableGen will synthesize missing RC sub-classes.

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:66

Parameters

const llvm::TargetRegisterClass* RC
unsigned int Idx

bool hasBasePointer(
    const llvm::MachineFunction& MF) const

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:132

Parameters

const llvm::MachineFunction& MF

bool isArgumentRegister(
    const llvm::MachineFunction& MF,
    llvm::MCRegister Reg) const

Description

isArgumentReg - Returns true if Reg can be used as an argument to a function.

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:120

Parameters

const llvm::MachineFunction& MF
llvm::MCRegister Reg

bool isFixedRegister(
    const llvm::MachineFunction& MF,
    llvm::MCRegister PhysReg) const

Description

Returns true if PhysReg is a fixed register.

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:127

Parameters

const llvm::MachineFunction& MF
llvm::MCRegister PhysReg

bool isTileRegisterClass(
    const llvm::TargetRegisterClass* RC) const

Description

Return true if it is tile register class.

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:124

Parameters

const llvm::TargetRegisterClass* RC

bool shouldRewriteCopySrc(
    const llvm::TargetRegisterClass* DefRC,
    unsigned int DefSubReg,
    const llvm::TargetRegisterClass* SrcRC,
    unsigned int SrcSubReg) const

Declared at: llvm/lib/Target/X86/X86RegisterInfo.h:73

Parameters

const llvm::TargetRegisterClass* DefRC
unsigned int DefSubReg
const llvm::TargetRegisterClass* SrcRC
unsigned int SrcSubReg