class ScheduleDAGMILive

Declaration

class ScheduleDAGMILive : public ScheduleDAGMI { /* full declaration omitted */ };

Description

ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while updating LiveIntervals and tracking regpressure.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:392

Inherits from: ScheduleDAGMI

Member Variables

protected llvm::RegisterClassInfo* RegClassInfo

protected llvm::SchedDFSResult* DFSResult = nullptr

Information about DAG subtrees. If DFSResult is NULL, then SchedulerTrees will be empty.

protected llvm::BitVector ScheduledTrees

protected MachineBasicBlock::iterator LiveRegionEnd

protected llvm::VReg2SUnitMultiMap VRegUses

Maps vregs to the SUnits of their uses in the current scheduling region.

protected llvm::PressureDiffs SUPressureDiffs

protected bool ShouldTrackPressure = false

Register pressure in this region computed by initRegPressure.

protected bool ShouldTrackLaneMasks = false

protected llvm::IntervalPressure RegPressure

protected llvm::RegPressureTracker RPTracker

protected std::vector<PressureChange> RegionCriticalPSets

List of pressure sets that exceed the target's pressure limit before scheduling, listed in increasing set ID order. Each pressure set is paired with its max pressure in the currently scheduled regions.

protected llvm::IntervalPressure TopPressure

The top of the unscheduled zone.

protected llvm::RegPressureTracker TopRPTracker

protected llvm::IntervalPressure BotPressure

The bottom of the unscheduled zone.

protected llvm::RegPressureTracker BotRPTracker

Inherited from ScheduleDAGMI:

protected AA

protected LIS

protected SchedImpl

protected Mutations

protected CurrentTop

protected CurrentBottom

protected NextClusterPred = nullptr

protected NextClusterSucc = nullptr

Inherited from ScheduleDAGInstrs:

protected MLI

protected MFI

protected SchedModel

protected RemoveKillFlags

protected CanHandleTerminators = false

protected TrackLaneMasks = false

protected BB

protected RegionBegin

protected RegionEnd

protected NumRegionInstrs

protected MISUnitMap

protected Defs

protected Uses

protected CurrentVRegDefs

protected CurrentVRegUses

protected AAForDep = nullptr

protected BarrierChain = nullptr

protected UnknownValue

protected Topo

protected DbgValues

protected FirstDbgValue = nullptr

protected LiveRegs

Inherited from ScheduleDAG:

public TM

public TII

public TRI

public MF

public MRI

public SUnits

public EntrySU

public ExitSU

public StressSched

Method Overview

• public ScheduleDAGMILive(llvm::MachineSchedContext * C, std::unique_ptr<MachineSchedStrategy> S)
• protected void buildDAGWithRegPressure()
• protected void collectVRegUses(llvm::SUnit & SU)
• public unsigned int computeCyclicCriticalPath()
• public void computeDFSResult()
• public void dump() const
• public void enterRegion(llvm::MachineBasicBlock * bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned int regioninstrs)
• public const llvm::IntervalPressure & getBotPressure() const
• public const llvm::RegPressureTracker & getBotRPTracker() const
• public const llvm::SchedDFSResult * getDFSResult() const
• public llvm::PressureDiff & getPressureDiff(const llvm::SUnit * SU)
• public const llvm::PressureDiff & getPressureDiff(const llvm::SUnit * SU) const
• public const llvm::IntervalPressure & getRegPressure() const
• public const std::vector<PressureChange> & getRegionCriticalPSets() const
• public llvm::BitVector & getScheduledTrees()
• public const llvm::IntervalPressure & getTopPressure() const
• public const llvm::RegPressureTracker & getTopRPTracker() const
• public bool hasVRegLiveness() const
• protected void initQueues(ArrayRef<llvm::SUnit *> TopRoots, ArrayRef<llvm::SUnit *> BotRoots)
• protected void initRegPressure()
• public bool isTrackingPressure() const
• public void schedule()
• protected void scheduleMI(llvm::SUnit * SU, bool IsTopNode)
• protected void updatePressureDiffs(ArrayRef<llvm::RegisterMaskPair> LiveUses)
• protected void updateScheduledPressure(const llvm::SUnit * SU, const std::vector<unsigned int> & NewMaxPressure)
• public ~ScheduleDAGMILive()

Inherited from ScheduleDAGMI:

• public addMutation
• public bottom
• protected checkSchedLimit
• public doMBBSchedRegionsTopDown
• protected dumpSchedule
• public enterRegion
• protected findRootsAndBiasEdges
• public finishBlock
• public getLIS
• public getNextClusterPred
• public getNextClusterSucc
• public hasVRegLiveness
• protected initQueues
• public moveInstruction
• protected placeDebugValues
• protected postprocessDAG
• protected releasePred
• protected releasePredecessors
• protected releaseSucc
• protected releaseSuccessors
• public schedule
• public startBlock
• public top
• protected updateQueues
• public viewGraph
• public viewGraph

Inherited from ScheduleDAGInstrs:

• public IsReachable
• protected addBarrierChain
• protected addChainDependencies
• protected addChainDependencies
• protected addChainDependencies
• protected addChainDependency
• public addEdge
• protected addPhysRegDataDeps
• protected addPhysRegDeps
• public addSchedBarrierDeps
• protected addVRegDefDeps
• protected addVRegUseDeps
• public begin
• public buildSchedGraph
• public canAddEdge
• protected deadDefHasNoUse
• public doMBBSchedRegionsTopDown
• public dump
• public dumpNode
• public end
• public enterRegion
• public exitRegion
• public finalizeSchedule
• public finishBlock
• public fixupKills
• public getDAGName
• public getGraphNodeLabel
• protected getLaneMaskForMO
• public getSUnit
• public getSchedClass
• public getSchedModel
• protected initSUnits
• protected insertBarrierChain
• public newSUnit
• protected reduceHugeMemNodeMaps
• public schedule
• public startBlock

Inherited from ScheduleDAG:

• public VerifyScheduledDAG
• public addCustomGraphFeatures
• public clearDAG
• public dump
• public dumpNode
• protected dumpNodeAll
• public dumpNodeName
• public getDAGName
• public getGraphNodeLabel
• public getInstrDesc
• public viewGraph
• public viewGraph

Methods

¶ScheduleDAGMILive(
    llvm::MachineSchedContext* C,
    std::unique_ptr<MachineSchedStrategy> S)

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:431

Parameters

llvm::MachineSchedContext* C

std::unique_ptr<MachineSchedStrategy> S

¶void buildDAGWithRegPressure()

Description

Call ScheduleDAGInstrs::buildSchedGraph with register pressure tracking enabled. This sets up three trackers. RPTracker will cover the entire DAG region, TopTracker and BottomTracker will be initialized to the top and bottom of the DAG region without covereing any unscheduled instruction.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:500

¶void collectVRegUses(llvm::SUnit& SU)

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:518

Parameters

llvm::SUnit& SU

¶unsigned int computeCyclicCriticalPath()

Description

Compute the cyclic critical path through the DAG.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:489

¶void computeDFSResult()

Description

Compute a DFSResult after DAG building is complete, and before any queue comparisons.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:469

¶void dump() const

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:491

¶void enterRegion(
    llvm::MachineBasicBlock* bb,
    MachineBasicBlock::iterator begin,
    MachineBasicBlock::iterator end,
    unsigned int regioninstrs)

Description

Implement the ScheduleDAGInstrs interface for handling the next scheduling region. This covers all instructions in a block, while schedule() may only cover a subset.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:479

Parameters

llvm::MachineBasicBlock* bb

MachineBasicBlock::iterator begin

MachineBasicBlock::iterator end

unsigned int regioninstrs

¶const llvm::IntervalPressure& getBotPressure()
    const

Description

Get current register pressure for the bottom scheduled instructions.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:450

¶const llvm::RegPressureTracker& getBotRPTracker()
    const

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:451

¶const llvm::SchedDFSResult* getDFSResult() const

Description

Return a non-null DFS result if the scheduling strategy initialized it.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:472

¶llvm::PressureDiff& getPressureDiff(
    const llvm::SUnit* SU)

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:460

Parameters

const llvm::SUnit* SU

¶const llvm::PressureDiff& getPressureDiff(
    const llvm::SUnit* SU) const

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:463

Parameters

const llvm::SUnit* SU

¶const llvm::IntervalPressure& getRegPressure()
    const

Description

Get register pressure for the entire scheduling region before scheduling.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:454

¶const std::vector<PressureChange>&
getRegionCriticalPSets() const

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:456

¶llvm::BitVector& getScheduledTrees()

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:474

¶const llvm::IntervalPressure& getTopPressure()
    const

Description

Get current register pressure for the top scheduled instructions.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:446

¶const llvm::RegPressureTracker& getTopRPTracker()
    const

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:447

¶bool hasVRegLiveness() const

Description

Return true if this DAG supports VReg liveness and RegPressure.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:440

¶void initQueues(ArrayRef<llvm::SUnit*> TopRoots,
                ArrayRef<llvm::SUnit*> BotRoots)

Description

Release ExitSU predecessors and setup scheduler queues. Re-position the Top RP tracker in case the region beginning has changed.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:504

Parameters

ArrayRef<llvm::SUnit*> TopRoots

ArrayRef<llvm::SUnit*> BotRoots

¶void initRegPressure()

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:511

¶bool isTrackingPressure() const

Description

Return true if register pressure tracking is enabled.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:443

¶void schedule()

Description

Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:486

¶void scheduleMI(llvm::SUnit* SU, bool IsTopNode)

Description

Move an instruction and update register pressure.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:507

Parameters

llvm::SUnit* SU

bool IsTopNode

¶void updatePressureDiffs(
    ArrayRef<llvm::RegisterMaskPair> LiveUses)

Description

Update the PressureDiff array for liveness after scheduling this instruction.

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:513

Parameters

ArrayRef<llvm::RegisterMaskPair> LiveUses

¶void updateScheduledPressure(
    const llvm::SUnit* SU,
    const std::vector<unsigned int>&
        NewMaxPressure)

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:515

Parameters

const llvm::SUnit* SU

const std::vector<unsigned int>& NewMaxPressure

¶~ScheduleDAGMILive()

Declared at: llvm/include/llvm/CodeGen/MachineScheduler.h:437