class X86TargetLowering
Declaration
class X86TargetLowering : public TargetLowering { /* full declaration omitted */ };
Description
This class defines information used to lower LLVM code to legal SelectionDAG operators that the target instruction selector can accept natively. This class also defines callbacks that targets must implement to lower target-specific constructs to SelectionDAG operators.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:937
Inherits from: TargetLowering
Member Variables
- private const llvm::X86Subtarget& Subtarget
- Keep a reference to the X86Subtarget around so that we can make the right decision when generating code for different targets.
- private std::vector<APFloat> LegalFPImmediates
- A list of legal FP immediates.
Inherited from TargetLoweringBase:
- protected GatherAllAliasesMaxDepth
- protected MaxStoresPerMemset
- protected MaxStoresPerMemsetOptSize
- protected MaxStoresPerMemcpy
- protected MaxStoresPerMemcpyOptSize
- protected MaxGluedStoresPerMemcpy = 0
- protected MaxLoadsPerMemcmp
- protected MaxLoadsPerMemcmpOptSize
- protected MaxStoresPerMemmove
- protected MaxStoresPerMemmoveOptSize
- protected PredictableSelectIsExpensive
- protected EnableExtLdPromotion
- protected IsStrictFPEnabled
Method Overview
- public std::pair<SDValue, SDValue> BuildFILD(llvm::EVT DstVT, llvm::EVT SrcVT, const llvm::SDLoc & DL, llvm::SDValue Chain, llvm::SDValue Pointer, llvm::MachinePointerInfo PtrInfo, llvm::Align Alignment, llvm::SelectionDAG & DAG) const
- private llvm::SDValue BuildSDIVPow2(llvm::SDNode * N, const llvm::APInt & Divisor, llvm::SelectionDAG & DAG, SmallVectorImpl<llvm::SDNode *> & Created) const
- private bool CanLowerReturn(CallingConv::ID CallConv, llvm::MachineFunction & MF, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> & Outs, llvm::LLVMContext & Context) const
- public unsigned int ComputeNumSignBitsForTargetNode(llvm::SDValue Op, const llvm::APInt & DemandedElts, const llvm::SelectionDAG & DAG, unsigned int Depth) const
- public llvm::MachineBasicBlock * EmitInstrWithCustomInserter(llvm::MachineInstr & MI, llvm::MachineBasicBlock * MBB) const
- private llvm::MachineBasicBlock * EmitLoweredCascadedSelect(llvm::MachineInstr & MI1, llvm::MachineInstr & MI2, llvm::MachineBasicBlock * BB) const
- private llvm::MachineBasicBlock * EmitLoweredCatchRet(llvm::MachineInstr & MI, llvm::MachineBasicBlock * BB) const
- private llvm::MachineBasicBlock * EmitLoweredIndirectThunk(llvm::MachineInstr & MI, llvm::MachineBasicBlock * BB) const
- private llvm::MachineBasicBlock * EmitLoweredProbedAlloca(llvm::MachineInstr & MI, llvm::MachineBasicBlock * BB) const
- private llvm::MachineBasicBlock * EmitLoweredSegAlloca(llvm::MachineInstr & MI, llvm::MachineBasicBlock * BB) const
- private llvm::MachineBasicBlock * EmitLoweredSelect(llvm::MachineInstr & I, llvm::MachineBasicBlock * BB) const
- private llvm::MachineBasicBlock * EmitLoweredTLSAddr(llvm::MachineInstr & MI, llvm::MachineBasicBlock * BB) const
- private llvm::MachineBasicBlock * EmitLoweredTLSCall(llvm::MachineInstr & MI, llvm::MachineBasicBlock * BB) const
- private llvm::MachineBasicBlock * EmitSjLjDispatchBlock(llvm::MachineInstr & MI, llvm::MachineBasicBlock * MBB) const
- private llvm::SDValue EmitTailCallLoadRetAddr(llvm::SelectionDAG & DAG, llvm::SDValue & OutRetAddr, llvm::SDValue Chain, bool IsTailCall, bool Is64Bit, int FPDiff, const llvm::SDLoc & dl) const
- private llvm::MachineBasicBlock * EmitVAARGWithCustomInserter(llvm::MachineInstr & MI, llvm::MachineBasicBlock * MBB) const
- public bool ExpandInlineAsm(llvm::CallInst * CI) const
- private llvm::SDValue FP_TO_INTHelper(llvm::SDValue Op, llvm::SelectionDAG & DAG, bool IsSigned, llvm::SDValue & Chain) const
- private unsigned int GetAlignedArgumentStackSize(unsigned int StackSize, llvm::SelectionDAG & DAG) const
- public bool IsDesirableToPromoteOp(llvm::SDValue Op, llvm::EVT & PVT) const
- private bool IsEligibleForTailCallOptimization(llvm::SDValue Callee, CallingConv::ID CalleeCC, bool IsCalleeStackStructRet, bool isVarArg, llvm::Type * RetTy, const SmallVectorImpl<ISD::OutputArg> & Outs, const SmallVectorImpl<llvm::SDValue> & OutVals, const SmallVectorImpl<ISD::InputArg> & Ins, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LRINT_LLRINTHelper(llvm::SDNode * N, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerADDROFRETURNADDR(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- public void LowerAsmOperandForConstraint(llvm::SDValue Op, std::string & Constraint, std::vector<SDValue> & Ops, llvm::SelectionDAG & DAG) const
- public llvm::SDValue LowerAsmOutputForConstraint(llvm::SDValue & Chain, llvm::SDValue & Flag, const llvm::SDLoc & DL, const llvm::TargetLowering::AsmOperandInfo & Constraint, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerBRCOND(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerBUILD_VECTOR(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerBlockAddress(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerCall(llvm::TargetLowering::CallLoweringInfo & CLI, SmallVectorImpl<llvm::SDValue> & InVals) const
- private llvm::SDValue LowerCallResult(llvm::SDValue Chain, llvm::SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> & Ins, const llvm::SDLoc & dl, llvm::SelectionDAG & DAG, SmallVectorImpl<llvm::SDValue> & InVals, uint32_t * RegMask) const
- private llvm::SDValue LowerConstantPool(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- public const llvm::MCExpr * LowerCustomJumpTableEntry(const llvm::MachineJumpTableInfo * MJTI, const llvm::MachineBasicBlock * MBB, unsigned int uid, llvm::MCContext & Ctx) const
- private llvm::SDValue LowerDYNAMIC_STACKALLOC(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerEH_RETURN(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerEXTRACT_VECTOR_ELT(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerExternalSymbol(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerFLT_ROUNDS_(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerFP_EXTEND(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerFP_ROUND(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerFP_TO_BF16(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerFP_TO_INT(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerFP_TO_INT_SAT(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerFRAMEADDR(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerFRAME_TO_ARGS_OFFSET(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerFormalArguments(llvm::SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> & Ins, const llvm::SDLoc & dl, llvm::SelectionDAG & DAG, SmallVectorImpl<llvm::SDValue> & InVals) const
- private llvm::SDValue LowerGC_TRANSITION(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerGlobalAddress(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerGlobalOrExternal(llvm::SDValue Op, llvm::SelectionDAG & DAG, bool ForCall) const
- private llvm::SDValue LowerGlobalTLSAddress(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerINIT_TRAMPOLINE(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerINSERT_VECTOR_ELT(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerINTRINSIC_WO_CHAIN(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerJumpTable(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerLRINT_LLRINT(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerMemArgument(llvm::SDValue Chain, CallingConv::ID CallConv, const SmallVectorImpl<ISD::InputArg> & ArgInfo, const llvm::SDLoc & dl, llvm::SelectionDAG & DAG, const llvm::CCValAssign & VA, llvm::MachineFrameInfo & MFI, unsigned int i) const
- private llvm::SDValue LowerMemOpCallTo(llvm::SDValue Chain, llvm::SDValue StackPtr, llvm::SDValue Arg, const llvm::SDLoc & dl, llvm::SelectionDAG & DAG, const llvm::CCValAssign & VA, ISD::ArgFlagsTy Flags, bool isByval) const
- public llvm::SDValue LowerOperation(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerRETURNADDR(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerReturn(llvm::SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> & Outs, const SmallVectorImpl<llvm::SDValue> & OutVals, const llvm::SDLoc & dl, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerSELECT(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerSETCC(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerSETCCCARRY(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerSET_ROUNDING(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerSINT_TO_FP(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerTRUNCATE(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerUINT_TO_FP(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerVAARG(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerVASTART(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerVSELECT(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerWin64_FP_TO_INT128(llvm::SDValue Op, llvm::SelectionDAG & DAG, llvm::SDValue & Chain) const
- private llvm::SDValue LowerWin64_INT128_TO_FP(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue LowerWin64_i128OP(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- public const char * LowerXConstraint(llvm::EVT ConstraintVT) const
- public llvm::SDValue PerformDAGCombine(llvm::SDNode * N, llvm::TargetLowering::DAGCombinerInfo & DCI) const
- public void ReplaceNodeResults(llvm::SDNode * N, SmallVectorImpl<llvm::SDValue> & Results, llvm::SelectionDAG & DAG) const
- private void SetupEntryBlockForSjLj(llvm::MachineInstr & MI, llvm::MachineBasicBlock * MBB, llvm::MachineBasicBlock * DispatchBB, int FI) const
- public bool ShouldShrinkFPConstant(llvm::EVT VT) const
- public bool SimplifyDemandedBitsForTargetNode(llvm::SDValue Op, const llvm::APInt & DemandedBits, const llvm::APInt & DemandedElts, llvm::KnownBits & Known, llvm::TargetLowering::TargetLoweringOpt & TLO, unsigned int Depth) const
- public bool SimplifyDemandedVectorEltsForTargetNode(llvm::SDValue Op, const llvm::APInt & DemandedElts, llvm::APInt & KnownUndef, llvm::APInt & KnownZero, llvm::TargetLowering::TargetLoweringOpt & TLO, unsigned int Depth) const
- public bool SimplifyDemandedVectorEltsForTargetShuffle(llvm::SDValue Op, const llvm::APInt & DemandedElts, unsigned int MaskIndex, llvm::TargetLowering::TargetLoweringOpt & TLO, unsigned int Depth) const
- public llvm::SDValue SimplifyMultipleUseDemandedBitsForTargetNode(llvm::SDValue Op, const llvm::APInt & DemandedBits, const llvm::APInt & DemandedElts, llvm::SelectionDAG & DAG, unsigned int Depth) const
- public X86TargetLowering(const llvm::X86TargetMachine & TM, const llvm::X86Subtarget & STI)
- private void addLegalFPImmediate(const llvm::APFloat & Imm)
- public bool allowTruncateForTailCall(llvm::Type * Ty1, llvm::Type * Ty2) const
- public bool allowsMisalignedMemoryAccesses(llvm::EVT VT, unsigned int AS, llvm::Align Alignment, MachineMemOperand::Flags Flags, bool * Fast) const
- public bool areJTsAllowed(const llvm::Function * Fn) const
- public bool canMergeStoresTo(unsigned int AddressSpace, llvm::EVT MemVT, const llvm::MachineFunction & MF) const
- private unsigned int combineRepeatedFPDivisors() const
- public void computeKnownBitsForTargetNode(const llvm::SDValue Op, llvm::KnownBits & Known, const llvm::APInt & DemandedElts, const llvm::SelectionDAG & DAG, unsigned int Depth = 0) const
- public bool convertSelectOfConstantsToMath(llvm::EVT VT) const
- public bool convertSetCCLogicToBitwiseLogic(llvm::EVT VT) const
- public llvm::FastISel * createFastISel(llvm::FunctionLoweringInfo & funcInfo, const llvm::TargetLibraryInfo * libInfo) const
- public bool decomposeMulByConstant(llvm::LLVMContext & Context, llvm::EVT VT, llvm::SDValue C) const
- private void emitBitTestAtomicRMWIntrinsic(llvm::AtomicRMWInst * AI) const
- private llvm::MachineBasicBlock * emitEHSjLjLongJmp(llvm::MachineInstr & MI, llvm::MachineBasicBlock * MBB) const
- private llvm::MachineBasicBlock * emitEHSjLjSetJmp(llvm::MachineInstr & MI, llvm::MachineBasicBlock * MBB) const
- private llvm::SDValue emitFlagsForSetcc(llvm::SDValue Op0, llvm::SDValue Op1, ISD::CondCode CC, const llvm::SDLoc & dl, llvm::SelectionDAG & DAG, llvm::SDValue & X86CC) const
- private llvm::MachineBasicBlock * emitLongJmpShadowStackFix(llvm::MachineInstr & MI, llvm::MachineBasicBlock * MBB) const
- private void emitSetJmpShadowStackFix(llvm::MachineInstr & MI, llvm::MachineBasicBlock * MBB) const
- public llvm::SDValue emitStackGuardXorFP(llvm::SelectionDAG & DAG, llvm::SDValue Val, const llvm::SDLoc & DL) const
- public llvm::SDValue expandIndirectJTBranch(const llvm::SDLoc & dl, llvm::SDValue Value, llvm::SDValue Addr, llvm::SelectionDAG & DAG) const
- protected std::pair<const TargetRegisterClass *, uint8_t> findRepresentativeClass(const llvm::TargetRegisterInfo * TRI, llvm::MVT VT) const
- private unsigned int getAddressSpace() const
- public uint64_t getByValTypeAlignment(llvm::Type * Ty, const llvm::DataLayout & DL) const
- public const char * getClearCacheBuiltinName() const
- public llvm::TargetLowering::ConstraintType getConstraintType(llvm::StringRef Constraint) const
- public llvm::Register getExceptionPointerRegister(const llvm::Constant * PersonalityFn) const
- public llvm::Register getExceptionSelectorRegister(const llvm::Constant * PersonalityFn) const
- private unsigned int getGlobalWrapperKind(const llvm::GlobalValue * GV = nullptr, const unsigned char OpFlags = 0) const
- public llvm::Value * getIRStackGuard(llvm::IRBuilderBase & IRB) const
- public unsigned int getInlineAsmMemConstraint(llvm::StringRef ConstraintCode) const
- public unsigned int getJumpTableEncoding() const
- public unsigned int getMaxSupportedInterleaveFactor() const
- public llvm::SDValue getNegatedExpression(llvm::SDValue Op, llvm::SelectionDAG & DAG, bool LegalOperations, bool ForCodeSize, llvm::TargetLoweringBase::NegatibleCost & Cost, unsigned int Depth) const
- public unsigned int getNumRegistersForCallingConv(llvm::LLVMContext & Context, CallingConv::ID CC, llvm::EVT VT) const
- public llvm::EVT getOptimalMemOpType(const llvm::MemOp & Op, const llvm::AttributeList & FuncAttributes) const
- public llvm::SDValue getPICJumpTableRelocBase(llvm::SDValue Table, llvm::SelectionDAG & DAG) const
- public const llvm::MCExpr * getPICJumpTableRelocBaseExpr(const llvm::MachineFunction * MF, unsigned int JTI, llvm::MCContext & Ctx) const
- public llvm::Align getPrefLoopAlignment(llvm::MachineLoop * ML) const
- public llvm::MVT getPreferredSwitchConditionType(llvm::LLVMContext & Context, llvm::EVT ConditionVT) const
- public llvm::TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(llvm::MVT VT) const
- private llvm::SDValue getRecipEstimate(llvm::SDValue Op, llvm::SelectionDAG & DAG, int Enabled, int & RefinementSteps) const
- public std::pair<unsigned int, const TargetRegisterClass *> getRegForInlineAsmConstraint(const llvm::TargetRegisterInfo * TRI, llvm::StringRef Constraint, llvm::MVT VT) const
- public llvm::Register getRegisterByName(const char * RegName, llvm::LLT VT, const llvm::MachineFunction & MF) const
- public llvm::MVT getRegisterTypeForCallingConv(llvm::LLVMContext & Context, CallingConv::ID CC, llvm::EVT VT) const
- public llvm::SDValue getReturnAddressFrameIndex(llvm::SelectionDAG & DAG) const
- public llvm::Value * getSDagStackGuard(const llvm::Module & M) const
- public llvm::Function * getSSPStackGuardCheck(const llvm::Module & M) const
- public llvm::Value * getSafeStackPointerLocation(llvm::IRBuilderBase & IRB) const
- public llvm::MVT getScalarShiftAmountTy(const llvm::DataLayout &, llvm::EVT VT) const
- public llvm::InstructionCost getScalingFactorCost(const llvm::DataLayout & DL, const llvm::TargetLoweringBase::AddrMode & AM, llvm::Type * Ty, unsigned int AS) const
- private const llvm::MCPhysReg * getScratchRegisters(CallingConv::ID CC) const
- public llvm::EVT getSetCCResultType(const llvm::DataLayout & DL, llvm::LLVMContext & Context, llvm::EVT VT) const
- public llvm::TargetLowering::ConstraintWeight getSingleConstraintMatchWeight(llvm::TargetLowering::AsmOperandInfo & info, const char * constraint) const
- private llvm::SDValue getSqrtEstimate(llvm::SDValue Op, llvm::SelectionDAG & DAG, int Enabled, int & RefinementSteps, bool & UseOneConstNR, bool Reciprocal) const
- public unsigned int getStackProbeSize(llvm::MachineFunction & MF) const
- public llvm::StringRef getStackProbeSymbolName(llvm::MachineFunction & MF) const
- public const llvm::Constant * getTargetConstantFromLoad(llvm::LoadSDNode * LD) const
- public const char * getTargetNodeName(unsigned int Opcode) const
- public bool getTgtMemIntrinsic(llvm::TargetLoweringBase::IntrinsicInfo & Info, const llvm::CallInst & I, llvm::MachineFunction & MF, unsigned int Intrinsic) const
- private llvm::EVT getTypeForExtReturn(llvm::LLVMContext & Context, llvm::EVT VT, ISD::NodeType ExtendKind) const
- public unsigned int getVectorTypeBreakdownForCallingConv(llvm::LLVMContext & Context, CallingConv::ID CC, llvm::EVT VT, llvm::EVT & IntermediateVT, unsigned int & NumIntermediates, llvm::MVT & RegisterVT) const
- public bool hasAndNot(llvm::SDValue Y) const
- public bool hasAndNotCompare(llvm::SDValue Y) const
- public bool hasBitPreservingFPLogic(llvm::EVT VT) const
- public bool hasBitTest(llvm::SDValue X, llvm::SDValue Y) const
- public llvm::MVT hasFastEqualityCompare(unsigned int NumBits) const
- public bool hasInlineStackProbe(llvm::MachineFunction & MF) const
- public bool hasStackProbeSymbol(llvm::MachineFunction & MF) const
- public bool hasVectorBlend() const
- private void initializeSplitCSR(llvm::MachineBasicBlock * Entry) const
- private void insertCopiesSplitCSR(llvm::MachineBasicBlock * Entry, const SmallVectorImpl<llvm::MachineBasicBlock *> & Exits) const
- public void insertSSPDeclarations(llvm::Module & M) const
- public bool isBinOp(unsigned int Opcode) const
- public bool isCheapToSpeculateCtlz() const
- public bool isCheapToSpeculateCttz() const
- public bool isCommutativeBinOp(unsigned int Opcode) const
- public bool isCtlzFast() const
- public bool isExtractSubvectorCheap(llvm::EVT ResVT, llvm::EVT SrcVT, unsigned int Index) const
- public bool isExtractVecEltCheap(llvm::EVT VT, unsigned int Index) const
- public bool isFMAFasterThanFMulAndFAdd(const llvm::MachineFunction & MF, llvm::EVT VT) const
- public bool isFPImmLegal(const llvm::APFloat & Imm, llvm::EVT VT, bool ForCodeSize) const
- private bool isFsqrtCheap(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- public bool isIntDivCheap(llvm::EVT VT, llvm::AttributeList Attr) const
- public bool isLegalAddImmediate(int64_t Imm) const
- public bool isLegalAddressingMode(const llvm::DataLayout & DL, const llvm::TargetLoweringBase::AddrMode & AM, llvm::Type * Ty, unsigned int AS, llvm::Instruction * I = nullptr) const
- public bool isLegalICmpImmediate(int64_t Imm) const
- public bool isLegalStoreImmediate(int64_t Imm) const
- public bool isLoadBitCastBeneficial(llvm::EVT LoadVT, llvm::EVT BitcastVT, const llvm::SelectionDAG & DAG, const llvm::MachineMemOperand & MMO) const
- public bool isMaskAndCmp0FoldingBeneficial(const llvm::Instruction & AndI) const
- public bool isMultiStoresCheaperThanBitsMerge(llvm::EVT LTy, llvm::EVT HTy) const
- public bool isNarrowingProfitable(llvm::EVT VT1, llvm::EVT VT2) const
- public bool isSafeMemOpType(llvm::MVT VT) const
- public bool isScalarFPTypeInSSEReg(llvm::EVT VT) const
- public bool isShuffleMaskLegal(ArrayRef<int> Mask, llvm::EVT VT) const
- private template <typename T>bool isSoftFP16(T VT) const
- public bool isSplatValueForTargetNode(llvm::SDValue Op, const llvm::APInt & DemandedElts, llvm::APInt & UndefElts, unsigned int Depth) const
- public bool isTargetCanonicalConstantNode(llvm::SDValue Op) const
- public bool isTruncateFree(llvm::EVT VT1, llvm::EVT VT2) const
- public bool isTruncateFree(llvm::Type * Ty1, llvm::Type * Ty2) const
- public bool isTypeDesirableForOp(unsigned int Opc, llvm::EVT VT) const
- private bool isUsedByReturnOnly(llvm::SDNode * N, llvm::SDValue & Chain) const
- public bool isVectorClearMaskLegal(ArrayRef<int> Mask, llvm::EVT VT) const
- public bool isVectorLoadExtDesirable(llvm::SDValue) const
- public bool isVectorShiftByScalarCheap(llvm::Type * Ty) const
- public bool isZExtFree(llvm::SDValue Val, llvm::EVT VT2) const
- public bool isZExtFree(llvm::EVT VT1, llvm::EVT VT2) const
- public bool isZExtFree(llvm::Type * Ty1, llvm::Type * Ty2) const
- private llvm::SDValue joinRegisterPartsIntoValue(llvm::SelectionDAG & DAG, const llvm::SDLoc & DL, const llvm::SDValue * Parts, unsigned int NumParts, llvm::MVT PartVT, llvm::EVT ValueVT, Optional<CallingConv::ID> CC) const
- private bool lowerAtomicLoadAsLoadSDNode(const llvm::LoadInst & LI) const
- private bool lowerAtomicStoreAsStoreSDNode(const llvm::StoreInst & SI) const
- private llvm::SDValue lowerEH_SJLJ_LONGJMP(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue lowerEH_SJLJ_SETJMP(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue lowerEH_SJLJ_SETUP_DISPATCH(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::SDValue lowerFaddFsub(llvm::SDValue Op, llvm::SelectionDAG & DAG) const
- private llvm::LoadInst * lowerIdempotentRMWIntoFencedLoad(llvm::AtomicRMWInst * AI) const
- public bool lowerInterleavedLoad(llvm::LoadInst * LI, ArrayRef<llvm::ShuffleVectorInst *> Shuffles, ArrayRef<unsigned int> Indices, unsigned int Factor) const
- public bool lowerInterleavedStore(llvm::StoreInst * SI, llvm::ShuffleVectorInst * SVI, unsigned int Factor) const
- public void markLibCallAttributes(llvm::MachineFunction * MF, unsigned int CC, llvm::TargetLoweringBase::ArgListTy & Args) const
- private bool mayBeEmittedAsTailCall(const llvm::CallInst * CI) const
- public bool mergeStoresAfterLegalization(llvm::EVT MemVT) const
- private bool needsCmpXchgNb(llvm::Type * MemType) const
- public bool needsFixedCatchObjects() const
- public bool reduceSelectOfFPConstantLoads(llvm::EVT CmpOpVT) const
- public bool shouldConvertConstantLoadToIntImm(const llvm::APInt & Imm, llvm::Type * Ty) const
- public bool shouldConvertFpToSat(unsigned int Op, llvm::EVT FPVT, llvm::EVT VT) const
- public bool shouldConvertPhiType(llvm::Type * From, llvm::Type * To) const
- private TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicLoadInIR(llvm::LoadInst * LI) const
- private TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicRMWInIR(llvm::AtomicRMWInst * AI) const
- private TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicStoreInIR(llvm::StoreInst * SI) const
- private TargetLoweringBase::AtomicExpansionKind shouldExpandLogicAtomicRMWInIR(llvm::AtomicRMWInst * AI) const
- public bool shouldExpandShift(llvm::SelectionDAG & DAG, llvm::SDNode * N) const
- public bool shouldFoldConstantShiftPairToMask(const llvm::SDNode * N, llvm::CombineLevel Level) const
- public bool shouldFoldMaskToVariableShiftPair(llvm::SDValue Y) const
- public bool shouldFoldSelectWithIdentityConstant(unsigned int BinOpcode, llvm::EVT VT) const
- public bool shouldFormOverflowOp(unsigned int Opcode, llvm::EVT VT, bool MathUsed) const
- public bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(llvm::SDValue X, llvm::ConstantSDNode * XC, llvm::ConstantSDNode * CC, llvm::SDValue Y, unsigned int OldShiftOpcode, unsigned int NewShiftOpcode, llvm::SelectionDAG & DAG) const
- public bool shouldReduceLoadWidth(llvm::SDNode * Load, ISD::LoadExtType ExtTy, llvm::EVT NewVT) const
- public bool shouldScalarizeBinop(llvm::SDValue) const
- public bool shouldSinkOperands(llvm::Instruction * I, SmallVectorImpl<llvm::Use *> & Ops) const
- public bool shouldSplatInsEltVarIndex(llvm::EVT VT) const
- public bool shouldTransformSignedTruncationCheck(llvm::EVT XVT, unsigned int KeptBits) const
- public bool softPromoteHalfType() const
- private bool splitValueIntoRegisterParts(llvm::SelectionDAG & DAG, const llvm::SDLoc & DL, llvm::SDValue Val, llvm::SDValue * Parts, unsigned int NumParts, llvm::MVT PartVT, Optional<CallingConv::ID> CC) const
- public bool storeOfVectorConstantIsCheap(llvm::EVT MemVT, unsigned int NumElem, unsigned int AddrSpace) const
- private bool supportSplitCSR(llvm::MachineFunction * MF) const
- public bool supportSwiftError() const
- public bool targetShrinkDemandedConstant(llvm::SDValue Op, const llvm::APInt & DemandedBits, const llvm::APInt & DemandedElts, llvm::TargetLowering::TargetLoweringOpt & TLO) const
- public llvm::SDValue unwrapAddress(llvm::SDValue N) const
- public bool useLoadStackGuardNode() const
- public bool useSoftFloat() const
- public bool useStackGuardXorFP() const
Inherited from TargetLowering:
- public AdjustInstrPostInstrSelection
- public BuildSDIV
- public BuildSDIVPow2
- public BuildSREMPow2
- public BuildUDIV
- public CanLowerReturn
- public ComputeConstraintToUse
- public ComputeNumSignBitsForTargetNode
- public EmitInstrWithCustomInserter
- public ExpandInlineAsm
- public HandleByVal
- public IncrementMemoryAddress
- public IsDesirableToPromoteOp
- public LegalizeSetCCCondCode
- public LowerAsmOperandForConstraint
- public LowerAsmOutputForConstraint
- public LowerCall
- public LowerCallTo
- public LowerCustomJumpTableEntry
- public LowerFormalArguments
- public LowerOperation
- public LowerOperationWrapper
- public LowerReturn
- public LowerToTLSEmulatedModel
- public LowerXConstraint
- public ParseConstraints
- public PerformDAGCombine
- public ReplaceNodeResults
- public ShrinkDemandedConstant
- public ShrinkDemandedConstant
- public ShrinkDemandedOp
- public SimplifyDemandedBits
- public SimplifyDemandedBits
- public SimplifyDemandedBits
- public SimplifyDemandedBits
- public SimplifyDemandedBitsForTargetNode
- public SimplifyDemandedVectorElts
- public SimplifyDemandedVectorElts
- public SimplifyDemandedVectorEltsForTargetNode
- public SimplifyMultipleUseDemandedBits
- public SimplifyMultipleUseDemandedBits
- public SimplifyMultipleUseDemandedBitsForTargetNode
- public SimplifyMultipleUseDemandedVectorElts
- public SimplifySetCC
- public buildLegalVectorShuffle
- public combineRepeatedFPDivisors
- public computeKnownAlignForTargetInstr
- public computeKnownBitsForFrameIndex
- public computeKnownBitsForTargetInstr
- public computeKnownBitsForTargetNode
- public computeNumSignBitsForTargetInstr
- public createFastISel
- public createSelectForFMINNUM_FMAXNUM
- public emitStackGuardXorFP
- public expandABS
- public expandAddSubSat
- public expandBITREVERSE
- public expandBSWAP
- public expandCTLZ
- public expandCTPOP
- public expandCTTZ
- public expandFMINNUM_FMAXNUM
- public expandFP_TO_INT_SAT
- public expandFP_TO_SINT
- public expandFP_TO_UINT
- public expandFixedPointDiv
- public expandFixedPointMul
- public expandFunnelShift
- public expandIS_FPCLASS
- public expandIndirectJTBranch
- public expandIntMINMAX
- public expandMUL
- public expandMULO
- public expandMUL_LOHI
- public expandREM
- public expandROT
- public expandSADDSUBO
- public expandShiftParts
- public expandShlSat
- public expandUADDSUBO
- public expandUINT_TO_FP
- public expandUnalignedLoad
- public expandUnalignedStore
- public expandVecReduce
- public expandVecReduceSeq
- public expandVectorSplice
- public findOptimalMemOpLowering
- public functionArgumentNeedsConsecutiveRegisters
- public getCheaperNegatedExpression
- public getClearCacheBuiltinName
- public getConstraintType
- public getInlineAsmMemConstraint
- public getJumpTableEncoding
- public getMultipleConstraintMatchWeight
- public getNegatedExpression
- public getNegatedExpression
- public getPICJumpTableRelocBase
- public getPICJumpTableRelocBaseExpr
- public getPostIndexedAddressParts
- public getPreIndexedAddressParts
- public getRecipEstimate
- public getRegForInlineAsmConstraint
- public getRegisterByName
- public getScratchRegisters
- public getSingleConstraintMatchWeight
- public getSqrtEstimate
- public getSqrtInputTest
- public getSqrtResultForDenormInput
- public getTargetConstantFromLoad
- public getTargetNodeName
- public getTypeForExtReturn
- public getVectorElementPointer
- public getVectorSubVecPointer
- public initializeSplitCSR
- public insertCopiesSplitCSR
- public isConstFalseVal
- public isConstTrueVal
- public isDesirableToCommuteWithShift
- public isDesirableToCommuteXorWithShift
- public isDesirableToTransformToIntegerOp
- public isExtendedTrueVal
- public isGAPlusOffset
- public isGuaranteedNotToBeUndefOrPoisonForTargetNode
- public isInTailCallPosition
- public isIndexingLegal
- public isKnownNeverNaNForTargetNode
- public isOffsetFoldingLegal
- public isPositionIndependent
- public isReassocProfitable
- public isSDNodeAlwaysUniform
- public isSDNodeSourceOfDivergence
- public isSplatValueForTargetNode
- public isTargetCanonicalConstantNode
- public isTypeDesirableForOp
- public isUsedByReturnOnly
- public joinRegisterPartsIntoValue
- public lowerAtomicLoadAsLoadSDNode
- public lowerAtomicStoreAsStoreSDNode
- public lowerCmpEqZeroToCtlzSrl
- public makeLibCall
- public mayBeEmittedAsTailCall
- public parametersInCSRMatch
- public prepareVolatileOrAtomicLoad
- public scalarizeVectorLoad
- public scalarizeVectorStore
- public shouldSimplifyDemandedVectorElts
- public shouldSplitFunctionArgumentsAsLittleEndian
- public softenSetCCOperands
- public softenSetCCOperands
- public splitValueIntoRegisterParts
- public supportSplitCSR
- public supportSwiftError
- public targetShrinkDemandedConstant
- public unwrapAddress
- public useLoadStackGuardNode
- public verifyReturnAddressArgumentIsConstant
Inherited from TargetLoweringBase:
- protected AddPromotedToType
- public InstructionOpcodeToISD
- public ShouldShrinkFPConstant
- protected addBypassSlowDiv
- protected addRegisterClass
- public aggressivelyPreferBuildVectorSources
- public alignLoopsWithOptSize
- public allowTruncateForTailCall
- public allowsMemoryAccess
- public allowsMemoryAccess
- public allowsMemoryAccess
- public allowsMemoryAccessForAlignment
- public allowsMemoryAccessForAlignment
- public allowsMisalignedMemoryAccesses
- public allowsMisalignedMemoryAccesses
- public areJTsAllowed
- public canCombineStoreAndExtract
- public canCombineTruncStore
- public canMergeStoresTo
- public canOpTrap
- protected computeRegisterProperties
- public convertSelectOfConstantsToMath
- public convertSetCCLogicToBitwiseLogic
- public decomposeMulByConstant
- public emitAtomicCmpXchgNoStoreLLBalance
- public emitBitTestAtomicRMWIntrinsic
- public emitLeadingFence
- public emitLoadLinked
- public emitMaskedAtomicCmpXchgIntrinsic
- public emitMaskedAtomicRMWIntrinsic
- protected emitPatchPoint
- public emitStoreConditional
- public emitTrailingFence
- public enableAggressiveFMAFusion
- public enableAggressiveFMAFusion
- public enableExtLdPromotion
- public fallBackToDAGISel
- public finalizeLowering
- protected findRepresentativeClass
- public generateFMAsInMachineCombiner
- public getABIAlignmentForCallingConv
- public getAddrModeArguments
- public getAsmOperandValueType
- public getAtomicMemOperandFlags
- public getBooleanContents
- public getBooleanContents
- public getByValTypeAlignment
- public getBypassSlowDivWidths
- public getCmpLibcallCC
- public getCmpLibcallReturnType
- public getCondCodeAction
- public getCustomCtpopCost
- public getCustomOperationAction
- protected getDefaultSafeStackPointerLocation
- public getDivRefinementSteps
- public getExceptionPointerRegister
- public getExceptionSelectorRegister
- public getExtendForAtomicCmpSwapArg
- public getExtendForAtomicOps
- public getExtendForContent
- public getFenceOperandTy
- public getFixedPointOperationAction
- public getFrameIndexTy
- public getGatherAllAliasesMaxDepth
- public getIRStackGuard
- public getIndexedLoadAction
- public getIndexedMaskedLoadAction
- public getIndexedMaskedStoreAction
- public getIndexedStoreAction
- public getLibcallCallingConv
- public getLibcallName
- public getLoadExtAction
- public getLoadMemOperandFlags
- public getMaxAtomicSizeInBitsSupported
- public getMaxExpandSizeMemcmp
- public getMaxGluedStoresPerMemcpy
- public getMaxPermittedBytesForAlignment
- public getMaxStoresPerMemcpy
- public getMaxStoresPerMemmove
- public getMaxStoresPerMemset
- public getMaxSupportedInterleaveFactor
- public getMaximumJumpTableSize
- public getMemValueType
- public getMinCmpXchgSizeInBits
- public getMinFunctionAlignment
- public getMinStackArgumentAlignment
- public getMinimumJumpTableDensity
- public getMinimumJumpTableEntries
- public getNumRegisters
- public getNumRegistersForCallingConv
- public getOperationAction
- public getOptimalMemOpLLT
- public getOptimalMemOpType
- public getPointerMemTy
- public getPointerTy
- public getPrefFunctionAlignment
- public getPrefLoopAlignment
- public getPreferredShiftAmountTy
- public getPreferredSwitchConditionType
- public getPreferredVectorAction
- public getProgramPointerTy
- public getRecipEstimateDivEnabled
- public getRecipEstimateSqrtEnabled
- public getRegClassFor
- public getRegisterType
- public getRegisterType
- public getRegisterTypeForCallingConv
- public getRepRegClassCostFor
- public getRepRegClassFor
- public getSDagStackGuard
- public getSSPStackGuardCheck
- public getSafeStackPointerLocation
- public getScalarShiftAmountTy
- public getScalingFactorCost
- public getSchedulingPreference
- public getSchedulingPreference
- public getSetCCResultType
- public getShiftAmountTy
- public getSimpleValueType
- public getSqrtRefinementSteps
- public getStackPointerRegisterToSaveRestore
- public getStackProbeSymbolName
- public getStoreMemOperandFlags
- public getStrictFPOperationAction
- public getTargetMMOFlags
- public getTargetMachine
- public getTgtMemIntrinsic
- public getTruncStoreAction
- public getTypeAction
- public getTypeAction
- public getTypeLegalizationCost
- public getTypeToExpandTo
- public getTypeToPromoteTo
- public getTypeToTransformTo
- public getVPExplicitVectorLengthTy
- public getVaListSizeInBits
- public getValueType
- public getValueTypeActions
- public getVectorIdxTy
- public getVectorTypeBreakdown
- public getVectorTypeBreakdownForCallingConv
- public hasAndNot
- public hasAndNotCompare
- public hasBigEndianPartOrdering
- public hasBitPreservingFPLogic
- public hasBitTest
- public hasExtractBitsInsn
- public hasFastEqualityCompare
- public hasInlineStackProbe
- public hasMultipleConditionRegisters
- public hasPairedLoad
- public hasStackProbeSymbol
- public hasStandaloneRem
- public hasTargetDAGCombine
- public hasVectorBlend
- protected initActions
- public insertSSPDeclarations
- public isBeneficialToExpandPowI
- public isBinOp
- public isCheapToSpeculateCtlz
- public isCheapToSpeculateCttz
- public isCommutativeBinOp
- public isCondCodeLegal
- public isCondCodeLegalOrCustom
- public isConstantUnsignedBitfieldExtractLegal
- public isCtlzFast
- public isEqualityCmpFoldedWithSignedCmp
- public isExtFree
- protected isExtFreeImpl
- public isExtLoad
- public isExtractSubvectorCheap
- public isExtractVecEltCheap
- public isFAbsFree
- public isFMADLegal
- public isFMADLegal
- public isFMAFasterThanFMulAndFAdd
- public isFMAFasterThanFMulAndFAdd
- public isFMAFasterThanFMulAndFAdd
- public isFNegFree
- public isFPExtFoldable
- public isFPExtFoldable
- public isFPExtFree
- public isFPImmLegal
- public isFreeAddrSpaceCast
- public isFsqrtCheap
- public isIndexedLoadLegal
- public isIndexedMaskedLoadLegal
- public isIndexedMaskedStoreLegal
- public isIndexedStoreLegal
- public isIntDivCheap
- public isJumpExpensive
- public isJumpTableRelative
- public isLegalAddImmediate
- public isLegalAddressingMode
- public isLegalICmpImmediate
- protected isLegalRC
- public isLegalStoreImmediate
- public isLoadBitCastBeneficial
- public isLoadExtLegal
- public isLoadExtLegalOrCustom
- public isMaskAndCmp0FoldingBeneficial
- public isMulAddWithConstProfitable
- public isMultiStoresCheaperThanBitsMerge
- public isNarrowingProfitable
- public isOperationCustom
- public isOperationExpand
- public isOperationLegal
- public isOperationLegalOrCustom
- public isOperationLegalOrCustomOrPromote
- public isOperationLegalOrPromote
- public isPredictableSelectExpensive
- public isProfitableToCombineMinNumMaxNum
- public isProfitableToHoist
- public isSExtCheaperThanZExt
- public isSafeMemOpType
- public isSelectSupported
- public isShuffleMaskLegal
- public isSlowDivBypassed
- public isStoreBitCastBeneficial
- public isStrictFPEnabled
- public isSuitableForBitTests
- public isSuitableForJumpTable
- public isSupportedFixedPointOperation
- public isTruncStoreLegal
- public isTruncStoreLegalOrCustom
- public isTruncateFree
- public isTruncateFree
- public isTruncateFree
- public isTypeLegal
- public isVScaleKnownToBeAPowerOfTwo
- public isVectorClearMaskLegal
- public isVectorLoadExtDesirable
- public isVectorShiftByScalarCheap
- public isZExtFree
- public isZExtFree
- public isZExtFree
- public isZExtFree
- public lowerIdempotentRMWIntoFencedLoad
- public lowerInterleavedLoad
- public lowerInterleavedStore
- public markLibCallAttributes
- public mergeStoresAfterLegalization
- public needsFixedCatchObjects
- public preferIncOfAddToSubOfNot
- public preferZeroCompareBranch
- public promoteTargetBoolean
- public rangeFitsInWord
- public reduceSelectOfFPConstantLoads
- public requiresUniformRegister
- protected setBooleanContents
- protected setBooleanContents
- protected setBooleanVectorContents
- public setCmpLibcallCC
- protected setCondCodeAction
- protected setCondCodeAction
- protected setHasExtractBitsInsn
- protected setHasMultipleConditionRegisters
- protected setIndexedLoadAction
- protected setIndexedLoadAction
- protected setIndexedMaskedLoadAction
- protected setIndexedMaskedStoreAction
- protected setIndexedStoreAction
- protected setIndexedStoreAction
- protected setJumpIsExpensive
- public setLibcallCallingConv
- public setLibcallName
- public setLibcallName
- protected setLoadExtAction
- protected setLoadExtAction
- protected setLoadExtAction
- protected setMaxAtomicSizeInBitsSupported
- protected setMaxBytesForAlignment
- protected setMaximumJumpTableSize
- protected setMinCmpXchgSizeInBits
- protected setMinFunctionAlignment
- protected setMinStackArgumentAlignment
- protected setMinimumJumpTableEntries
- protected setOperationAction
- protected setOperationAction
- protected setOperationAction
- protected setOperationPromotedToType
- protected setPrefFunctionAlignment
- protected setPrefLoopAlignment
- protected setSchedulingPreference
- protected setStackPointerRegisterToSaveRestore
- protected setSupportsUnalignedAtomics
- protected setTargetDAGCombine
- protected setTruncStoreAction
- public shouldAlignPointerArgs
- public shouldAvoidTransformToShift
- public shouldCastAtomicLoadInIR
- public shouldCastAtomicRMWIInIR
- public shouldCastAtomicStoreInIR
- public shouldConsiderGEPOffsetSplit
- public shouldConvertConstantLoadToIntImm
- public shouldConvertFpToSat
- public shouldConvertPhiType
- public shouldConvertSplatType
- public shouldExpandAtomicCmpXchgInIR
- public shouldExpandAtomicLoadInIR
- public shouldExpandAtomicRMWInIR
- public shouldExpandAtomicStoreInIR
- public shouldExpandBuildVectorWithShuffles
- public shouldExpandGetActiveLaneMask
- public shouldExpandShift
- public shouldExtendGSIndex
- public shouldExtendTypeInLibCall
- public shouldFoldConstantShiftPairToMask
- public shouldFoldMaskToVariableShiftPair
- public shouldFoldSelectWithIdentityConstant
- public shouldFormOverflowOp
- public shouldInsertFencesForAtomic
- public shouldKeepZExtForFP16Conv
- public shouldLocalize
- public shouldNormalizeToSelectSequence
- public shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd
- public shouldReduceLoadWidth
- public shouldRemoveExtendFromGSIndex
- public shouldScalarizeBinop
- public shouldSignExtendTypeInLibCall
- public shouldSinkOperands
- public shouldSplatInsEltVarIndex
- public shouldTransformSignedTruncationCheck
- public shouldUseStrictFP_TO_INT
- public signExtendConstant
- public softPromoteHalfType
- public storeOfVectorConstantIsCheap
- public supportsUnalignedAtomics
- public useSoftFloat
- public useStackGuardXorFP
Methods
¶std::pair<SDValue, SDValue> BuildFILD(
llvm::EVT DstVT,
llvm::EVT SrcVT,
const llvm::SDLoc& DL,
llvm::SDValue Chain,
llvm::SDValue Pointer,
llvm::MachinePointerInfo PtrInfo,
llvm::Align Alignment,
llvm::SelectionDAG& DAG) const
std::pair<SDValue, SDValue> BuildFILD(
llvm::EVT DstVT,
llvm::EVT SrcVT,
const llvm::SDLoc& DL,
llvm::SDValue Chain,
llvm::SDValue Pointer,
llvm::MachinePointerInfo PtrInfo,
llvm::Align Alignment,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1437
Parameters
- llvm::EVT DstVT
- llvm::EVT SrcVT
- const llvm::SDLoc& DL
- llvm::SDValue Chain
- llvm::SDValue Pointer
- llvm::MachinePointerInfo PtrInfo
- llvm::Align Alignment
- llvm::SelectionDAG& DAG
¶llvm::SDValue BuildSDIVPow2(
llvm::SDNode* N,
const llvm::APInt& Divisor,
llvm::SelectionDAG& DAG,
SmallVectorImpl<llvm::SDNode*>& Created) const
llvm::SDValue BuildSDIVPow2(
llvm::SDNode* N,
const llvm::APInt& Divisor,
llvm::SelectionDAG& DAG,
SmallVectorImpl<llvm::SDNode*>& Created) const
Description
Targets may override this function to provide custom SDIV lowering for power-of-2 denominators. If the target returns an empty SDValue, LLVM assumes SDIV is expensive and replaces it with a series of other integer operations.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1739
Parameters
- llvm::SDNode* N
- const llvm::APInt& Divisor
- llvm::SelectionDAG& DAG
- SmallVectorImpl<llvm::SDNode*>& Created
¶bool CanLowerReturn(
CallingConv::ID CallConv,
llvm::MachineFunction& MF,
bool isVarArg,
const SmallVectorImpl<ISD::OutputArg>& Outs,
llvm::LLVMContext& Context) const
bool CanLowerReturn(
CallingConv::ID CallConv,
llvm::MachineFunction& MF,
bool isVarArg,
const SmallVectorImpl<ISD::OutputArg>& Outs,
llvm::LLVMContext& Context) const
Description
This hook should be implemented to check whether the return values described by the Outs array can fit into the return registers. If false is returned, an sret-demotion is performed.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1643
Parameters
- CallingConv::ID CallConv
- llvm::MachineFunction& MF
- bool isVarArg
- const SmallVectorImpl<ISD::OutputArg>& Outs
- llvm::LLVMContext& Context
¶unsigned int ComputeNumSignBitsForTargetNode(
llvm::SDValue Op,
const llvm::APInt& DemandedElts,
const llvm::SelectionDAG& DAG,
unsigned int Depth) const
unsigned int ComputeNumSignBitsForTargetNode(
llvm::SDValue Op,
const llvm::APInt& DemandedElts,
const llvm::SelectionDAG& DAG,
unsigned int Depth) const
Description
Determine the number of bits in the operation that are sign bits.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1130
Parameters
- llvm::SDValue Op
- const llvm::APInt& DemandedElts
- const llvm::SelectionDAG& DAG
- unsigned int Depth
¶llvm::MachineBasicBlock*
EmitInstrWithCustomInserter(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* MBB) const
llvm::MachineBasicBlock*
EmitInstrWithCustomInserter(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* MBB) const
Description
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' flag. These instructions are special in various ways, which require special support to insert. The specified MachineInstr is created but not inserted into any basic blocks, and this method is called to expand it into a sequence of instructions, potentially also creating new basic blocks and control flow. As long as the returned basic block is different (i.e., we created a new one), the custom inserter is free to modify the rest of \p MBB.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1021
Parameters
¶llvm::MachineBasicBlock*
EmitLoweredCascadedSelect(
llvm::MachineInstr& MI1,
llvm::MachineInstr& MI2,
llvm::MachineBasicBlock* BB) const
llvm::MachineBasicBlock*
EmitLoweredCascadedSelect(
llvm::MachineInstr& MI1,
llvm::MachineInstr& MI2,
llvm::MachineBasicBlock* BB) const
Description
Utility function to emit the xmm reg save portion of va_start.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1678
Parameters
¶llvm::MachineBasicBlock* EmitLoweredCatchRet(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* BB) const
llvm::MachineBasicBlock* EmitLoweredCatchRet(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* BB) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1685
Parameters
¶llvm::MachineBasicBlock* EmitLoweredIndirectThunk(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* BB) const
llvm::MachineBasicBlock* EmitLoweredIndirectThunk(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* BB) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1700
Parameters
¶llvm::MachineBasicBlock* EmitLoweredProbedAlloca(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* BB) const
llvm::MachineBasicBlock* EmitLoweredProbedAlloca(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* BB) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1691
Parameters
¶llvm::MachineBasicBlock* EmitLoweredSegAlloca(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* BB) const
llvm::MachineBasicBlock* EmitLoweredSegAlloca(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* BB) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1688
Parameters
¶llvm::MachineBasicBlock* EmitLoweredSelect(
llvm::MachineInstr& I,
llvm::MachineBasicBlock* BB) const
llvm::MachineBasicBlock* EmitLoweredSelect(
llvm::MachineInstr& I,
llvm::MachineBasicBlock* BB) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1682
Parameters
¶llvm::MachineBasicBlock* EmitLoweredTLSAddr(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* BB) const
llvm::MachineBasicBlock* EmitLoweredTLSAddr(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* BB) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1694
Parameters
¶llvm::MachineBasicBlock* EmitLoweredTLSCall(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* BB) const
llvm::MachineBasicBlock* EmitLoweredTLSCall(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* BB) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1697
Parameters
¶llvm::MachineBasicBlock* EmitSjLjDispatchBlock(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* MBB) const
llvm::MachineBasicBlock* EmitSjLjDispatchBlock(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* MBB) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1715
Parameters
¶llvm::SDValue EmitTailCallLoadRetAddr(
llvm::SelectionDAG& DAG,
llvm::SDValue& OutRetAddr,
llvm::SDValue Chain,
bool IsTailCall,
bool Is64Bit,
int FPDiff,
const llvm::SDLoc& dl) const
llvm::SDValue EmitTailCallLoadRetAddr(
llvm::SelectionDAG& DAG,
llvm::SDValue& OutRetAddr,
llvm::SDValue Chain,
bool IsTailCall,
bool Is64Bit,
int FPDiff,
const llvm::SDLoc& dl) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1535
Parameters
- llvm::SelectionDAG& DAG
- llvm::SDValue& OutRetAddr
- llvm::SDValue Chain
- bool IsTailCall
- bool Is64Bit
- int FPDiff
- const llvm::SDLoc& dl
¶llvm::MachineBasicBlock*
EmitVAARGWithCustomInserter(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* MBB) const
llvm::MachineBasicBlock*
EmitVAARGWithCustomInserter(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* MBB) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1675
Parameters
¶bool ExpandInlineAsm(llvm::CallInst* CI) const
bool ExpandInlineAsm(llvm::CallInst* CI) const
Description
This hook allows the target to expand an inline asm call to be explicit llvm code if it wants to. This is useful for turning simple inline asms into LLVM intrinsics, which gives the compiler more information about the behavior of the code.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1182
Parameters
- llvm::CallInst* CI
¶llvm::SDValue FP_TO_INTHelper(
llvm::SDValue Op,
llvm::SelectionDAG& DAG,
bool IsSigned,
llvm::SDValue& Chain) const
llvm::SDValue FP_TO_INTHelper(
llvm::SDValue Op,
llvm::SelectionDAG& DAG,
bool IsSigned,
llvm::SDValue& Chain) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1545
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
- bool IsSigned
- llvm::SDValue& Chain
¶unsigned int GetAlignedArgumentStackSize(
unsigned int StackSize,
llvm::SelectionDAG& DAG) const
unsigned int GetAlignedArgumentStackSize(
unsigned int StackSize,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1540
Parameters
- unsigned int StackSize
- llvm::SelectionDAG& DAG
¶bool IsDesirableToPromoteOp(llvm::SDValue Op,
llvm::EVT& PVT) const
bool IsDesirableToPromoteOp(llvm::SDValue Op,
llvm::EVT& PVT) const
Description
Return true if the target has native support for the specified value type and it is 'desirable' to use the type. e.g. On x86 i16 is legal, but undesirable since i16 instruction encodings are longer and some i16 instructions are slow.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1010
Parameters
- llvm::SDValue Op
- llvm::EVT& PVT
¶bool IsEligibleForTailCallOptimization(
llvm::SDValue Callee,
CallingConv::ID CalleeCC,
bool IsCalleeStackStructRet,
bool isVarArg,
llvm::Type* RetTy,
const SmallVectorImpl<ISD::OutputArg>& Outs,
const SmallVectorImpl<llvm::SDValue>& OutVals,
const SmallVectorImpl<ISD::InputArg>& Ins,
llvm::SelectionDAG& DAG) const
bool IsEligibleForTailCallOptimization(
llvm::SDValue Callee,
CallingConv::ID CalleeCC,
bool IsCalleeStackStructRet,
bool isVarArg,
llvm::Type* RetTy,
const SmallVectorImpl<ISD::OutputArg>& Outs,
const SmallVectorImpl<llvm::SDValue>& OutVals,
const SmallVectorImpl<ISD::InputArg>& Ins,
llvm::SelectionDAG& DAG) const
Description
Check whether the call is eligible for tail call optimization. Targets that want to do tail call optimization should implement this function.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1530
Parameters
- llvm::SDValue Callee
- CallingConv::ID CalleeCC
- bool IsCalleeStackStructRet
- bool isVarArg
- llvm::Type* RetTy
- const SmallVectorImpl<ISD::OutputArg>& Outs
- const SmallVectorImpl<llvm::SDValue>& OutVals
- const SmallVectorImpl<ISD::InputArg>& Ins
- llvm::SelectionDAG& DAG
¶llvm::SDValue LRINT_LLRINTHelper(
llvm::SDNode* N,
llvm::SelectionDAG& DAG) const
llvm::SDValue LRINT_LLRINTHelper(
llvm::SDNode* N,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1547
Parameters
- llvm::SDNode* N
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerADDROFRETURNADDR(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerADDROFRETURNADDR(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1582
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶void LowerAsmOperandForConstraint(
llvm::SDValue Op,
std::string& Constraint,
std::vector<SDValue>& Ops,
llvm::SelectionDAG& DAG) const
void LowerAsmOperandForConstraint(
llvm::SDValue Op,
std::string& Constraint,
std::vector<SDValue>& Ops,
llvm::SelectionDAG& DAG) const
Description
Lower the specified operand into the Ops vector. If it is invalid, don't add anything to Ops. If hasMemory is true it means one of the asm constraint of the inline asm instruction being processed is 'm'.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1197
Parameters
- llvm::SDValue Op
- std::string& Constraint
- std::vector<SDValue>& Ops
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerAsmOutputForConstraint(
llvm::SDValue& Chain,
llvm::SDValue& Flag,
const llvm::SDLoc& DL,
const llvm::TargetLowering::AsmOperandInfo&
Constraint,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerAsmOutputForConstraint(
llvm::SDValue& Chain,
llvm::SDValue& Flag,
const llvm::SDLoc& DL,
const llvm::TargetLowering::AsmOperandInfo&
Constraint,
llvm::SelectionDAG& DAG) const
Description
Handle Lowering flag assembly outputs.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1210
Parameters
- llvm::SDValue& Chain
- llvm::SDValue& Flag
- const llvm::SDLoc& DL
- const llvm::TargetLowering::AsmOperandInfo& Constraint
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerBRCOND(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerBRCOND(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1576
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerBUILD_VECTOR(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerBUILD_VECTOR(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1549
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerBlockAddress(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerBlockAddress(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1557
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerCall(
llvm::TargetLowering::CallLoweringInfo& CLI,
SmallVectorImpl<llvm::SDValue>& InVals) const
llvm::SDValue LowerCall(
llvm::TargetLowering::CallLoweringInfo& CLI,
SmallVectorImpl<llvm::SDValue>& InVals) const
Description
This hook must be implemented to lower calls into the specified DAG. The outgoing arguments to the call are described by the Outs array, and the values to be returned by the call are described by the Ins array. The implementation should fill in the InVals array with legal-type return values from the call, and return the resulting token chain value.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1608
Parameters
- llvm::TargetLowering::CallLoweringInfo& CLI
- SmallVectorImpl<llvm::SDValue>& InVals
¶llvm::SDValue LowerCallResult(
llvm::SDValue Chain,
llvm::SDValue InFlag,
CallingConv::ID CallConv,
bool isVarArg,
const SmallVectorImpl<ISD::InputArg>& Ins,
const llvm::SDLoc& dl,
llvm::SelectionDAG& DAG,
SmallVectorImpl<llvm::SDValue>& InVals,
uint32_t* RegMask) const
llvm::SDValue LowerCallResult(
llvm::SDValue Chain,
llvm::SDValue InFlag,
CallingConv::ID CallConv,
bool isVarArg,
const SmallVectorImpl<ISD::InputArg>& Ins,
const llvm::SDLoc& dl,
llvm::SelectionDAG& DAG,
SmallVectorImpl<llvm::SDValue>& InVals,
uint32_t* RegMask) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1510
Parameters
- llvm::SDValue Chain
- llvm::SDValue InFlag
- CallingConv::ID CallConv
- bool isVarArg
- const SmallVectorImpl<ISD::InputArg>& Ins
- const llvm::SDLoc& dl
- llvm::SelectionDAG& DAG
- SmallVectorImpl<llvm::SDValue>& InVals
- uint32_t* RegMask
¶llvm::SDValue LowerConstantPool(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerConstantPool(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1556
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶const llvm::MCExpr* LowerCustomJumpTableEntry(
const llvm::MachineJumpTableInfo* MJTI,
const llvm::MachineBasicBlock* MBB,
unsigned int uid,
llvm::MCContext& Ctx) const
const llvm::MCExpr* LowerCustomJumpTableEntry(
const llvm::MachineJumpTableInfo* MJTI,
const llvm::MachineBasicBlock* MBB,
unsigned int uid,
llvm::MCContext& Ctx) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:953
Parameters
- const llvm::MachineJumpTableInfo* MJTI
- const llvm::MachineBasicBlock* MBB
- unsigned int uid
- llvm::MCContext& Ctx
¶llvm::SDValue LowerDYNAMIC_STACKALLOC(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerDYNAMIC_STACKALLOC(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1578
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerEH_RETURN(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerEH_RETURN(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1585
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerEXTRACT_VECTOR_ELT(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerEXTRACT_VECTOR_ELT(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1551
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerExternalSymbol(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerExternalSymbol(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1560
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerFLT_ROUNDS_(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerFLT_ROUNDS_(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1590
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerFP_EXTEND(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerFP_EXTEND(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1599
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerFP_ROUND(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerFP_ROUND(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1600
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerFP_TO_BF16(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerFP_TO_BF16(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1601
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerFP_TO_INT(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerFP_TO_INT(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1570
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerFP_TO_INT_SAT(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerFP_TO_INT_SAT(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1571
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerFRAMEADDR(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerFRAMEADDR(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1583
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerFRAME_TO_ARGS_OFFSET(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerFRAME_TO_ARGS_OFFSET(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1584
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerFormalArguments(
llvm::SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
const SmallVectorImpl<ISD::InputArg>& Ins,
const llvm::SDLoc& dl,
llvm::SelectionDAG& DAG,
SmallVectorImpl<llvm::SDValue>& InVals) const
llvm::SDValue LowerFormalArguments(
llvm::SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
const SmallVectorImpl<ISD::InputArg>& Ins,
const llvm::SDLoc& dl,
llvm::SelectionDAG& DAG,
SmallVectorImpl<llvm::SDValue>& InVals) const
Description
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array, into the specified DAG. The implementation should fill in the InVals array with legal-type argument values, and return the resulting token chain value.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1604
Parameters
- llvm::SDValue Chain
- CallingConv::ID CallConv
- bool isVarArg
- const SmallVectorImpl<ISD::InputArg>& Ins
- const llvm::SDLoc& dl
- llvm::SelectionDAG& DAG
- SmallVectorImpl<llvm::SDValue>& InVals
¶llvm::SDValue LowerGC_TRANSITION(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerGC_TRANSITION(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1596
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerGlobalAddress(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerGlobalAddress(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1558
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerGlobalOrExternal(
llvm::SDValue Op,
llvm::SelectionDAG& DAG,
bool ForCall) const
llvm::SDValue LowerGlobalOrExternal(
llvm::SDValue Op,
llvm::SelectionDAG& DAG,
bool ForCall) const
Description
Creates target global address or external symbol nodes for calls or other uses.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1564
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
- bool ForCall
¶llvm::SDValue LowerGlobalTLSAddress(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerGlobalTLSAddress(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1559
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerINIT_TRAMPOLINE(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerINIT_TRAMPOLINE(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1589
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerINSERT_VECTOR_ELT(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerINSERT_VECTOR_ELT(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1552
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerINTRINSIC_WO_CHAIN(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerINTRINSIC_WO_CHAIN(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1597
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerJumpTable(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerJumpTable(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1577
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerLRINT_LLRINT(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerLRINT_LLRINT(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1572
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerMemArgument(
llvm::SDValue Chain,
CallingConv::ID CallConv,
const SmallVectorImpl<ISD::InputArg>& ArgInfo,
const llvm::SDLoc& dl,
llvm::SelectionDAG& DAG,
const llvm::CCValAssign& VA,
llvm::MachineFrameInfo& MFI,
unsigned int i) const
llvm::SDValue LowerMemArgument(
llvm::SDValue Chain,
CallingConv::ID CallConv,
const SmallVectorImpl<ISD::InputArg>& ArgInfo,
const llvm::SDLoc& dl,
llvm::SelectionDAG& DAG,
const llvm::CCValAssign& VA,
llvm::MachineFrameInfo& MFI,
unsigned int i) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1516
Parameters
- llvm::SDValue Chain
- CallingConv::ID CallConv
- const SmallVectorImpl<ISD::InputArg>& ArgInfo
- const llvm::SDLoc& dl
- llvm::SelectionDAG& DAG
- const llvm::CCValAssign& VA
- llvm::MachineFrameInfo& MFI
- unsigned int i
¶llvm::SDValue LowerMemOpCallTo(
llvm::SDValue Chain,
llvm::SDValue StackPtr,
llvm::SDValue Arg,
const llvm::SDLoc& dl,
llvm::SelectionDAG& DAG,
const llvm::CCValAssign& VA,
ISD::ArgFlagsTy Flags,
bool isByval) const
llvm::SDValue LowerMemOpCallTo(
llvm::SDValue Chain,
llvm::SDValue StackPtr,
llvm::SDValue Arg,
const llvm::SDLoc& dl,
llvm::SelectionDAG& DAG,
const llvm::CCValAssign& VA,
ISD::ArgFlagsTy Flags,
bool isByval) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1521
Parameters
- llvm::SDValue Chain
- llvm::SDValue StackPtr
- llvm::SDValue Arg
- const llvm::SDLoc& dl
- llvm::SelectionDAG& DAG
- const llvm::CCValAssign& VA
- ISD::ArgFlagsTy Flags
- bool isByval
¶llvm::SDValue LowerOperation(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerOperation(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Description
Provide custom lowering hooks for some operations.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:990
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerRETURNADDR(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerRETURNADDR(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1581
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerReturn(
llvm::SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
const SmallVectorImpl<ISD::OutputArg>& Outs,
const SmallVectorImpl<llvm::SDValue>& OutVals,
const llvm::SDLoc& dl,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerReturn(
llvm::SDValue Chain,
CallingConv::ID CallConv,
bool isVarArg,
const SmallVectorImpl<ISD::OutputArg>& Outs,
const SmallVectorImpl<llvm::SDValue>& OutVals,
const llvm::SDLoc& dl,
llvm::SelectionDAG& DAG) const
Description
This hook must be implemented to lower outgoing return values, described by the Outs array, into the specified DAG. The implementation should return the resulting token chain value.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1611
Parameters
- llvm::SDValue Chain
- CallingConv::ID CallConv
- bool isVarArg
- const SmallVectorImpl<ISD::OutputArg>& Outs
- const SmallVectorImpl<llvm::SDValue>& OutVals
- const llvm::SDLoc& dl
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerSELECT(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerSELECT(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1575
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerSETCC(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerSETCC(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1573
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerSETCCCARRY(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerSETCCCARRY(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1574
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerSET_ROUNDING(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerSET_ROUNDING(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1591
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerSINT_TO_FP(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerSINT_TO_FP(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1567
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerTRUNCATE(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerTRUNCATE(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1569
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerUINT_TO_FP(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerUINT_TO_FP(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1568
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerVAARG(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerVAARG(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1580
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerVASTART(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerVASTART(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1579
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerVSELECT(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerVSELECT(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1550
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerWin64_FP_TO_INT128(
llvm::SDValue Op,
llvm::SelectionDAG& DAG,
llvm::SDValue& Chain) const
llvm::SDValue LowerWin64_FP_TO_INT128(
llvm::SDValue Op,
llvm::SelectionDAG& DAG,
llvm::SDValue& Chain) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1593
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
- llvm::SDValue& Chain
¶llvm::SDValue LowerWin64_INT128_TO_FP(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerWin64_INT128_TO_FP(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1595
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue LowerWin64_i128OP(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue LowerWin64_i128OP(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1592
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶const char* LowerXConstraint(
llvm::EVT ConstraintVT) const
const char* LowerXConstraint(
llvm::EVT ConstraintVT) const
Description
Try to replace an X constraint, which matches anything, with another that has more specific requirements based on the type of the corresponding operand. This returns null if there is no replacement to make.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1192
Parameters
- llvm::EVT ConstraintVT
¶llvm::SDValue PerformDAGCombine(
llvm::SDNode* N,
llvm::TargetLowering::DAGCombinerInfo& DCI)
const
llvm::SDValue PerformDAGCombine(
llvm::SDNode* N,
llvm::TargetLowering::DAGCombinerInfo& DCI)
const
Description
This method will be invoked for all target nodes and for any target-independent nodes that the target has registered with invoke it for. The semantics are as follows: Return Value: SDValue.Val == 0 - No change was made SDValue.Val == N - N was replaced, is dead, and is already handled. otherwise - N should be replaced by the returned Operand. In addition, methods provided by DAGCombinerInfo may be used to perform more complex transformations.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:998
Parameters
¶void ReplaceNodeResults(
llvm::SDNode* N,
SmallVectorImpl<llvm::SDValue>& Results,
llvm::SelectionDAG& DAG) const
void ReplaceNodeResults(
llvm::SDNode* N,
SmallVectorImpl<llvm::SDValue>& Results,
llvm::SelectionDAG& DAG) const
Description
Replace the results of node with an illegal result type with new values built out of custom code.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:995
Parameters
- llvm::SDNode* N
- SmallVectorImpl<llvm::SDValue>& Results
- llvm::SelectionDAG& DAG
¶void SetupEntryBlockForSjLj(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* MBB,
llvm::MachineBasicBlock* DispatchBB,
int FI) const
void SetupEntryBlockForSjLj(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* MBB,
llvm::MachineBasicBlock* DispatchBB,
int FI) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1670
Parameters
- llvm::MachineInstr& MI
- llvm::MachineBasicBlock* MBB
- llvm::MachineBasicBlock* DispatchBB
- int FI
¶bool ShouldShrinkFPConstant(llvm::EVT VT) const
bool ShouldShrinkFPConstant(llvm::EVT VT) const
Description
If true, then instruction selection should seek to shrink the FP constant of the specified type to a smaller type in order to save space and / or reduce runtime.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1338
Parameters
- llvm::EVT VT
¶bool SimplifyDemandedBitsForTargetNode(
llvm::SDValue Op,
const llvm::APInt& DemandedBits,
const llvm::APInt& DemandedElts,
llvm::KnownBits& Known,
llvm::TargetLowering::TargetLoweringOpt& TLO,
unsigned int Depth) const
bool SimplifyDemandedBitsForTargetNode(
llvm::SDValue Op,
const llvm::APInt& DemandedBits,
const llvm::APInt& DemandedElts,
llvm::KnownBits& Known,
llvm::TargetLowering::TargetLoweringOpt& TLO,
unsigned int Depth) const
Description
Attempt to simplify any target nodes based on the demanded bits/elts, returning true on success. Otherwise, analyze the expression and return a mask of KnownOne and KnownZero bits for the expression (used to simplify the caller). The KnownZero/One bits may only be accurate for those bits in the Demanded masks.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1148
Parameters
- llvm::SDValue Op
- const llvm::APInt& DemandedBits
- const llvm::APInt& DemandedElts
- llvm::KnownBits& Known
- llvm::TargetLowering::TargetLoweringOpt& TLO
- unsigned int Depth
¶bool SimplifyDemandedVectorEltsForTargetNode(
llvm::SDValue Op,
const llvm::APInt& DemandedElts,
llvm::APInt& KnownUndef,
llvm::APInt& KnownZero,
llvm::TargetLowering::TargetLoweringOpt& TLO,
unsigned int Depth) const
bool SimplifyDemandedVectorEltsForTargetNode(
llvm::SDValue Op,
const llvm::APInt& DemandedElts,
llvm::APInt& KnownUndef,
llvm::APInt& KnownZero,
llvm::TargetLowering::TargetLoweringOpt& TLO,
unsigned int Depth) const
Description
Attempt to simplify any target nodes based on the demanded vector elements, returning true on success. Otherwise, analyze the expression and return a mask of KnownUndef and KnownZero elements for the expression (used to simplify the caller). The KnownUndef/Zero elements may only be accurate for those bits in the DemandedMask.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1135
Parameters
- llvm::SDValue Op
- const llvm::APInt& DemandedElts
- llvm::APInt& KnownUndef
- llvm::APInt& KnownZero
- llvm::TargetLowering::TargetLoweringOpt& TLO
- unsigned int Depth
¶bool SimplifyDemandedVectorEltsForTargetShuffle(
llvm::SDValue Op,
const llvm::APInt& DemandedElts,
unsigned int MaskIndex,
llvm::TargetLowering::TargetLoweringOpt& TLO,
unsigned int Depth) const
bool SimplifyDemandedVectorEltsForTargetShuffle(
llvm::SDValue Op,
const llvm::APInt& DemandedElts,
unsigned int MaskIndex,
llvm::TargetLowering::TargetLoweringOpt& TLO,
unsigned int Depth) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1142
Parameters
- llvm::SDValue Op
- const llvm::APInt& DemandedElts
- unsigned int MaskIndex
- llvm::TargetLowering::TargetLoweringOpt& TLO
- unsigned int Depth
¶llvm::SDValue
SimplifyMultipleUseDemandedBitsForTargetNode(
llvm::SDValue Op,
const llvm::APInt& DemandedBits,
const llvm::APInt& DemandedElts,
llvm::SelectionDAG& DAG,
unsigned int Depth) const
llvm::SDValue
SimplifyMultipleUseDemandedBitsForTargetNode(
llvm::SDValue Op,
const llvm::APInt& DemandedBits,
const llvm::APInt& DemandedElts,
llvm::SelectionDAG& DAG,
unsigned int Depth) const
Description
More limited version of SimplifyDemandedBits that can be used to "look through" ops that don't contribute to the DemandedBits/DemandedElts - bitwise ops etc.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1155
Parameters
- llvm::SDValue Op
- const llvm::APInt& DemandedBits
- const llvm::APInt& DemandedElts
- llvm::SelectionDAG& DAG
- unsigned int Depth
¶X86TargetLowering(
const llvm::X86TargetMachine& TM,
const llvm::X86Subtarget& STI)
X86TargetLowering(
const llvm::X86TargetMachine& TM,
const llvm::X86Subtarget& STI)
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:939
Parameters
- const llvm::X86TargetMachine& TM
- const llvm::X86Subtarget& STI
¶void addLegalFPImmediate(const llvm::APFloat& Imm)
void addLegalFPImmediate(const llvm::APFloat& Imm)
Description
Indicate that this x86 target can instruction select the specified FP immediate natively.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1506
Parameters
- const llvm::APFloat& Imm
¶bool allowTruncateForTailCall(
llvm::Type* Ty1,
llvm::Type* Ty2) const
bool allowTruncateForTailCall(
llvm::Type* Ty1,
llvm::Type* Ty2) const
Description
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail position. Typically this means that both results would be assigned to the same register or stack slot, but it could mean the target performs adequate checks of its own before proceeding with the tail call. Targets must return false when FromTy < = ToTy.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1268
Parameters
- llvm::Type* Ty1
- llvm::Type* Ty2
¶bool allowsMisalignedMemoryAccesses(
llvm::EVT VT,
unsigned int AS,
llvm::Align Alignment,
MachineMemOperand::Flags Flags,
bool* Fast) const
bool allowsMisalignedMemoryAccesses(
llvm::EVT VT,
unsigned int AS,
llvm::Align Alignment,
MachineMemOperand::Flags Flags,
bool* Fast) const
Description
Returns true if the target allows unaligned memory accesses of the specified type. Returns whether it is "fast" in the last argument.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:984
Parameters
- llvm::EVT VT
- unsigned int AS
- llvm::Align Alignment
- MachineMemOperand::Flags Flags
- bool* Fast
¶bool areJTsAllowed(const llvm::Function* Fn) const
bool areJTsAllowed(const llvm::Function* Fn) const
Description
Returns true if lowering to a jump table is allowed.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1330
Parameters
- const llvm::Function* Fn
¶bool canMergeStoresTo(
unsigned int AddressSpace,
llvm::EVT MemVT,
const llvm::MachineFunction& MF) const
bool canMergeStoresTo(
unsigned int AddressSpace,
llvm::EVT MemVT,
const llvm::MachineFunction& MF) const
Description
Returns if it's reasonable to merge stores to MemVT size.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1033
Parameters
- unsigned int AddressSpace
- llvm::EVT MemVT
- const llvm::MachineFunction& MF
¶unsigned int combineRepeatedFPDivisors() const
unsigned int combineRepeatedFPDivisors() const
Description
Reassociate floating point divisions into multiply by reciprocal.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1737
¶void computeKnownBitsForTargetNode(
const llvm::SDValue Op,
llvm::KnownBits& Known,
const llvm::APInt& DemandedElts,
const llvm::SelectionDAG& DAG,
unsigned int Depth = 0) const
void computeKnownBitsForTargetNode(
const llvm::SDValue Op,
llvm::KnownBits& Known,
const llvm::APInt& DemandedElts,
const llvm::SelectionDAG& DAG,
unsigned int Depth = 0) const
Description
Determine which of the bits specified in Mask are known to be either zero or one and return them in the KnownZero/KnownOne bitsets.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1123
Parameters
- const llvm::SDValue Op
- llvm::KnownBits& Known
- const llvm::APInt& DemandedElts
- const llvm::SelectionDAG& DAG
- unsigned int Depth = 0
¶bool convertSelectOfConstantsToMath(
llvm::EVT VT) const
bool convertSelectOfConstantsToMath(
llvm::EVT VT) const
Description
Return true if a select of constants (select Cond, C1, C2) should be transformed into simple math ops with the condition value. For example: select Cond, C1, C1-1 --> add (zext Cond), C1-1
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1356
Parameters
- llvm::EVT VT
¶bool convertSetCCLogicToBitwiseLogic(
llvm::EVT VT) const
bool convertSetCCLogicToBitwiseLogic(
llvm::EVT VT) const
Description
Use bitwise logic to make pairs of compares more efficient. For example: and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0 This should be true when it takes more than one instruction to lower setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1106
Parameters
- llvm::EVT VT
¶llvm::FastISel* createFastISel(
llvm::FunctionLoweringInfo& funcInfo,
const llvm::TargetLibraryInfo* libInfo) const
llvm::FastISel* createFastISel(
llvm::FunctionLoweringInfo& funcInfo,
const llvm::TargetLibraryInfo* libInfo) const
Description
This method returns a target specific FastISel object, or null if the target does not support "fast" ISel.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1416
Parameters
- llvm::FunctionLoweringInfo& funcInfo
- const llvm::TargetLibraryInfo* libInfo
¶bool decomposeMulByConstant(
llvm::LLVMContext& Context,
llvm::EVT VT,
llvm::SDValue C) const
bool decomposeMulByConstant(
llvm::LLVMContext& Context,
llvm::EVT VT,
llvm::SDValue C) const
Description
Return true if it is profitable to transform an integer multiplication-by-constant into simpler operations like shifts and adds. This may be true if the target does not directly support the multiplication operation for the specified type or the sequence of simpler ops is faster than the multiply.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1358
Parameters
- llvm::LLVMContext& Context
- llvm::EVT VT
- llvm::SDValue C
¶void emitBitTestAtomicRMWIntrinsic(
llvm::AtomicRMWInst* AI) const
void emitBitTestAtomicRMWIntrinsic(
llvm::AtomicRMWInst* AI) const
Description
Perform a bit test atomicrmw using a target-specific intrinsic. This represents the combined bit test intrinsic which will be lowered at a late stage by the backend.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1658
Parameters
¶llvm::MachineBasicBlock* emitEHSjLjLongJmp(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* MBB) const
llvm::MachineBasicBlock* emitEHSjLjLongJmp(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* MBB) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1709
Parameters
¶llvm::MachineBasicBlock* emitEHSjLjSetJmp(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* MBB) const
llvm::MachineBasicBlock* emitEHSjLjSetJmp(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* MBB) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1703
Parameters
¶llvm::SDValue emitFlagsForSetcc(
llvm::SDValue Op0,
llvm::SDValue Op1,
ISD::CondCode CC,
const llvm::SDLoc& dl,
llvm::SelectionDAG& DAG,
llvm::SDValue& X86CC) const
llvm::SDValue emitFlagsForSetcc(
llvm::SDValue Op0,
llvm::SDValue Op1,
ISD::CondCode CC,
const llvm::SDLoc& dl,
llvm::SelectionDAG& DAG,
llvm::SDValue& X86CC) const
Description
Emit flags for the given setcc condition and operands. Also returns the corresponding X86 condition code constant in X86CC.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1720
Parameters
- llvm::SDValue Op0
- llvm::SDValue Op1
- ISD::CondCode CC
- const llvm::SDLoc& dl
- llvm::SelectionDAG& DAG
- llvm::SDValue& X86CC
¶llvm::MachineBasicBlock*
emitLongJmpShadowStackFix(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* MBB) const
llvm::MachineBasicBlock*
emitLongJmpShadowStackFix(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* MBB) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1712
Parameters
¶void emitSetJmpShadowStackFix(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* MBB) const
void emitSetJmpShadowStackFix(
llvm::MachineInstr& MI,
llvm::MachineBasicBlock* MBB) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1706
Parameters
¶llvm::SDValue emitStackGuardXorFP(
llvm::SelectionDAG& DAG,
llvm::SDValue Val,
const llvm::SDLoc& DL) const
llvm::SDValue emitStackGuardXorFP(
llvm::SelectionDAG& DAG,
llvm::SDValue Val,
const llvm::SDLoc& DL) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1428
Parameters
- llvm::SelectionDAG& DAG
- llvm::SDValue Val
- const llvm::SDLoc& DL
¶llvm::SDValue expandIndirectJTBranch(
const llvm::SDLoc& dl,
llvm::SDValue Value,
llvm::SDValue Addr,
llvm::SelectionDAG& DAG) const
llvm::SDValue expandIndirectJTBranch(
const llvm::SDLoc& dl,
llvm::SDValue Value,
llvm::SDValue Addr,
llvm::SelectionDAG& DAG) const
Description
Expands target specific indirect branch for the case of JumpTable expanasion.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1485
Parameters
- const llvm::SDLoc& dl
- llvm::SDValue Value
- llvm::SDValue Addr
- llvm::SelectionDAG& DAG
¶std::pair<const TargetRegisterClass*, uint8_t>
findRepresentativeClass(
const llvm::TargetRegisterInfo* TRI,
llvm::MVT VT) const
std::pair<const TargetRegisterClass*, uint8_t>
findRepresentativeClass(
const llvm::TargetRegisterInfo* TRI,
llvm::MVT VT) const
Description
Return the largest legal super-reg register class of the register class for the specified type and its associated "cost".
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1493
Parameters
- const llvm::TargetRegisterInfo* TRI
- llvm::MVT VT
¶unsigned int getAddressSpace() const
unsigned int getAddressSpace() const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1543
¶uint64_t getByValTypeAlignment(
llvm::Type* Ty,
const llvm::DataLayout& DL) const
uint64_t getByValTypeAlignment(
llvm::Type* Ty,
const llvm::DataLayout& DL) const
Description
Return the desired alignment for ByVal aggregate function arguments in the caller parameter area. For X86, aggregates that contains are placed at 16-byte boundaries while the rest are at 4-byte boundaries.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:968
Parameters
- llvm::Type* Ty
- const llvm::DataLayout& DL
¶const char* getClearCacheBuiltinName() const
const char* getClearCacheBuiltinName() const
Description
Intel processors have a unified instruction and data cache
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1395
¶llvm::TargetLowering::ConstraintType
getConstraintType(
llvm::StringRef Constraint) const
llvm::TargetLowering::ConstraintType
getConstraintType(
llvm::StringRef Constraint) const
Description
Given a constraint, return the type of constraint it is for this target.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1184
Parameters
- llvm::StringRef Constraint
¶llvm::Register getExceptionPointerRegister(
const llvm::Constant* PersonalityFn) const
llvm::Register getExceptionPointerRegister(
const llvm::Constant* PersonalityFn) const
Description
If a physical register, this returns the register that receives the exception address on entry to an EH pad.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1405
Parameters
- const llvm::Constant* PersonalityFn
¶llvm::Register getExceptionSelectorRegister(
const llvm::Constant* PersonalityFn) const
llvm::Register getExceptionSelectorRegister(
const llvm::Constant* PersonalityFn) const
Description
If a physical register, this returns the register that receives the exception typeid on entry to a landing pad.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1410
Parameters
- const llvm::Constant* PersonalityFn
¶unsigned int getGlobalWrapperKind(
const llvm::GlobalValue* GV = nullptr,
const unsigned char OpFlags = 0) const
unsigned int getGlobalWrapperKind(
const llvm::GlobalValue* GV = nullptr,
const unsigned char OpFlags = 0) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1554
Parameters
- const llvm::GlobalValue* GV = nullptr
- const unsigned char OpFlags = 0
¶llvm::Value* getIRStackGuard(
llvm::IRBuilderBase& IRB) const
llvm::Value* getIRStackGuard(
llvm::IRBuilderBase& IRB) const
Description
If the target has a standard location for the stack protector cookie, returns the address of that location. Otherwise, returns nullptr.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1421
Parameters
- llvm::IRBuilderBase& IRB
¶unsigned int getInlineAsmMemConstraint(
llvm::StringRef ConstraintCode) const
unsigned int getInlineAsmMemConstraint(
llvm::StringRef ConstraintCode) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1203
Parameters
- llvm::StringRef ConstraintCode
¶unsigned int getJumpTableEncoding() const
unsigned int getJumpTableEncoding() const
Description
Return the entry encoding for a jump table in the current function. The returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:942
¶unsigned int getMaxSupportedInterleaveFactor()
const
unsigned int getMaxSupportedInterleaveFactor()
const
Description
Get the maximum supported factor for interleaved memory accesses. Default to be the minimum interleave factor: 2.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1471
¶llvm::SDValue getNegatedExpression(
llvm::SDValue Op,
llvm::SelectionDAG& DAG,
bool LegalOperations,
bool ForCodeSize,
llvm::TargetLoweringBase::NegatibleCost& Cost,
unsigned int Depth) const
llvm::SDValue getNegatedExpression(
llvm::SDValue Op,
llvm::SelectionDAG& DAG,
bool LegalOperations,
bool ForCodeSize,
llvm::TargetLoweringBase::NegatibleCost& Cost,
unsigned int Depth) const
Description
Return the newly negated expression if the cost is not expensive and set the cost in \p Cost to indicate that if it is cheaper or neutral to do the negation.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1015
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
- bool LegalOperations
- bool ForCodeSize
- llvm::TargetLoweringBase::NegatibleCost& Cost
- unsigned int Depth
¶unsigned int getNumRegistersForCallingConv(
llvm::LLVMContext& Context,
CallingConv::ID CC,
llvm::EVT VT) const
unsigned int getNumRegistersForCallingConv(
llvm::LLVMContext& Context,
CallingConv::ID CC,
llvm::EVT VT) const
Description
Certain targets require unusual breakdowns of certain types. For MIPS, this occurs when a vector type is used, as vector are passed through the integer register set.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1451
Parameters
- llvm::LLVMContext& Context
- CallingConv::ID CC
- llvm::EVT VT
¶llvm::EVT getOptimalMemOpType(
const llvm::MemOp& Op,
const llvm::AttributeList& FuncAttributes)
const
llvm::EVT getOptimalMemOpType(
const llvm::MemOp& Op,
const llvm::AttributeList& FuncAttributes)
const
Description
Returns the target specific optimal type for load and store operations as a result of memset, memcpy, and memmove lowering. It returns EVT::Other if the type should be determined using generic target-independent logic.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:971
Parameters
- const llvm::MemOp& Op
- const llvm::AttributeList& FuncAttributes
¶llvm::SDValue getPICJumpTableRelocBase(
llvm::SDValue Table,
llvm::SelectionDAG& DAG) const
llvm::SDValue getPICJumpTableRelocBase(
llvm::SDValue Table,
llvm::SelectionDAG& DAG) const
Description
Returns relocation base for the given PIC jumptable.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:958
Parameters
- llvm::SDValue Table
- llvm::SelectionDAG& DAG
¶const llvm::MCExpr* getPICJumpTableRelocBaseExpr(
const llvm::MachineFunction* MF,
unsigned int JTI,
llvm::MCContext& Ctx) const
const llvm::MCExpr* getPICJumpTableRelocBaseExpr(
const llvm::MachineFunction* MF,
unsigned int JTI,
llvm::MCContext& Ctx) const
Description
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase, but as an MCExpr.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:961
Parameters
- const llvm::MachineFunction* MF
- unsigned int JTI
- llvm::MCContext& Ctx
¶llvm::Align getPrefLoopAlignment(
llvm::MachineLoop* ML) const
llvm::Align getPrefLoopAlignment(
llvm::MachineLoop* ML) const
Description
Return the preferred loop alignment.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1489
Parameters
¶llvm::MVT getPreferredSwitchConditionType(
llvm::LLVMContext& Context,
llvm::EVT ConditionVT) const
llvm::MVT getPreferredSwitchConditionType(
llvm::LLVMContext& Context,
llvm::EVT ConditionVT) const
Description
Returns preferred type for switch condition.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1332
Parameters
- llvm::LLVMContext& Context
- llvm::EVT ConditionVT
¶llvm::TargetLoweringBase::LegalizeTypeAction
getPreferredVectorAction(llvm::MVT VT) const
llvm::TargetLoweringBase::LegalizeTypeAction
getPreferredVectorAction(llvm::MVT VT) const
Description
Customize the preferred legalization strategy for certain types.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1444
Parameters
- llvm::MVT VT
¶llvm::SDValue getRecipEstimate(
llvm::SDValue Op,
llvm::SelectionDAG& DAG,
int Enabled,
int& RefinementSteps) const
llvm::SDValue getRecipEstimate(
llvm::SDValue Op,
llvm::SelectionDAG& DAG,
int Enabled,
int& RefinementSteps) const
Description
Use rcp* to speed up fdiv calculations.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1733
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
- int Enabled
- int& RefinementSteps
¶std::pair<unsigned int,
const TargetRegisterClass*>
getRegForInlineAsmConstraint(
const llvm::TargetRegisterInfo* TRI,
llvm::StringRef Constraint,
llvm::MVT VT) const
std::pair<unsigned int,
const TargetRegisterClass*>
getRegForInlineAsmConstraint(
const llvm::TargetRegisterInfo* TRI,
llvm::StringRef Constraint,
llvm::MVT VT) const
Description
Given a physical register constraint (e.g. {edx}), return the register number and the register class for the register. This should only be used for C_Register constraints. On error, this returns a register number of 0.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1220
Parameters
- const llvm::TargetRegisterInfo* TRI
- llvm::StringRef Constraint
- llvm::MVT VT
¶llvm::Register getRegisterByName(
const char* RegName,
llvm::LLT VT,
const llvm::MachineFunction& MF) const
llvm::Register getRegisterByName(
const char* RegName,
llvm::LLT VT,
const llvm::MachineFunction& MF) const
Description
Return the register ID of the name passed in. Used by named register global variables extension. There is no target-independent behaviour so the default action is to bail.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1399
Parameters
- const char* RegName
- llvm::LLT VT
- const llvm::MachineFunction& MF
¶llvm::MVT getRegisterTypeForCallingConv(
llvm::LLVMContext& Context,
CallingConv::ID CC,
llvm::EVT VT) const
llvm::MVT getRegisterTypeForCallingConv(
llvm::LLVMContext& Context,
CallingConv::ID CC,
llvm::EVT VT) const
Description
Certain combinations of ABIs, Targets and features require that types are legal for some operations and not for other operations. For MIPS all vector types must be passed through the integer register set.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1448
Parameters
- llvm::LLVMContext& Context
- CallingConv::ID CC
- llvm::EVT VT
¶llvm::SDValue getReturnAddressFrameIndex(
llvm::SelectionDAG& DAG) const
llvm::SDValue getReturnAddressFrameIndex(
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1180
Parameters
- llvm::SelectionDAG& DAG
¶llvm::Value* getSDagStackGuard(
const llvm::Module& M) const
llvm::Value* getSDagStackGuard(
const llvm::Module& M) const
Description
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nullptr. Should be used only when getIRStackGuard returns nullptr.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1426
Parameters
- const llvm::Module& M
¶llvm::Function* getSSPStackGuardCheck(
const llvm::Module& M) const
llvm::Function* getSSPStackGuardCheck(
const llvm::Module& M) const
Description
If the target has a standard stack protection check function that performs validation and error handling, returns the function. Otherwise, returns nullptr. Must be previously inserted by insertSSPDeclarations. Should be used only when getIRStackGuard returns nullptr.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1427
Parameters
- const llvm::Module& M
¶llvm::Value* getSafeStackPointerLocation(
llvm::IRBuilderBase& IRB) const
llvm::Value* getSafeStackPointerLocation(
llvm::IRBuilderBase& IRB) const
Description
Return true if the target stores SafeStack pointer at a fixed offset in some non-standard address space, and populates the address space and offset as appropriate.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1435
Parameters
- llvm::IRBuilderBase& IRB
¶llvm::MVT getScalarShiftAmountTy(
const llvm::DataLayout&,
llvm::EVT VT) const
llvm::MVT getScalarShiftAmountTy(
const llvm::DataLayout&,
llvm::EVT VT) const
Description
Return the type to use for a scalar shift opcode, given the shifted amount type. Targets should return a legal type if the input type is legal. Targets can return a type that is too small if the input type is illegal.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:948
Parameters
- const llvm::DataLayout&
- llvm::EVT VT
¶llvm::InstructionCost getScalingFactorCost(
const llvm::DataLayout& DL,
const llvm::TargetLoweringBase::AddrMode& AM,
llvm::Type* Ty,
unsigned int AS) const
llvm::InstructionCost getScalingFactorCost(
const llvm::DataLayout& DL,
const llvm::TargetLoweringBase::AddrMode& AM,
llvm::Type* Ty,
unsigned int AS) const
Description
Return the cost of the scaling factor used in the addressing mode represented by AM for this target, for a load/store of the specified type. If the AM is supported, the return value must be >= 0. If the AM is not supported, it returns a negative value.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1248
Parameters
- const llvm::DataLayout& DL
- const llvm::TargetLoweringBase::AddrMode& AM
- llvm::Type* Ty
- unsigned int AS
¶const llvm::MCPhysReg* getScratchRegisters(
CallingConv::ID CC) const
const llvm::MCPhysReg* getScratchRegisters(
CallingConv::ID CC) const
Description
Returns a 0 terminated array of registers that can be safely used as scratch registers.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1648
Parameters
- CallingConv::ID CC
¶llvm::EVT getSetCCResultType(
const llvm::DataLayout& DL,
llvm::LLVMContext& Context,
llvm::EVT VT) const
llvm::EVT getSetCCResultType(
const llvm::DataLayout& DL,
llvm::LLVMContext& Context,
llvm::EVT VT) const
Description
Return the value type to use for ISD::SETCC.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1114
Parameters
- const llvm::DataLayout& DL
- llvm::LLVMContext& Context
- llvm::EVT VT
¶llvm::TargetLowering::ConstraintWeight
getSingleConstraintMatchWeight(
llvm::TargetLowering::AsmOperandInfo& info,
const char* constraint) const
llvm::TargetLowering::ConstraintWeight
getSingleConstraintMatchWeight(
llvm::TargetLowering::AsmOperandInfo& info,
const char* constraint) const
Description
Examine constraint string and operand type and determine a weight value. The operand object must already have been set up with the operand type.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1189
Parameters
- llvm::TargetLowering::AsmOperandInfo& info
- const char* constraint
¶llvm::SDValue getSqrtEstimate(
llvm::SDValue Op,
llvm::SelectionDAG& DAG,
int Enabled,
int& RefinementSteps,
bool& UseOneConstNR,
bool Reciprocal) const
llvm::SDValue getSqrtEstimate(
llvm::SDValue Op,
llvm::SelectionDAG& DAG,
int Enabled,
int& RefinementSteps,
bool& UseOneConstNR,
bool Reciprocal) const
Description
Use rsqrt* to speed up sqrt calculations.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1728
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
- int Enabled
- int& RefinementSteps
- bool& UseOneConstNR
- bool Reciprocal
¶unsigned int getStackProbeSize(
llvm::MachineFunction& MF) const
unsigned int getStackProbeSize(
llvm::MachineFunction& MF) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1467
Parameters
¶llvm::StringRef getStackProbeSymbolName(
llvm::MachineFunction& MF) const
llvm::StringRef getStackProbeSymbolName(
llvm::MachineFunction& MF) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1465
Parameters
¶const llvm::Constant* getTargetConstantFromLoad(
llvm::LoadSDNode* LD) const
const llvm::Constant* getTargetConstantFromLoad(
llvm::LoadSDNode* LD) const
Description
This method returns the constant pool value that will be loaded by LD. NOTE: You must check for implicit extensions of the constant by LD.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1176
Parameters
- llvm::LoadSDNode* LD
¶const char* getTargetNodeName(
unsigned int Opcode) const
const char* getTargetNodeName(
unsigned int Opcode) const
Description
This method returns the name of a target specific DAG node.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1025
Parameters
- unsigned int Opcode
¶bool getTgtMemIntrinsic(
llvm::TargetLoweringBase::IntrinsicInfo& Info,
const llvm::CallInst& I,
llvm::MachineFunction& MF,
unsigned int Intrinsic) const
bool getTgtMemIntrinsic(
llvm::TargetLoweringBase::IntrinsicInfo& Info,
const llvm::CallInst& I,
llvm::MachineFunction& MF,
unsigned int Intrinsic) const
Description
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (touches memory). If this is the case, it returns true and stores the intrinsic information into the IntrinsicInfo that was passed to the function.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1308
Parameters
- llvm::TargetLoweringBase::IntrinsicInfo& Info
- const llvm::CallInst& I
- llvm::MachineFunction& MF
- unsigned int Intrinsic
¶llvm::EVT getTypeForExtReturn(
llvm::LLVMContext& Context,
llvm::EVT VT,
ISD::NodeType ExtendKind) const
llvm::EVT getTypeForExtReturn(
llvm::LLVMContext& Context,
llvm::EVT VT,
ISD::NodeType ExtendKind) const
Description
Return the type that should be used to zero or sign extend a zeroext/signext integer return value. FIXME: Some C calling conventions require the return type to be promoted, but this is not true all the time, e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling conventions. The frontend should handle this and include all of the necessary information.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1640
Parameters
- llvm::LLVMContext& Context
- llvm::EVT VT
- ISD::NodeType ExtendKind
¶unsigned int getVectorTypeBreakdownForCallingConv(
llvm::LLVMContext& Context,
CallingConv::ID CC,
llvm::EVT VT,
llvm::EVT& IntermediateVT,
unsigned int& NumIntermediates,
llvm::MVT& RegisterVT) const
unsigned int getVectorTypeBreakdownForCallingConv(
llvm::LLVMContext& Context,
CallingConv::ID CC,
llvm::EVT VT,
llvm::EVT& IntermediateVT,
unsigned int& NumIntermediates,
llvm::MVT& RegisterVT) const
Description
Certain targets such as MIPS require that some types such as vectors are always broken down into scalars in some contexts. This occurs even if the vector type is legal.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1455
Parameters
- llvm::LLVMContext& Context
- CallingConv::ID CC
- llvm::EVT VT
- llvm::EVT& IntermediateVT
- unsigned int& NumIntermediates
- llvm::MVT& RegisterVT
¶bool hasAndNot(llvm::SDValue Y) const
bool hasAndNot(llvm::SDValue Y) const
Description
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify select or other instructions.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1064
Parameters
¶bool hasAndNotCompare(llvm::SDValue Y) const
bool hasAndNotCompare(llvm::SDValue Y) const
Description
Return true if the target should transform: (X & Y) == Y ---> (~X & Y) == 0 (X & Y) != Y ---> (~X & Y) != 0 This may be profitable if the target has a bitwise and-not operation that sets comparison flags. A target may want to limit the transformation based on the type of Y or if Y is a constant. Note that the transform will not occur if Y is known to be a power-of-2 because a mask and compare of a single bit can be handled by inverting the predicate, for example: (X & 8) == 8 ---> (X & 8) != 0
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1062
Parameters
¶bool hasBitPreservingFPLogic(llvm::EVT VT) const
bool hasBitPreservingFPLogic(llvm::EVT VT) const
Description
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floating-point operation. This should be set to true if the target has IEEE-754-compliant fabs/fneg operations for the input type.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1042
Parameters
- llvm::EVT VT
¶bool hasBitTest(llvm::SDValue X,
llvm::SDValue Y) const
bool hasBitTest(llvm::SDValue X,
llvm::SDValue Y) const
Description
Return true if the target has a bit-test instruction: (X & (1 < < Y)) ==/!= 0 This knowledge can be used to prevent breaking the pattern, or creating it if it could be recognized.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1066
Parameters
¶llvm::MVT hasFastEqualityCompare(
unsigned int NumBits) const
llvm::MVT hasFastEqualityCompare(
unsigned int NumBits) const
Description
Vector-sized comparisons are fast using PCMPEQ + PMOVMSK or PTEST.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1111
Parameters
- unsigned int NumBits
¶bool hasInlineStackProbe(
llvm::MachineFunction& MF) const
bool hasInlineStackProbe(
llvm::MachineFunction& MF) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1464
Parameters
¶bool hasStackProbeSymbol(
llvm::MachineFunction& MF) const
bool hasStackProbeSymbol(
llvm::MachineFunction& MF) const
Description
Returns the name of the symbol used to emit stack probes or the empty string if not applicable.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1463
Parameters
¶bool hasVectorBlend() const
bool hasVectorBlend() const
Description
Return true if the target has a vector blend instruction.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1469
¶void initializeSplitCSR(
llvm::MachineBasicBlock* Entry) const
void initializeSplitCSR(
llvm::MachineBasicBlock* Entry) const
Description
Perform necessary initialization to handle a subset of CSRs explicitly via copies. This function is called at the beginning of instruction selection.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1620
Parameters
- llvm::MachineBasicBlock* Entry
¶void insertCopiesSplitCSR(
llvm::MachineBasicBlock* Entry,
const SmallVectorImpl<
llvm::MachineBasicBlock*>& Exits) const
void insertCopiesSplitCSR(
llvm::MachineBasicBlock* Entry,
const SmallVectorImpl<
llvm::MachineBasicBlock*>& Exits) const
Description
Insert explicit copies in entry and exit blocks. We copy a subset of CSRs to virtual registers in the entry block, and copy them back to physical registers in the exit blocks. This function is called at the end of instruction selection.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1621
Parameters
- llvm::MachineBasicBlock* Entry
- const SmallVectorImpl<llvm::MachineBasicBlock*>& Exits
¶void insertSSPDeclarations(llvm::Module& M) const
void insertSSPDeclarations(llvm::Module& M) const
Description
Inserts necessary declarations for SSP (stack protection) purpose. Should be used only when getIRStackGuard returns nullptr.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1425
Parameters
- llvm::Module& M
¶bool isBinOp(unsigned int Opcode) const
bool isBinOp(unsigned int Opcode) const
Description
Add x86-specific opcodes to the default list.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1257
Parameters
- unsigned int Opcode
¶bool isCheapToSpeculateCtlz() const
bool isCheapToSpeculateCtlz() const
Description
Return true if it is cheap to speculate a call to intrinsic ctlz.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1038
¶bool isCheapToSpeculateCttz() const
bool isCheapToSpeculateCttz() const
Description
Return true if it is cheap to speculate a call to intrinsic cttz.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1036
¶bool isCommutativeBinOp(unsigned int Opcode) const
bool isCommutativeBinOp(unsigned int Opcode) const
Description
Returns true if the opcode is a commutative binary operation.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1260
Parameters
- unsigned int Opcode
¶bool isCtlzFast() const
bool isCtlzFast() const
Description
Return true if ctlz instruction is fast.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1040
¶bool isExtractSubvectorCheap(
llvm::EVT ResVT,
llvm::EVT SrcVT,
unsigned int Index) const
bool isExtractSubvectorCheap(
llvm::EVT ResVT,
llvm::EVT SrcVT,
unsigned int Index) const
Description
Return true if EXTRACT_SUBVECTOR is cheap for this result type with this index.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1363
Parameters
¶bool isExtractVecEltCheap(
llvm::EVT VT,
unsigned int Index) const
bool isExtractVecEltCheap(
llvm::EVT VT,
unsigned int Index) const
Description
Extract of a scalar FP value from index 0 of a vector is free.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1372
Parameters
- llvm::EVT VT
- unsigned int Index
¶bool isFMAFasterThanFMulAndFAdd(
const llvm::MachineFunction& MF,
llvm::EVT VT) const
bool isFMAFasterThanFMulAndFAdd(
const llvm::MachineFunction& MF,
llvm::EVT VT) const
Description
Return true if an FMA operation is faster than a pair of fmul and fadd instructions. fmuladd intrinsics will be expanded to FMAs when this method returns true, otherwise fmuladd is expanded to fmul + fadd.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1293
Parameters
- const llvm::MachineFunction& MF
- llvm::EVT VT
¶bool isFPImmLegal(const llvm::APFloat& Imm,
llvm::EVT VT,
bool ForCodeSize) const
bool isFPImmLegal(const llvm::APFloat& Imm,
llvm::EVT VT,
bool ForCodeSize) const
Description
Returns true if the target can instruction select the specified FP immediate natively. If false, the legalizer will materialize the FP immediate as a load from a constant pool.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1315
Parameters
- const llvm::APFloat& Imm
- llvm::EVT VT
- bool ForCodeSize
¶bool isFsqrtCheap(llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
bool isFsqrtCheap(llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Description
Check if replacement of SQRT with RSQRT should be disabled.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1725
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶bool isIntDivCheap(llvm::EVT VT,
llvm::AttributeList Attr) const
bool isIntDivCheap(llvm::EVT VT,
llvm::AttributeList Attr) const
Description
Return true if integer divide is usually cheaper than a sequence of several shifts, adds, and multiplies for this target. The definition of "cheaper" may depend on whether we're optimizing for speed or for size.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1459
Parameters
- llvm::EVT VT
- llvm::AttributeList Attr
¶bool isLegalAddImmediate(int64_t Imm) const
bool isLegalAddImmediate(int64_t Imm) const
Description
Return true if the specified immediate is legal add immediate, that is the target has add instructions which can add a register and the immediate without having to materialize the immediate into a register.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1239
Parameters
- int64_t Imm
¶bool isLegalAddressingMode(
const llvm::DataLayout& DL,
const llvm::TargetLoweringBase::AddrMode& AM,
llvm::Type* Ty,
unsigned int AS,
llvm::Instruction* I = nullptr) const
bool isLegalAddressingMode(
const llvm::DataLayout& DL,
const llvm::TargetLoweringBase::AddrMode& AM,
llvm::Type* Ty,
unsigned int AS,
llvm::Instruction* I = nullptr) const
Description
Return true if the addressing mode represented by AM is legal for this target, for a load/store of the specified type.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1225
Parameters
- const llvm::DataLayout& DL
- const llvm::TargetLoweringBase::AddrMode& AM
- llvm::Type* Ty
- unsigned int AS
- llvm::Instruction* I = nullptr
¶bool isLegalICmpImmediate(int64_t Imm) const
bool isLegalICmpImmediate(int64_t Imm) const
Description
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructions which can compare a register against the immediate without having to materialize the immediate into a register.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1233
Parameters
- int64_t Imm
¶bool isLegalStoreImmediate(int64_t Imm) const
bool isLegalStoreImmediate(int64_t Imm) const
Description
Return true if the specified immediate is legal for the value input of a store instruction.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1241
Parameters
- int64_t Imm
¶bool isLoadBitCastBeneficial(
llvm::EVT LoadVT,
llvm::EVT BitcastVT,
const llvm::SelectionDAG& DAG,
const llvm::MachineMemOperand& MMO) const
bool isLoadBitCastBeneficial(
llvm::EVT LoadVT,
llvm::EVT BitcastVT,
const llvm::SelectionDAG& DAG,
const llvm::MachineMemOperand& MMO) const
Description
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently, casting the load to a smaller vector of larger types and loading is more efficient, however, this can be undone by optimizations in dag combiner.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1390
Parameters
- llvm::EVT LoadVT
- llvm::EVT BitcastVT
- const llvm::SelectionDAG& DAG
- const llvm::MachineMemOperand& MMO
¶bool isMaskAndCmp0FoldingBeneficial(
const llvm::Instruction& AndI) const
bool isMaskAndCmp0FoldingBeneficial(
const llvm::Instruction& AndI) const
Description
Return if the target supports combining a chain like: into a single machine instruction of a form like:
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1060
Parameters
- const llvm::Instruction& AndI
¶bool isMultiStoresCheaperThanBitsMerge(
llvm::EVT LTy,
llvm::EVT HTy) const
bool isMultiStoresCheaperThanBitsMerge(
llvm::EVT LTy,
llvm::EVT HTy) const
Description
Return true if it is cheaper to split the store of a merged int val from a pair of smaller values into multiple stores.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1044
Parameters
¶bool isNarrowingProfitable(llvm::EVT VT1,
llvm::EVT VT2) const
bool isNarrowingProfitable(llvm::EVT VT1,
llvm::EVT VT2) const
Description
Return true if it's profitable to narrow operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from i32 to i16.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1299
Parameters
¶bool isSafeMemOpType(llvm::MVT VT) const
bool isSafeMemOpType(llvm::MVT VT) const
Description
Returns true if it's safe to use load / store of the specified type to expand memcpy / memset inline. This is mostly true for all types except for some special cases. For example, on X86 targets without SSE2 f64 load / store are done with fldl / fstpl which also does type conversion. Note the specified type doesn't have to be legal as the hook is used before type legalization.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:980
Parameters
- llvm::MVT VT
¶bool isScalarFPTypeInSSEReg(llvm::EVT VT) const
bool isScalarFPTypeInSSEReg(llvm::EVT VT) const
Description
Return true if the specified scalar FP type is computed in an SSE register, not on the X87 floating point stack.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1347
Parameters
- llvm::EVT VT
¶bool isShuffleMaskLegal(ArrayRef<int> Mask,
llvm::EVT VT) const
bool isShuffleMaskLegal(ArrayRef<int> Mask,
llvm::EVT VT) const
Description
Targets can use this to indicate that they only support *some* VECTOR_SHUFFLE operations, those with specific masks. By default, if a target supports the VECTOR_SHUFFLE node, all mask values are assumed to be legal.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1322
Parameters
¶template <typename T>
bool isSoftFP16(T VT) const
template <typename T>
bool isSoftFP16(T VT) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1668
Templates
- T
Parameters
- T VT
¶bool isSplatValueForTargetNode(
llvm::SDValue Op,
const llvm::APInt& DemandedElts,
llvm::APInt& UndefElts,
unsigned int Depth) const
bool isSplatValueForTargetNode(
llvm::SDValue Op,
const llvm::APInt& DemandedElts,
llvm::APInt& UndefElts,
unsigned int Depth) const
Description
Return true if vector \p Op has the same value across all \p DemandedElts, indicating any elements which may be undef in the output \p UndefElts.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1159
Parameters
- llvm::SDValue Op
- const llvm::APInt& DemandedElts
- llvm::APInt& UndefElts
- unsigned int Depth
¶bool isTargetCanonicalConstantNode(
llvm::SDValue Op) const
bool isTargetCanonicalConstantNode(
llvm::SDValue Op) const
Description
Returns true if the given Opc is considered a canonical constant for the target, which should not be transformed back into a BUILD_VECTOR.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1163
Parameters
¶bool isTruncateFree(llvm::EVT VT1,
llvm::EVT VT2) const
bool isTruncateFree(llvm::EVT VT1,
llvm::EVT VT2) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1266
Parameters
¶bool isTruncateFree(llvm::Type* Ty1,
llvm::Type* Ty2) const
bool isTruncateFree(llvm::Type* Ty1,
llvm::Type* Ty2) const
Description
Return true if it's free to truncate a value of type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16 by referencing its sub-register AX.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1265
Parameters
- llvm::Type* Ty1
- llvm::Type* Ty2
¶bool isTypeDesirableForOp(unsigned int Opc,
llvm::EVT VT) const
bool isTypeDesirableForOp(unsigned int Opc,
llvm::EVT VT) const
Description
Return true if the target has native support for the specified value type and it is 'desirable' to use the type for the given node type. e.g. On x86 i16 is legal, but undesirable since i16 instruction encodings are longer and some i16 instructions are slow.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1004
Parameters
- unsigned int Opc
- llvm::EVT VT
¶bool isUsedByReturnOnly(
llvm::SDNode* N,
llvm::SDValue& Chain) const
bool isUsedByReturnOnly(
llvm::SDNode* N,
llvm::SDValue& Chain) const
Description
Return true if result of the specified node is used by a return node only. It also compute and return the input chain for the tail call. This is used to determine whether it is possible to codegen a libcall as tail call at legalization time.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1636
Parameters
- llvm::SDNode* N
- llvm::SDValue& Chain
¶bool isVectorClearMaskLegal(ArrayRef<int> Mask,
llvm::EVT VT) const
bool isVectorClearMaskLegal(ArrayRef<int> Mask,
llvm::EVT VT) const
Description
Similar to isShuffleMaskLegal. Targets can use this to indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a constant pool entry.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1327
Parameters
¶bool isVectorLoadExtDesirable(llvm::SDValue) const
bool isVectorLoadExtDesirable(llvm::SDValue) const
Description
Return true if folding a vector load into ExtVal (a sign, zero, or any extend node) is profitable.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1288
Parameters
¶bool isVectorShiftByScalarCheap(
llvm::Type* Ty) const
bool isVectorShiftByScalarCheap(
llvm::Type* Ty) const
Description
This is used to enable splatted operand transforms for vector shifts and vector funnel shifts.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1254
Parameters
- llvm::Type* Ty
¶bool isZExtFree(llvm::SDValue Val,
llvm::EVT VT2) const
bool isZExtFree(llvm::SDValue Val,
llvm::EVT VT2) const
Description
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicitly zero-extended such as ARM ldrb / ldrh or because it's folded such as X86 zero-extending loads).
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1280
Parameters
- llvm::SDValue Val
- llvm::EVT VT2
¶bool isZExtFree(llvm::EVT VT1,
llvm::EVT VT2) const
bool isZExtFree(llvm::EVT VT1,
llvm::EVT VT2) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1279
Parameters
¶bool isZExtFree(llvm::Type* Ty1,
llvm::Type* Ty2) const
bool isZExtFree(llvm::Type* Ty1,
llvm::Type* Ty2) const
Description
Return true if any actual instruction that defines a value of type Ty1 implicit zero-extends the value to Ty2 in the result register. This does not necessarily include registers defined in unknown ways, such as incoming arguments, or copies from unknown virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to truncate instructions. e.g. on x86-64, all instructions that define 32-bit values implicit zero-extend the result out to 64 bits.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1278
Parameters
- llvm::Type* Ty1
- llvm::Type* Ty2
¶llvm::SDValue joinRegisterPartsIntoValue(
llvm::SelectionDAG& DAG,
const llvm::SDLoc& DL,
const llvm::SDValue* Parts,
unsigned int NumParts,
llvm::MVT PartVT,
llvm::EVT ValueVT,
Optional<CallingConv::ID> CC) const
llvm::SDValue joinRegisterPartsIntoValue(
llvm::SelectionDAG& DAG,
const llvm::SDLoc& DL,
const llvm::SDValue* Parts,
unsigned int NumParts,
llvm::MVT PartVT,
llvm::EVT ValueVT,
Optional<CallingConv::ID> CC) const
Description
Target-specific combining of register parts into its original value
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1631
Parameters
- llvm::SelectionDAG& DAG
- const llvm::SDLoc& DL
- const llvm::SDValue* Parts
- unsigned int NumParts
- llvm::MVT PartVT
- llvm::EVT ValueVT
- Optional<CallingConv::ID> CC
¶bool lowerAtomicLoadAsLoadSDNode(
const llvm::LoadInst& LI) const
bool lowerAtomicLoadAsLoadSDNode(
const llvm::LoadInst& LI) const
Description
Should SelectionDAG lower an atomic load of the given kind as a normal LoadSDNode (as opposed to an AtomicSDNode)? NOTE: The intention is to eventually migrate all targets to the using LoadSDNodes, but porting is being done target at a time.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1664
Parameters
- const llvm::LoadInst& LI
¶bool lowerAtomicStoreAsStoreSDNode(
const llvm::StoreInst& SI) const
bool lowerAtomicStoreAsStoreSDNode(
const llvm::StoreInst& SI) const
Description
Should SelectionDAG lower an atomic store of the given kind as a normal StoreSDNode (as opposed to an AtomicSDNode)? NOTE: The intention is to eventually migrate all targets to the using StoreSDNodes, but porting is being done target at a time.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1663
Parameters
- const llvm::StoreInst& SI
¶llvm::SDValue lowerEH_SJLJ_LONGJMP(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue lowerEH_SJLJ_LONGJMP(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1587
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue lowerEH_SJLJ_SETJMP(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue lowerEH_SJLJ_SETJMP(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1586
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue lowerEH_SJLJ_SETUP_DISPATCH(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue lowerEH_SJLJ_SETUP_DISPATCH(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1588
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::SDValue lowerFaddFsub(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
llvm::SDValue lowerFaddFsub(
llvm::SDValue Op,
llvm::SelectionDAG& DAG) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1598
Parameters
- llvm::SDValue Op
- llvm::SelectionDAG& DAG
¶llvm::LoadInst* lowerIdempotentRMWIntoFencedLoad(
llvm::AtomicRMWInst* AI) const
llvm::LoadInst* lowerIdempotentRMWIntoFencedLoad(
llvm::AtomicRMWInst* AI) const
Description
On some platforms, an AtomicRMW that never actually modifies the value (such as fetch_add of 0) can be turned into a fence followed by an atomic load. This may sound useless, but it makes it possible for the processor to keep the cacheline shared, dramatically improving performance. And such idempotent RMWs are useful for implementing some kinds of locks, see for example (justification + benchmarks): http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf This method tries doing that transformation, returning the atomic load if it succeeds, and nullptr otherwise. If shouldExpandAtomicLoadInIR returns true on that load, it will undergo another round of expansion.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1661
Parameters
¶bool lowerInterleavedLoad(
llvm::LoadInst* LI,
ArrayRef<llvm::ShuffleVectorInst*> Shuffles,
ArrayRef<unsigned int> Indices,
unsigned int Factor) const
bool lowerInterleavedLoad(
llvm::LoadInst* LI,
ArrayRef<llvm::ShuffleVectorInst*> Shuffles,
ArrayRef<unsigned int> Indices,
unsigned int Factor) const
Description
Lower interleaved load(s) into target specific instructions/intrinsics.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1475
Parameters
- llvm::LoadInst* LI
- ArrayRef<llvm::ShuffleVectorInst*> Shuffles
- ArrayRef<unsigned int> Indices
- unsigned int Factor
¶bool lowerInterleavedStore(
llvm::StoreInst* SI,
llvm::ShuffleVectorInst* SVI,
unsigned int Factor) const
bool lowerInterleavedStore(
llvm::StoreInst* SI,
llvm::ShuffleVectorInst* SVI,
unsigned int Factor) const
Description
Lower interleaved store(s) into target specific instructions/intrinsics.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1482
Parameters
- llvm::StoreInst* SI
- llvm::ShuffleVectorInst* SVI
- unsigned int Factor
¶void markLibCallAttributes(
llvm::MachineFunction* MF,
unsigned int CC,
llvm::TargetLoweringBase::ArgListTy& Args)
const
void markLibCallAttributes(
llvm::MachineFunction* MF,
unsigned int CC,
llvm::TargetLoweringBase::ArgListTy& Args)
const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:945
Parameters
- llvm::MachineFunction* MF
- unsigned int CC
- llvm::TargetLoweringBase::ArgListTy& Args
¶bool mayBeEmittedAsTailCall(
const llvm::CallInst* CI) const
bool mayBeEmittedAsTailCall(
const llvm::CallInst* CI) const
Description
Return true if the target may be able emit the call instruction as a tail call. This is used by optimization passes to determine if it's profitable to duplicate return instructions to enable tailcall optimization.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1638
Parameters
- const llvm::CallInst* CI
¶bool mergeStoresAfterLegalization(
llvm::EVT MemVT) const
bool mergeStoresAfterLegalization(
llvm::EVT MemVT) const
Description
Do not merge vector stores after legalization because that may conflict with x86-specific store splitting optimizations.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1029
Parameters
- llvm::EVT MemVT
¶bool needsCmpXchgNb(llvm::Type* MemType) const
bool needsCmpXchgNb(llvm::Type* MemType) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1666
Parameters
- llvm::Type* MemType
¶bool needsFixedCatchObjects() const
bool needsFixedCatchObjects() const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1412
¶bool reduceSelectOfFPConstantLoads(
llvm::EVT CmpOpVT) const
bool reduceSelectOfFPConstantLoads(
llvm::EVT CmpOpVT) const
Description
Return true if it is profitable to convert a select of FP constants into a constant pool load whose address depends on the select condition. The parameter may be used to differentiate a select with FP compare from integer compare.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1354
Parameters
- llvm::EVT CmpOpVT
¶bool shouldConvertConstantLoadToIntImm(
const llvm::APInt& Imm,
llvm::Type* Ty) const
bool shouldConvertConstantLoadToIntImm(
const llvm::APInt& Imm,
llvm::Type* Ty) const
Description
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1351
Parameters
- const llvm::APInt& Imm
- llvm::Type* Ty
¶bool shouldConvertFpToSat(unsigned int Op,
llvm::EVT FPVT,
llvm::EVT VT) const
bool shouldConvertFpToSat(unsigned int Op,
llvm::EVT FPVT,
llvm::EVT VT) const
Description
Should we generate fp_to_si_sat and fp_to_ui_sat from type FPVT to type VT from min(max(fptoi)) saturation patterns.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1100
Parameters
¶bool shouldConvertPhiType(llvm::Type* From,
llvm::Type* To) const
bool shouldConvertPhiType(llvm::Type* From,
llvm::Type* To) const
Description
Given a set in interconnected phis of type 'From' that are loaded/stored or bitcast to type 'To', return true if the set should be converted to 'To'.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1284
Parameters
- llvm::Type* From
- llvm::Type* To
¶TargetLoweringBase::AtomicExpansionKind
shouldExpandAtomicLoadInIR(
llvm::LoadInst* LI) const
TargetLoweringBase::AtomicExpansionKind
shouldExpandAtomicLoadInIR(
llvm::LoadInst* LI) const
Description
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1651
Parameters
- llvm::LoadInst* LI
¶TargetLoweringBase::AtomicExpansionKind
shouldExpandAtomicRMWInIR(
llvm::AtomicRMWInst* AI) const
TargetLoweringBase::AtomicExpansionKind
shouldExpandAtomicRMWInIR(
llvm::AtomicRMWInst* AI) const
Description
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all. Default is to never expand.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1655
Parameters
¶TargetLoweringBase::AtomicExpansionKind
shouldExpandAtomicStoreInIR(
llvm::StoreInst* SI) const
TargetLoweringBase::AtomicExpansionKind
shouldExpandAtomicStoreInIR(
llvm::StoreInst* SI) const
Description
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into. For instance AtomicExpansionKind::Expand will try to use an atomicrmw xchg.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1653
Parameters
- llvm::StoreInst* SI
¶TargetLoweringBase::AtomicExpansionKind
shouldExpandLogicAtomicRMWInIR(
llvm::AtomicRMWInst* AI) const
TargetLoweringBase::AtomicExpansionKind
shouldExpandLogicAtomicRMWInIR(
llvm::AtomicRMWInst* AI) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1657
Parameters
¶bool shouldExpandShift(llvm::SelectionDAG& DAG,
llvm::SDNode* N) const
bool shouldExpandShift(llvm::SelectionDAG& DAG,
llvm::SDNode* N) const
Description
Return true if SHIFT instructions should be expanded to SHIFT_PARTS instructions, and false if a library call is preferred (e.g for code-size reasons).
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1096
Parameters
- llvm::SelectionDAG& DAG
- llvm::SDNode* N
¶bool shouldFoldConstantShiftPairToMask(
const llvm::SDNode* N,
llvm::CombineLevel Level) const
bool shouldFoldConstantShiftPairToMask(
const llvm::SDNode* N,
llvm::CombineLevel Level) const
Description
Return true if it is profitable to fold a pair of shifts into a mask. This is usually true on most targets. But some targets, like Thumb1, have immediate shift instructions, but no immediate "and" instruction; this makes the fold unprofitable.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1073
Parameters
- const llvm::SDNode* N
- llvm::CombineLevel Level
¶bool shouldFoldMaskToVariableShiftPair(
llvm::SDValue Y) const
bool shouldFoldMaskToVariableShiftPair(
llvm::SDValue Y) const
Description
There are two ways to clear extreme bits (either low or high): Mask: x & (-1 < < y) (the instcombine canonical form) Shifts: x >> y < < y Return true if the variant with 2 variable shifts is preferred. Return false if there is no preference.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1076
Parameters
¶bool shouldFoldSelectWithIdentityConstant(
unsigned int BinOpcode,
llvm::EVT VT) const
bool shouldFoldSelectWithIdentityConstant(
unsigned int BinOpcode,
llvm::EVT VT) const
Description
Return true if pulling a binary operation into a select with an identity constant is profitable. This is the inverse of an IR transform. Example: X + (Cond ? Y : 0) --> Cond ? (X + Y) : X
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1301
Parameters
- unsigned int BinOpcode
- llvm::EVT VT
¶bool shouldFormOverflowOp(unsigned int Opcode,
llvm::EVT VT,
bool MathUsed) const
bool shouldFormOverflowOp(unsigned int Opcode,
llvm::EVT VT,
bool MathUsed) const
Description
Overflow nodes should get combined/lowered to optimal instructions (they should allow eliminating explicit compares by getting flags from math ops).
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1380
Parameters
- unsigned int Opcode
- llvm::EVT VT
- bool MathUsed
¶bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
llvm::SDValue X,
llvm::ConstantSDNode* XC,
llvm::ConstantSDNode* CC,
llvm::SDValue Y,
unsigned int OldShiftOpcode,
unsigned int NewShiftOpcode,
llvm::SelectionDAG& DAG) const
bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
llvm::SDValue X,
llvm::ConstantSDNode* XC,
llvm::ConstantSDNode* CC,
llvm::SDValue Y,
unsigned int OldShiftOpcode,
unsigned int NewShiftOpcode,
llvm::SelectionDAG& DAG) const
Description
Given the pattern (X & (C l>>/ < < Y)) ==/!= 0 return true if it should be transformed into: ((X < </l >> Y) & C) ==/!= 0 WARNING: if 'X' is a constant, the fold may deadlock! FIXME: we could avoid passing XC, but we can't use isConstOrConstSplat() here because it can end up being not linked in.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1068
Parameters
- llvm::SDValue X
- llvm::ConstantSDNode* XC
- llvm::ConstantSDNode* CC
- llvm::SDValue Y
- unsigned int OldShiftOpcode
- unsigned int NewShiftOpcode
- llvm::SelectionDAG& DAG
¶bool shouldReduceLoadWidth(llvm::SDNode* Load,
ISD::LoadExtType ExtTy,
llvm::EVT NewVT) const
bool shouldReduceLoadWidth(llvm::SDNode* Load,
ISD::LoadExtType ExtTy,
llvm::EVT NewVT) const
Description
Return true if we believe it is correct and profitable to reduce the load node to a smaller type.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1342
Parameters
- llvm::SDNode* Load
- ISD::LoadExtType ExtTy
- llvm::EVT NewVT
¶bool shouldScalarizeBinop(llvm::SDValue) const
bool shouldScalarizeBinop(llvm::SDValue) const
Description
Scalar ops always have equal or better analysis/performance/power than the vector equivalent, so this always makes sense if the scalar op is supported.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1369
Parameters
¶bool shouldSinkOperands(
llvm::Instruction* I,
SmallVectorImpl<llvm::Use*>& Ops) const
bool shouldSinkOperands(
llvm::Instruction* I,
SmallVectorImpl<llvm::Use*>& Ops) const
Description
Return true if sinking I's operands to the same basic block as I is profitable, e.g. because the operands can be folded into a target instruction during instruction selection. After calling the function\p Ops contains the Uses to sink ordered by dominance (dominating users come first).
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1282
Parameters
- llvm::Instruction* I
- SmallVectorImpl<llvm::Use*>& Ops
¶bool shouldSplatInsEltVarIndex(llvm::EVT VT) const
bool shouldSplatInsEltVarIndex(llvm::EVT VT) const
Description
Return true if inserting a scalar into a variable element of an undef vector is more efficiently handled by splatting the scalar instead.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1098
Parameters
- llvm::EVT VT
¶bool shouldTransformSignedTruncationCheck(
llvm::EVT XVT,
unsigned int KeptBits) const
bool shouldTransformSignedTruncationCheck(
llvm::EVT XVT,
unsigned int KeptBits) const
Description
Should we tranform the IR-optimal check for whether given truncation down into KeptBits would be truncating or not: (add %x, (1 < < (KeptBits-1))) srccond (1 < < KeptBits) Into it's more traditional form: ((%x < < C) a>> C) dstcond %x Return true if we should transform. Return false if there is no preference.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1079
Parameters
- llvm::EVT XVT
- unsigned int KeptBits
¶bool softPromoteHalfType() const
bool softPromoteHalfType() const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1446
¶bool splitValueIntoRegisterParts(
llvm::SelectionDAG& DAG,
const llvm::SDLoc& DL,
llvm::SDValue Val,
llvm::SDValue* Parts,
unsigned int NumParts,
llvm::MVT PartVT,
Optional<CallingConv::ID> CC) const
bool splitValueIntoRegisterParts(
llvm::SelectionDAG& DAG,
const llvm::SDLoc& DL,
llvm::SDValue Val,
llvm::SDValue* Parts,
unsigned int NumParts,
llvm::MVT PartVT,
Optional<CallingConv::ID> CC) const
Description
Target-specific splitting of values into parts that fit a register storing a legal type
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1626
Parameters
- llvm::SelectionDAG& DAG
- const llvm::SDLoc& DL
- llvm::SDValue Val
- llvm::SDValue* Parts
- unsigned int NumParts
- llvm::MVT PartVT
- Optional<CallingConv::ID> CC
¶bool storeOfVectorConstantIsCheap(
llvm::EVT MemVT,
unsigned int NumElem,
unsigned int AddrSpace) const
bool storeOfVectorConstantIsCheap(
llvm::EVT MemVT,
unsigned int NumElem,
unsigned int AddrSpace) const
Description
Return true if it is expected to be cheaper to do a store of a non-zero vector constant with the given size and type for the address space than to store the individual scalar element constants.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1383
Parameters
- llvm::EVT MemVT
- unsigned int NumElem
- unsigned int AddrSpace
¶bool supportSplitCSR(
llvm::MachineFunction* MF) const
bool supportSplitCSR(
llvm::MachineFunction* MF) const
Description
Return true if the target supports that a subset of CSRs for the given machine function is handled explicitly via copies.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1616
Parameters
¶bool supportSwiftError() const
bool supportSwiftError() const
Description
Return true if the target supports swifterror attribute. It optimizes loads and stores to reading and writing a specific register.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1461
¶bool targetShrinkDemandedConstant(
llvm::SDValue Op,
const llvm::APInt& DemandedBits,
const llvm::APInt& DemandedElts,
llvm::TargetLowering::TargetLoweringOpt& TLO)
const
bool targetShrinkDemandedConstant(
llvm::SDValue Op,
const llvm::APInt& DemandedBits,
const llvm::APInt& DemandedElts,
llvm::TargetLowering::TargetLoweringOpt& TLO)
const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1117
Parameters
- llvm::SDValue Op
- const llvm::APInt& DemandedBits
- const llvm::APInt& DemandedElts
- llvm::TargetLowering::TargetLoweringOpt& TLO
¶llvm::SDValue unwrapAddress(llvm::SDValue N) const
llvm::SDValue unwrapAddress(llvm::SDValue N) const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1178
Parameters
¶bool useLoadStackGuardNode() const
bool useLoadStackGuardNode() const
Description
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1423
¶bool useSoftFloat() const
bool useSoftFloat() const
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:943
¶bool useStackGuardXorFP() const
bool useStackGuardXorFP() const
Description
If this function returns true, stack protection checks should XOR the frame pointer (or whichever pointer is used to address locals) into the stack guard value before checking it. getIRStackGuard must return nullptr if this returns true.
Declared at: llvm/lib/Target/X86/X86ISelLowering.h:1424