class MachineIRBuilder

Declaration

class MachineIRBuilder { /* full declaration omitted */ };

Description

Helper class to build MachineInstr. It keeps internally the insertion point and debug location for all the new instructions we want to create. This information can be modify via the related setters.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:219

Member Variables

private llvm::MachineIRBuilderState State

Method Overview

public MachineIRBuilder()
public MachineIRBuilder(llvm::MachineFunction & MF)
public MachineIRBuilder(llvm::MachineBasicBlock & MBB, MachineBasicBlock::iterator InsPt)
public MachineIRBuilder(llvm::MachineInstr & MI)
public MachineIRBuilder(llvm::MachineInstr & MI, llvm::GISelChangeObserver & Observer)
public MachineIRBuilder(const llvm::MachineIRBuilderState & BState)
public llvm::MachineInstrBuilder buildAShr(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildAbs(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildAdd(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildAddrSpaceCast(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildAnd(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1)
public llvm::MachineInstrBuilder buildAnyExt(const llvm::DstOp & Res, const llvm::SrcOp & Op)
public llvm::MachineInstrBuilder buildAnyExtOrTrunc(const llvm::DstOp & Res, const llvm::SrcOp & Op)
public llvm::MachineInstrBuilder buildAssertAlign(const llvm::DstOp & Res, const llvm::SrcOp & Op, llvm::Align AlignVal)
public llvm::MachineInstrBuilder buildAssertOp(unsigned int Opc, const llvm::DstOp & Res, const llvm::SrcOp & Op, unsigned int Val)
public llvm::MachineInstrBuilder buildAssertSExt(const llvm::DstOp & Res, const llvm::SrcOp & Op, unsigned int Size)
public llvm::MachineInstrBuilder buildAssertZExt(const llvm::DstOp & Res, const llvm::SrcOp & Op, unsigned int Size)
public llvm::MachineInstrBuilder buildAtomicCmpXchg(llvm::Register OldValRes, llvm::Register Addr, llvm::Register CmpVal, llvm::Register NewVal, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicCmpXchgWithSuccess(llvm::Register OldValRes, llvm::Register SuccessRes, llvm::Register Addr, llvm::Register CmpVal, llvm::Register NewVal, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMW(unsigned int Opcode, const llvm::DstOp & OldValRes, const llvm::SrcOp & Addr, const llvm::SrcOp & Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWAdd(llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWAnd(llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWFAdd(const llvm::DstOp & OldValRes, const llvm::SrcOp & Addr, const llvm::SrcOp & Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWFMax(const llvm::DstOp & OldValRes, const llvm::SrcOp & Addr, const llvm::SrcOp & Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWFMin(const llvm::DstOp & OldValRes, const llvm::SrcOp & Addr, const llvm::SrcOp & Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWFSub(const llvm::DstOp & OldValRes, const llvm::SrcOp & Addr, const llvm::SrcOp & Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWMax(llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWMin(llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWNand(llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWOr(llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWSub(llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWUmax(llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWUmin(llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWXchg(llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildAtomicRMWXor(llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildBSwap(const llvm::DstOp & Dst, const llvm::SrcOp & Src0)
public llvm::MachineInstrBuilder buildBitReverse(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildBitcast(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildBlockAddress(llvm::Register Res, const llvm::BlockAddress * BA)
public llvm::MachineInstrBuilder buildBoolExt(const llvm::DstOp & Res, const llvm::SrcOp & Op, bool IsFP)
public llvm::MachineInstrBuilder buildBoolExtInReg(const llvm::DstOp & Res, const llvm::SrcOp & Op, bool IsVector, bool IsFP)
public llvm::MachineInstrBuilder buildBr(llvm::MachineBasicBlock & Dest)
public llvm::MachineInstrBuilder buildBrCond(const llvm::SrcOp & Tst, llvm::MachineBasicBlock & Dest)
public llvm::MachineInstrBuilder buildBrIndirect(llvm::Register Tgt)
public llvm::MachineInstrBuilder buildBrJT(llvm::Register TablePtr, unsigned int JTI, llvm::Register IndexReg)
public llvm::MachineInstrBuilder buildBuildVector(const llvm::DstOp & Res, ArrayRef<llvm::Register> Ops)
public llvm::MachineInstrBuilder buildBuildVectorConstant(const llvm::DstOp & Res, ArrayRef<llvm::APInt> Ops)
public llvm::MachineInstrBuilder buildBuildVectorTrunc(const llvm::DstOp & Res, ArrayRef<llvm::Register> Ops)
public llvm::MachineInstrBuilder buildCTLZ(const llvm::DstOp & Dst, const llvm::SrcOp & Src0)
public llvm::MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const llvm::DstOp & Dst, const llvm::SrcOp & Src0)
public llvm::MachineInstrBuilder buildCTPOP(const llvm::DstOp & Dst, const llvm::SrcOp & Src0)
public llvm::MachineInstrBuilder buildCTTZ(const llvm::DstOp & Dst, const llvm::SrcOp & Src0)
public llvm::MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const llvm::DstOp & Dst, const llvm::SrcOp & Src0)
public llvm::MachineInstrBuilder buildCast(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildConcatVectors(const llvm::DstOp & Res, ArrayRef<llvm::Register> Ops)
public llvm::MachineInstrBuilder buildConstDbgValue(const llvm::Constant & C, const llvm::MDNode * Variable, const llvm::MDNode * Expr)
public virtual llvm::MachineInstrBuilder buildConstant(const llvm::DstOp & Res, const llvm::ConstantInt & Val)
public llvm::MachineInstrBuilder buildConstant(const llvm::DstOp & Res, int64_t Val)
public llvm::MachineInstrBuilder buildConstant(const llvm::DstOp & Res, const llvm::APInt & Val)
public llvm::MachineInstrBuilder buildCopy(const llvm::DstOp & Res, const llvm::SrcOp & Op)
public llvm::MachineInstrBuilder buildDbgLabel(const llvm::MDNode * Label)
public llvm::MachineInstrBuilder buildDeleteTrailingVectorElements(const llvm::DstOp & Res, const llvm::SrcOp & Op0)
public llvm::MachineInstrBuilder buildDirectDbgValue(llvm::Register Reg, const llvm::MDNode * Variable, const llvm::MDNode * Expr)
public llvm::MachineInstrBuilder buildDynStackAlloc(const llvm::DstOp & Res, const llvm::SrcOp & Size, llvm::Align Alignment)
public llvm::MachineInstrBuilder buildExtOrTrunc(unsigned int ExtOpc, const llvm::DstOp & Res, const llvm::SrcOp & Op)
public llvm::MachineInstrBuilder buildExtract(const llvm::DstOp & Res, const llvm::SrcOp & Src, uint64_t Index)
public llvm::MachineInstrBuilder buildExtractVectorElement(const llvm::DstOp & Res, const llvm::SrcOp & Val, const llvm::SrcOp & Idx)
public llvm::MachineInstrBuilder buildFAbs(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFAdd(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFCanonicalize(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const llvm::DstOp & Res, const llvm::SrcOp & Op0, const llvm::SrcOp & Op1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFConstant(const llvm::DstOp & Res, const llvm::APFloat & Val)
public llvm::MachineInstrBuilder buildFConstant(const llvm::DstOp & Res, double Val)
public virtual llvm::MachineInstrBuilder buildFConstant(const llvm::DstOp & Res, const llvm::ConstantFP & Val)
public llvm::MachineInstrBuilder buildFCopysign(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1)
public llvm::MachineInstrBuilder buildFDiv(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFExp2(const llvm::DstOp & Dst, const llvm::SrcOp & Src, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFFloor(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFIDbgValue(int FI, const llvm::MDNode * Variable, const llvm::MDNode * Expr)
public llvm::MachineInstrBuilder buildFLog(const llvm::DstOp & Dst, const llvm::SrcOp & Src, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFLog2(const llvm::DstOp & Dst, const llvm::SrcOp & Src, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFMA(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, const llvm::SrcOp & Src2, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFMAD(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, const llvm::SrcOp & Src2, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFMaxNum(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFMaxNumIEEE(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFMinNum(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFMinNumIEEE(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFMul(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFNeg(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFPExt(const llvm::DstOp & Res, const llvm::SrcOp & Op, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFPTOSI(const llvm::DstOp & Dst, const llvm::SrcOp & Src0)
public llvm::MachineInstrBuilder buildFPTOUI(const llvm::DstOp & Dst, const llvm::SrcOp & Src0)
public llvm::MachineInstrBuilder buildFPTrunc(const llvm::DstOp & Res, const llvm::SrcOp & Op, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFPow(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFSub(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildFence(unsigned int Ordering, unsigned int Scope)
public llvm::MachineInstrBuilder buildFrameIndex(const llvm::DstOp & Res, int Idx)
public llvm::MachineInstrBuilder buildFreeze(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildGlobalValue(const llvm::DstOp & Res, const llvm::GlobalValue * GV)
public llvm::MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const llvm::DstOp & Res, const llvm::SrcOp & Op0, const llvm::SrcOp & Op1)
public llvm::MachineInstrBuilder buildIndirectDbgValue(llvm::Register Reg, const llvm::MDNode * Variable, const llvm::MDNode * Expr)
public llvm::MachineInstrBuilder buildInsert(const llvm::DstOp & Res, const llvm::SrcOp & Src, const llvm::SrcOp & Op, unsigned int Index)
public llvm::MachineInstrBuilder buildInsertVectorElement(const llvm::DstOp & Res, const llvm::SrcOp & Val, const llvm::SrcOp & Elt, const llvm::SrcOp & Idx)
public virtual llvm::MachineInstrBuilder buildInstr(unsigned int Opc, ArrayRef<llvm::DstOp> DstOps, ArrayRef<llvm::SrcOp> SrcOps, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildInstr(unsigned int Opcode)
public llvm::MachineInstrBuilder buildInstrNoInsert(unsigned int Opcode)
public llvm::MachineInstrBuilder buildIntToPtr(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<llvm::Register> Res, bool HasSideEffects)
public llvm::MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<llvm::DstOp> Res, bool HasSideEffects)
public llvm::MachineInstrBuilder buildIntrinsicTrunc(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildJumpTable(const llvm::LLT PtrTy, unsigned int JTI)
public llvm::MachineInstrBuilder buildLShr(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildLoad(const llvm::DstOp & Res, const llvm::SrcOp & Addr, llvm::MachinePointerInfo PtrInfo, llvm::Align Alignment, MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone, const llvm::AAMDNodes & AAInfo = llvm::AAMDNodes())
public llvm::MachineInstrBuilder buildLoad(const llvm::DstOp & Res, const llvm::SrcOp & Addr, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildLoadFromOffset(const llvm::DstOp & Dst, const llvm::SrcOp & BasePtr, llvm::MachineMemOperand & BaseMMO, int64_t Offset)
public llvm::MachineInstrBuilder buildLoadInstr(unsigned int Opcode, const llvm::DstOp & Res, const llvm::SrcOp & Addr, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildMaskLowPtrBits(const llvm::DstOp & Res, const llvm::SrcOp & Op0, uint32_t NumBits)
public llvm::MachineInstrBuilder buildMemCpy(const llvm::SrcOp & DstPtr, const llvm::SrcOp & SrcPtr, const llvm::SrcOp & Size, llvm::MachineMemOperand & DstMMO, llvm::MachineMemOperand & SrcMMO)
public llvm::MachineInstrBuilder buildMemTransferInst(unsigned int Opcode, const llvm::SrcOp & DstPtr, const llvm::SrcOp & SrcPtr, const llvm::SrcOp & Size, llvm::MachineMemOperand & DstMMO, llvm::MachineMemOperand & SrcMMO)
public llvm::MachineInstrBuilder buildMerge(const llvm::DstOp & Res, ArrayRef<llvm::Register> Ops)
public llvm::MachineInstrBuilder buildMerge(const llvm::DstOp & Res, std::initializer_list<SrcOp> Ops)
public llvm::MachineInstrBuilder buildMul(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildNeg(const llvm::DstOp & Dst, const llvm::SrcOp & Src0)
public llvm::MachineInstrBuilder buildNot(const llvm::DstOp & Dst, const llvm::SrcOp & Src0)
public llvm::MachineInstrBuilder buildOr(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildPadVectorWithUndefElements(const llvm::DstOp & Res, const llvm::SrcOp & Op0)
public llvm::MachineInstrBuilder buildPtrAdd(const llvm::DstOp & Res, const llvm::SrcOp & Op0, const llvm::SrcOp & Op1)
public llvm::MachineInstrBuilder buildPtrMask(const llvm::DstOp & Res, const llvm::SrcOp & Op0, const llvm::SrcOp & Op1)
public llvm::MachineInstrBuilder buildPtrToInt(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildRotateLeft(const llvm::DstOp & Dst, const llvm::SrcOp & Src, const llvm::SrcOp & Amt)
public llvm::MachineInstrBuilder buildRotateRight(const llvm::DstOp & Dst, const llvm::SrcOp & Src, const llvm::SrcOp & Amt)
public llvm::MachineInstrBuilder buildSAdde(const llvm::DstOp & Res, const llvm::DstOp & CarryOut, const llvm::SrcOp & Op0, const llvm::SrcOp & Op1, const llvm::SrcOp & CarryIn)
public llvm::MachineInstrBuilder buildSAddo(const llvm::DstOp & Res, const llvm::DstOp & CarryOut, const llvm::SrcOp & Op0, const llvm::SrcOp & Op1)
public llvm::MachineInstrBuilder buildSExt(const llvm::DstOp & Res, const llvm::SrcOp & Op)
public llvm::MachineInstrBuilder buildSExtInReg(const llvm::DstOp & Res, const llvm::SrcOp & Op, int64_t ImmOp)
public llvm::MachineInstrBuilder buildSExtOrTrunc(const llvm::DstOp & Res, const llvm::SrcOp & Op)
public llvm::MachineInstrBuilder buildSITOFP(const llvm::DstOp & Dst, const llvm::SrcOp & Src0)
public llvm::MachineInstrBuilder buildSMax(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1)
public llvm::MachineInstrBuilder buildSMin(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1)
public llvm::MachineInstrBuilder buildSMulH(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildSSube(const llvm::DstOp & Res, const llvm::DstOp & CarryOut, const llvm::SrcOp & Op0, const llvm::SrcOp & Op1, const llvm::SrcOp & CarryIn)
public llvm::MachineInstrBuilder buildSSubo(const llvm::DstOp & Res, const llvm::DstOp & CarryOut, const llvm::SrcOp & Op0, const llvm::SrcOp & Op1)
public llvm::MachineInstrBuilder buildSbfx(const llvm::DstOp & Dst, const llvm::SrcOp & Src, const llvm::SrcOp & LSB, const llvm::SrcOp & Width)
public llvm::MachineInstrBuilder buildSelect(const llvm::DstOp & Res, const llvm::SrcOp & Tst, const llvm::SrcOp & Op0, const llvm::SrcOp & Op1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildShl(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildShuffleSplat(const llvm::DstOp & Res, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildShuffleVector(const llvm::DstOp & Res, const llvm::SrcOp & Src1, const llvm::SrcOp & Src2, ArrayRef<int> Mask)
public llvm::MachineInstrBuilder buildSplatVector(const llvm::DstOp & Res, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildStore(const llvm::SrcOp & Val, const llvm::SrcOp & Addr, llvm::MachineMemOperand & MMO)
public llvm::MachineInstrBuilder buildStore(const llvm::SrcOp & Val, const llvm::SrcOp & Addr, llvm::MachinePointerInfo PtrInfo, llvm::Align Alignment, MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone, const llvm::AAMDNodes & AAInfo = llvm::AAMDNodes())
public llvm::MachineInstrBuilder buildSub(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildTrunc(const llvm::DstOp & Res, const llvm::SrcOp & Op)
public llvm::MachineInstrBuilder buildUAdde(const llvm::DstOp & Res, const llvm::DstOp & CarryOut, const llvm::SrcOp & Op0, const llvm::SrcOp & Op1, const llvm::SrcOp & CarryIn)
public llvm::MachineInstrBuilder buildUAddo(const llvm::DstOp & Res, const llvm::DstOp & CarryOut, const llvm::SrcOp & Op0, const llvm::SrcOp & Op1)
public llvm::MachineInstrBuilder buildUITOFP(const llvm::DstOp & Dst, const llvm::SrcOp & Src0)
public llvm::MachineInstrBuilder buildUMax(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1)
public llvm::MachineInstrBuilder buildUMin(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1)
public llvm::MachineInstrBuilder buildUMulH(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildURem(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1, Optional<unsigned int> Flags = None)
public llvm::MachineInstrBuilder buildUSube(const llvm::DstOp & Res, const llvm::DstOp & CarryOut, const llvm::SrcOp & Op0, const llvm::SrcOp & Op1, const llvm::SrcOp & CarryIn)
public llvm::MachineInstrBuilder buildUSubo(const llvm::DstOp & Res, const llvm::DstOp & CarryOut, const llvm::SrcOp & Op0, const llvm::SrcOp & Op1)
public llvm::MachineInstrBuilder buildUbfx(const llvm::DstOp & Dst, const llvm::SrcOp & Src, const llvm::SrcOp & LSB, const llvm::SrcOp & Width)
public llvm::MachineInstrBuilder buildUndef(const llvm::DstOp & Res)
public llvm::MachineInstrBuilder buildUnmerge(llvm::LLT Res, const llvm::SrcOp & Op)
public llvm::MachineInstrBuilder buildUnmerge(ArrayRef<llvm::Register> Res, const llvm::SrcOp & Op)
public llvm::MachineInstrBuilder buildUnmerge(ArrayRef<llvm::LLT> Res, const llvm::SrcOp & Op)
public llvm::MachineInstrBuilder buildVecReduceAdd(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildVecReduceAnd(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildVecReduceFAdd(const llvm::DstOp & Dst, const llvm::SrcOp & ScalarIn, const llvm::SrcOp & VecIn)
public llvm::MachineInstrBuilder buildVecReduceFMax(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildVecReduceFMin(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildVecReduceFMul(const llvm::DstOp & Dst, const llvm::SrcOp & ScalarIn, const llvm::SrcOp & VecIn)
public llvm::MachineInstrBuilder buildVecReduceMul(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildVecReduceOr(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildVecReduceSMax(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildVecReduceSMin(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildVecReduceSeqFAdd(const llvm::DstOp & Dst, const llvm::SrcOp & ScalarIn, const llvm::SrcOp & VecIn)
public llvm::MachineInstrBuilder buildVecReduceSeqFMul(const llvm::DstOp & Dst, const llvm::SrcOp & ScalarIn, const llvm::SrcOp & VecIn)
public llvm::MachineInstrBuilder buildVecReduceUMax(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildVecReduceUMin(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildVecReduceXor(const llvm::DstOp & Dst, const llvm::SrcOp & Src)
public llvm::MachineInstrBuilder buildXor(const llvm::DstOp & Dst, const llvm::SrcOp & Src0, const llvm::SrcOp & Src1)
public llvm::MachineInstrBuilder buildZExt(const llvm::DstOp & Res, const llvm::SrcOp & Op)
public llvm::MachineInstrBuilder buildZExtInReg(const llvm::DstOp & Res, const llvm::SrcOp & Op, int64_t ImmOp)
public llvm::MachineInstrBuilder buildZExtOrTrunc(const llvm::DstOp & Res, const llvm::SrcOp & Op)
public unsigned int getBoolExtOp(bool IsVec, bool IsFP) const
public llvm::GISelCSEInfo * getCSEInfo()
public const llvm::GISelCSEInfo * getCSEInfo() const
public const llvm::DebugLoc & getDL()
public const llvm::DataLayout & getDataLayout() const
public const llvm::DebugLoc & getDebugLoc()
public MachineBasicBlock::iterator getInsertPt()
public llvm::MachineBasicBlock & getMBB()
public const llvm::MachineBasicBlock & getMBB() const
public llvm::MachineFunction & getMF()
public const llvm::MachineFunction & getMF() const
public llvm::MachineRegisterInfo * getMRI()
public const llvm::MachineRegisterInfo * getMRI() const
public llvm::MachineIRBuilderState & getState()
public const llvm::TargetInstrInfo & getTII()
public llvm::MachineInstrBuilder insertInstr(llvm::MachineInstrBuilder MIB)
public Optional<llvm::MachineInstrBuilder> materializePtrAdd(llvm::Register & Res, llvm::Register Op0, const llvm::LLT ValueTy, uint64_t Value)
protected void recordInsertion(llvm::MachineInstr * InsertedInstr) const
public void setCSEInfo(llvm::GISelCSEInfo * Info)
public void setChangeObserver(llvm::GISelChangeObserver & Observer)
public void setDebugLoc(const llvm::DebugLoc & DL)
public void setInsertPt(llvm::MachineBasicBlock & MBB, MachineBasicBlock::iterator II)
public void setInstr(llvm::MachineInstr & MI)
public void setInstrAndDebugLoc(llvm::MachineInstr & MI)
public void setMBB(llvm::MachineBasicBlock & MBB)
public void setMF(llvm::MachineFunction & MF)
public void stopObservingChanges()
protected void validateBinaryOp(const llvm::LLT Res, const llvm::LLT Op0, const llvm::LLT Op1)
protected void validateSelectOp(const llvm::LLT ResTy, const llvm::LLT TstTy, const llvm::LLT Op0Ty, const llvm::LLT Op1Ty)
protected void validateShiftOp(const llvm::LLT Res, const llvm::LLT Op0, const llvm::LLT Op1)
protected void validateTruncExt(const llvm::LLT Dst, const llvm::LLT Src, bool IsExtend)
protected void validateUnaryOp(const llvm::LLT Res, const llvm::LLT Op0)
public virtual ~MachineIRBuilder()

Methods

¶MachineIRBuilder()

Description

Some constructors for easy use.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:240

¶MachineIRBuilder(llvm::MachineFunction& MF)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:241

Parameters

llvm::MachineFunction& MF

¶MachineIRBuilder(
    llvm::MachineBasicBlock& MBB,
    MachineBasicBlock::iterator InsPt)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:243

Parameters

llvm::MachineBasicBlock& MBB
MachineBasicBlock::iterator InsPt

¶MachineIRBuilder(llvm::MachineInstr& MI)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:248

Parameters

llvm::MachineInstr& MI

¶MachineIRBuilder(
    llvm::MachineInstr& MI,
    llvm::GISelChangeObserver& Observer)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:254

Parameters

llvm::MachineInstr& MI
llvm::GISelChangeObserver& Observer

¶MachineIRBuilder(
    const llvm::MachineIRBuilderState& BState)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:261

Parameters

const llvm::MachineIRBuilderState& BState

¶llvm::MachineInstrBuilder buildAShr(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1574

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildAbs(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert \p Dst = G_ABS \p Src

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1805

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildAdd(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_ADD \p Op0, \p Op1 G_ADD sets \p Res to the sum of integer parameters \p Op0 and \p Op1, truncated to their width.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1474

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAddrSpaceCast(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert \p Dst = G_ADDRSPACE_CAST \p Src

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:673

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildAnd(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1)

Description

Build and insert \p Res = G_AND \p Op0, \p Op1 G_AND sets \p Res to the bitwise and of integer parameters \p Op0 and \p Op1.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1591

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAnyExt(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op)

Description

Build and insert \p Res = G_ANYEXT \p Op0 G_ANYEXT produces a register of the specified width, with bits 0 to sizeof(\p Ty) * 8 set to \p Op. The remaining bits are unspecified (i.e. this is neither zero nor sign-extension). For a vector register, each element is extended individually.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:629

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildAnyExtOrTrunc(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op)

Description

\p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op. ///

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:735

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildAssertAlign(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op,
    llvm::Align AlignVal)

Description

Build and insert \p Res = G_ASSERT_ALIGN Op, AlignVal

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:881

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op
llvm::Align AlignVal

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAssertOp(
    unsigned int Opc,
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op,
    unsigned int Val)

Description

Build and insert G_ASSERT_SEXT, G_ASSERT_ZEXT, or G_ASSERT_ALIGN

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:857

Parameters

unsigned int Opc
const llvm::DstOp& Res
const llvm::SrcOp& Op
unsigned int Val

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAssertSExt(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op,
    unsigned int Size)

Description

Build and insert \p Res = G_ASSERT_SEXT Op, Size

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:873

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op
unsigned int Size

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAssertZExt(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op,
    unsigned int Size)

Description

Build and insert \p Res = G_ASSERT_ZEXT Op, Size

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:865

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op
unsigned int Size

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicCmpXchg(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register CmpVal,
    llvm::Register NewVal,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMIC_CMPXCHG Addr, CmpVal, NewVal, MMO`. Atomically replace the value at \p Addr with \p NewVal if it is currently\p CmpVal otherwise leaves it unchanged. Puts the original value from \p Addr in \p Res.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1210

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register CmpVal
llvm::Register NewVal
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder
buildAtomicCmpXchgWithSuccess(
    llvm::Register OldValRes,
    llvm::Register SuccessRes,
    llvm::Register Addr,
    llvm::Register CmpVal,
    llvm::Register NewVal,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def >, SuccessRes <def > = G_ATOMIC_CMPXCHG_WITH_SUCCESS Addr, CmpVal, NewVal, MMO`. Atomically replace the value at \p Addr with \p NewVal if it is currently\p CmpVal otherwise leaves it unchanged. Puts the original value from \p Addr in \p Res, along with an s1 indicating whether it was replaced.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1192

Parameters

llvm::Register OldValRes
llvm::Register SuccessRes
llvm::Register Addr
llvm::Register CmpVal
llvm::Register NewVal
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMW(
    unsigned int Opcode,
    const llvm::DstOp& OldValRes,
    const llvm::SrcOp& Addr,
    const llvm::SrcOp& Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_ <Opcode > Addr, Val, MMO`. Atomically read-modify-update the value at \p Addr with \p Val. Puts the original value from \p Addr in \p OldValRes. The modification is determined by the opcode.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1227

Parameters

unsigned int Opcode
const llvm::DstOp& OldValRes
const llvm::SrcOp& Addr
const llvm::SrcOp& Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWAdd(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_ADD Addr, Val, MMO`. Atomically replace the value at \p Addr with the addition of \p Val and the original value. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1258

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWAnd(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_AND Addr, Val, MMO`. Atomically replace the value at \p Addr with the bitwise and of \p Val and the original value. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1288

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWFAdd(
    const llvm::DstOp& OldValRes,
    const llvm::SrcOp& Addr,
    const llvm::SrcOp& Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_FADD Addr, Val, MMO`.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1402

Parameters

const llvm::DstOp& OldValRes
const llvm::SrcOp& Addr
const llvm::SrcOp& Val
llvm::MachineMemOperand& MMO

¶llvm::MachineInstrBuilder buildAtomicRMWFMax(
    const llvm::DstOp& OldValRes,
    const llvm::SrcOp& Addr,
    const llvm::SrcOp& Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_FMAX Addr, Val, MMO`. Atomically replace the value at \p Addr with the floating point maximum of\p Val and the original value. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1424

Parameters

const llvm::DstOp& OldValRes
const llvm::SrcOp& Addr
const llvm::SrcOp& Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWFMin(
    const llvm::DstOp& OldValRes,
    const llvm::SrcOp& Addr,
    const llvm::SrcOp& Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_FMIN Addr, Val, MMO`. Atomically replace the value at \p Addr with the floating point minimum of\p Val and the original value. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1441

Parameters

const llvm::DstOp& OldValRes
const llvm::SrcOp& Addr
const llvm::SrcOp& Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWFSub(
    const llvm::DstOp& OldValRes,
    const llvm::SrcOp& Addr,
    const llvm::SrcOp& Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_FSUB Addr, Val, MMO`.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1407

Parameters

const llvm::DstOp& OldValRes
const llvm::SrcOp& Addr
const llvm::SrcOp& Val
llvm::MachineMemOperand& MMO

¶llvm::MachineInstrBuilder buildAtomicRMWMax(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_MAX Addr, Val, MMO`. Atomically replace the value at \p Addr with the signed maximum of \p Val and the original value. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1350

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWMin(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_MIN Addr, Val, MMO`. Atomically replace the value at \p Addr with the signed minimum of \p Val and the original value. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1366

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWNand(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_NAND Addr, Val, MMO`. Atomically replace the value at \p Addr with the bitwise nand of \p Val and the original value. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1304

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWOr(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_OR Addr, Val, MMO`. Atomically replace the value at \p Addr with the bitwise or of \p Val and the original value. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1319

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWSub(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_SUB Addr, Val, MMO`. Atomically replace the value at \p Addr with the subtraction of \p Val and the original value. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1273

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWUmax(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_UMAX Addr, Val, MMO`. Atomically replace the value at \p Addr with the unsigned maximum of \p Val and the original value. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1382

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWUmin(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_UMIN Addr, Val, MMO`. Atomically replace the value at \p Addr with the unsigned minimum of \p Val and the original value. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1398

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWXchg(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_XCHG Addr, Val, MMO`. Atomically replace the value at \p Addr with \p Val. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1243

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildAtomicRMWXor(
    llvm::Register OldValRes,
    llvm::Register Addr,
    llvm::Register Val,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `OldValRes <def > = G_ATOMICRMW_XOR Addr, Val, MMO`. Atomically replace the value at \p Addr with the bitwise xor of \p Val and the original value. Puts the original value from \p Addr in \p OldValRes.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1334

Parameters

llvm::Register OldValRes
llvm::Register Addr
llvm::Register Val
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildBSwap(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0)

Description

Build and insert \p Dst = G_BSWAP \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1660

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0

¶llvm::MachineInstrBuilder buildBitReverse(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert \p Dst = G_BITREVERSE \p Src

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1958

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildBitcast(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert \p Dst = G_BITCAST \p Src

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:668

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildBlockAddress(
    llvm::Register Res,
    const llvm::BlockAddress* BA)

Description

Build and insert \p Res = G_BLOCK_ADDR \p BA G_BLOCK_ADDR computes the address of a basic block.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1461

Parameters

llvm::Register Res
const llvm::BlockAddress* BA

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildBoolExt(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op,
    bool IsFP)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:683

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op
bool IsFP

¶llvm::MachineInstrBuilder buildBoolExtInReg(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op,
    bool IsVector,
    bool IsFP)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:689

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op
bool IsVector
bool IsFP

¶llvm::MachineInstrBuilder buildBr(
    llvm::MachineBasicBlock& Dest)

Description

Build and insert G_BR \p Dest G_BR is an unconditional branch to \p Dest.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:765

Parameters

llvm::MachineBasicBlock& Dest

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildBrCond(
    const llvm::SrcOp& Tst,
    llvm::MachineBasicBlock& Dest)

Description

Build and insert G_BRCOND \p Tst, \p Dest G_BRCOND is a conditional branch to \p Dest.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:779

Parameters

const llvm::SrcOp& Tst
llvm::MachineBasicBlock& Dest

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildBrIndirect(
    llvm::Register Tgt)

Description

Build and insert G_BRINDIRECT \p Tgt G_BRINDIRECT is an indirect branch to \p Tgt.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:789

Parameters

llvm::Register Tgt

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildBrJT(
    llvm::Register TablePtr,
    unsigned int JTI,
    llvm::Register IndexReg)

Description

Build and insert G_BRJT \p TablePtr, \p JTI, \p IndexReg G_BRJT is a jump table branch using a table base pointer \p TablePtr, jump table index \p JTI and index \p IndexReg

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:802

Parameters

llvm::Register TablePtr
unsigned int JTI
llvm::Register IndexReg

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildBuildVector(
    const llvm::DstOp& Res,
    ArrayRef<llvm::Register> Ops)

Description

Build and insert \p Res = G_BUILD_VECTOR \p Op0, ... G_BUILD_VECTOR creates a vector value from multiple scalar registers.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:999

Parameters

const llvm::DstOp& Res
ArrayRef<llvm::Register> Ops

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder
buildBuildVectorConstant(
    const llvm::DstOp& Res,
    ArrayRef<llvm::APInt> Ops)

Description

Build and insert \p Res = G_BUILD_VECTOR \p Op0, ... where each OpN is built with G_CONSTANT.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1004

Parameters

const llvm::DstOp& Res
ArrayRef<llvm::APInt> Ops

¶llvm::MachineInstrBuilder buildBuildVectorTrunc(
    const llvm::DstOp& Res,
    ArrayRef<llvm::Register> Ops)

Description

Build and insert \p Res = G_BUILD_VECTOR_TRUNC \p Op0, ... G_BUILD_VECTOR_TRUNC creates a vector value from multiple scalar registers which have types larger than the destination vector element type, and truncates the values to fit. If the operands given are already the same size as the vector elt type, then this method will instead create a G_BUILD_VECTOR instruction.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1025

Parameters

const llvm::DstOp& Res
ArrayRef<llvm::Register> Ops

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildCTLZ(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0)

Description

Build and insert \p Res = G_CTLZ \p Op0, \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1640

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0

¶llvm::MachineInstrBuilder buildCTLZ_ZERO_UNDEF(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0)

Description

Build and insert \p Res = G_CTLZ_ZERO_UNDEF \p Op0, \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1645

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0

¶llvm::MachineInstrBuilder buildCTPOP(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0)

Description

Build and insert \p Res = G_CTPOP \p Op0, \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1635

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0

¶llvm::MachineInstrBuilder buildCTTZ(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0)

Description

Build and insert \p Res = G_CTTZ \p Op0, \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1650

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0

¶llvm::MachineInstrBuilder buildCTTZ_ZERO_UNDEF(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0)

Description

Build and insert \p Res = G_CTTZ_ZERO_UNDEF \p Op0, \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1655

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0

¶llvm::MachineInstrBuilder buildCast(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert an appropriate cast between two registers of equal size.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:756

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildConcatVectors(
    const llvm::DstOp& Res,
    ArrayRef<llvm::Register> Ops)

Description

Build and insert \p Res = G_CONCAT_VECTORS \p Op0, ... G_CONCAT_VECTORS creates a vector from the concatenation of 2 or more vectors.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1056

Parameters

const llvm::DstOp& Res
ArrayRef<llvm::Register> Ops

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildConstDbgValue(
    const llvm::Constant& C,
    const llvm::MDNode* Variable,
    const llvm::MDNode* Expr)

Description

Build and insert a DBG_VALUE instructions specifying that \p Variable is given by \p C (suitably modified by \p Expr).

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:408

Parameters

const llvm::Constant& C
const llvm::MDNode* Variable
const llvm::MDNode* Expr

¶virtual llvm::MachineInstrBuilder buildConstant(
    const llvm::DstOp& Res,
    const llvm::ConstantInt& Val)

Description

Build and insert \p Res = G_CONSTANT \p Val G_CONSTANT is an integer constant with the specified size and value. \p Val will be extended or truncated to the size of \p Reg.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:815

Parameters

const llvm::DstOp& Res
const llvm::ConstantInt& Val

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildConstant(
    const llvm::DstOp& Res,
    int64_t Val)

Description

Build and insert \p Res = G_CONSTANT \p Val G_CONSTANT is an integer constant with the specified size and value.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:826

Parameters

const llvm::DstOp& Res
int64_t Val

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildConstant(
    const llvm::DstOp& Res,
    const llvm::APInt& Val)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:827

Parameters

const llvm::DstOp& Res
const llvm::APInt& Val

¶llvm::MachineInstrBuilder buildCopy(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op)

Description

Build and insert \p Res = COPY Op Register-to-register COPY sets \p Res to \p Op.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:851

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildDbgLabel(
    const llvm::MDNode* Label)

Description

Build and insert a DBG_LABEL instructions specifying that \p Label is given. Convert "llvm.dbg.label Label" to "DBG_LABEL Label".

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:414

Parameters

const llvm::MDNode* Label

¶llvm::MachineInstrBuilder
buildDeleteTrailingVectorElements(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op0)

Description

Build and insert a, b, ..., x, y, z = G_UNMERGE_VALUES \p Op0 \p Res = G_BUILD_VECTOR a, b, ..., x Delete trailing elements in \p Op0 to match number of elements in \p Res.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:532

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op0

Returns

a MachineInstrBuilder for the newly created build vector instr.

¶llvm::MachineInstrBuilder buildDirectDbgValue(
    llvm::Register Reg,
    const llvm::MDNode* Variable,
    const llvm::MDNode* Expr)

Description

Build and insert a DBG_VALUE instruction expressing the fact that the associated \p Variable lives in \p Reg (suitably modified by \p Expr).

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:390

Parameters

llvm::Register Reg
const llvm::MDNode* Variable
const llvm::MDNode* Expr

¶llvm::MachineInstrBuilder buildDynStackAlloc(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Size,
    llvm::Align Alignment)

Description

Build and insert \p Res = G_DYN_STACKALLOC \p Size, \p Align G_DYN_STACKALLOC does a dynamic stack allocation and writes the address of the allocated memory into \p Res.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:424

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Size
llvm::Align Alignment

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildExtOrTrunc(
    unsigned int ExtOpc,
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op)

Description

Build and insert \p Res = \p ExtOpc, \p Res = G_TRUNC \p Op, or \p Res = COPY \p Op depending on the differing sizes of \p Res and\p Op. ///

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:746

Parameters

unsigned int ExtOpc
const llvm::DstOp& Res
const llvm::SrcOp& Op

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildExtract(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Src,
    uint64_t Index)

Description

Build and insert `Res0, ... = G_EXTRACT Src, Idx0`.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:954

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Src
uint64_t Index

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder
buildExtractVectorElement(const llvm::DstOp& Res,
                          const llvm::SrcOp& Val,
                          const llvm::SrcOp& Idx)

Description

Build and insert \p Res = G_EXTRACT_VECTOR_ELT \p Val, \p Idx

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1171

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Val
const llvm::SrcOp& Idx

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildFAbs(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_FABS \p Op0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1706

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFAdd(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_FADD \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1665

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFCanonicalize(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Dst = G_FCANONICALIZE \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1712

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFCmp(
    CmpInst::Predicate Pred,
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op0,
    const llvm::SrcOp& Op1,
    Optional<unsigned int> Flags = None)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1130

Parameters

CmpInst::Predicate Pred
const llvm::DstOp& Res
const llvm::SrcOp& Op0
const llvm::SrcOp& Op1
Optional<unsigned int> Flags = None

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildFConstant(
    const llvm::DstOp& Res,
    const llvm::APFloat& Val)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:842

Parameters

const llvm::DstOp& Res
const llvm::APFloat& Val

¶llvm::MachineInstrBuilder buildFConstant(
    const llvm::DstOp& Res,
    double Val)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:841

Parameters

const llvm::DstOp& Res
double Val

¶virtual llvm::MachineInstrBuilder buildFConstant(
    const llvm::DstOp& Res,
    const llvm::ConstantFP& Val)

Description

Build and insert \p Res = G_FCONSTANT \p Val G_FCONSTANT is a floating-point constant with the specified size and value.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:838

Parameters

const llvm::DstOp& Res
const llvm::ConstantFP& Val

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildFCopysign(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1)

Description

Build and insert \p Res = G_FCOPYSIGN \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1755

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1

¶llvm::MachineInstrBuilder buildFDiv(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_FDIV \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1679

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFExp2(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Dst = G_FEXP2 \p Src

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1742

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFFloor(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = GFFLOOR \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1724

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFIDbgValue(
    int FI,
    const llvm::MDNode* Variable,
    const llvm::MDNode* Expr)

Description

Build and insert a DBG_VALUE instruction expressing the fact that the associated \p Variable lives in the stack slot specified by \p FI (suitably modified by \p Expr).

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:403

Parameters

int FI
const llvm::MDNode* Variable
const llvm::MDNode* Expr

¶llvm::MachineInstrBuilder buildFLog(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Dst = G_FLOG \p Src

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1730

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFLog2(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Dst = G_FLOG2 \p Src

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1736

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFMA(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    const llvm::SrcOp& Src2,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1686

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
const llvm::SrcOp& Src2
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFMAD(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    const llvm::SrcOp& Src2,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_FMAD \p Op0, \p Op1, \p Op2

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1693

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
const llvm::SrcOp& Src2
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFMaxNum(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1544

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFMaxNumIEEE(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1556

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFMinNum(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1538

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFMinNumIEEE(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1550

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFMul(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1532

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFNeg(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_FNEG \p Op0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1700

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFPExt(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_FPEXT \p Op

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:651

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFPTOSI(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0)

Description

Build and insert \p Res = G_FPTOSI \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1776

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0

¶llvm::MachineInstrBuilder buildFPTOUI(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0)

Description

Build and insert \p Res = G_FPTOUI \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1771

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0

¶llvm::MachineInstrBuilder buildFPTrunc(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_FPTRUNC \p Op G_FPTRUNC converts a floating-point value into one with a smaller type.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1087

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op
Optional<unsigned int> Flags = None

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildFPow(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Dst = G_FPOW \p Src0, \p Src1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1748

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFSub(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_FSUB \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1672

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildFence(
    unsigned int Ordering,
    unsigned int Scope)

Description

Build and insert `G_FENCE Ordering, Scope`.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1446

Parameters

unsigned int Ordering
unsigned int Scope

¶llvm::MachineInstrBuilder buildFrameIndex(
    const llvm::DstOp& Res,
    int Idx)

Description

Build and insert \p Res = G_FRAME_INDEX \p Idx G_FRAME_INDEX materializes the address of an alloca value or other stack-based object.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:436

Parameters

const llvm::DstOp& Res
int Idx

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildFreeze(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert \p Dst = G_FREEZE \p Src

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1449

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildGlobalValue(
    const llvm::DstOp& Res,
    const llvm::GlobalValue* GV)

Description

Build and insert \p Res = G_GLOBAL_VALUE \p GV G_GLOBAL_VALUE materializes the address of the specified global into \p Res.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:448

Parameters

const llvm::DstOp& Res
const llvm::GlobalValue* GV

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildICmp(
    CmpInst::Predicate Pred,
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op0,
    const llvm::SrcOp& Op1)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1115

Parameters

CmpInst::Predicate Pred
const llvm::DstOp& Res
const llvm::SrcOp& Op0
const llvm::SrcOp& Op1

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildIndirectDbgValue(
    llvm::Register Reg,
    const llvm::MDNode* Variable,
    const llvm::MDNode* Expr)

Description

Build and insert a DBG_VALUE instruction expressing the fact that the associated \p Variable lives in memory at \p Reg (suitably modified by \p Expr).

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:396

Parameters

llvm::Register Reg
const llvm::MDNode* Variable
const llvm::MDNode* Expr

¶llvm::MachineInstrBuilder buildInsert(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Src,
    const llvm::SrcOp& Op,
    unsigned int Index)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1059

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Src
const llvm::SrcOp& Op
unsigned int Index

¶llvm::MachineInstrBuilder
buildInsertVectorElement(const llvm::DstOp& Res,
                         const llvm::SrcOp& Val,
                         const llvm::SrcOp& Elt,
                         const llvm::SrcOp& Idx)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1158

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Val
const llvm::SrcOp& Elt
const llvm::SrcOp& Idx

Returns

The newly created instruction.

¶virtual llvm::MachineInstrBuilder buildInstr(
    unsigned int Opc,
    ArrayRef<llvm::DstOp> DstOps,
    ArrayRef<llvm::SrcOp> SrcOps,
    Optional<unsigned int> Flags = None)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1962

Parameters

unsigned int Opc
ArrayRef<llvm::DstOp> DstOps
ArrayRef<llvm::SrcOp> SrcOps
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildInstr(
    unsigned int Opcode)

Description

Build and insert <empty > = \p Opcode <empty >. The insertion point is the one set by the last call of either setBasicBlock or setMI.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:374

Parameters

unsigned int Opcode

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildInstrNoInsert(
    unsigned int Opcode)

Description

Build but don't insert <empty > = \p Opcode <empty >.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:383

Parameters

unsigned int Opcode

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildIntToPtr(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert a G_INTTOPTR instruction.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:663

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildIntrinsic(
    Intrinsic::ID ID,
    ArrayRef<llvm::Register> Res,
    bool HasSideEffects)

Description

Build and insert either a G_INTRINSIC (if \p HasSideEffects is false) or G_INTRINSIC_W_SIDE_EFFECTS instruction. Its first operand will be the result register definition unless \p Reg is NoReg (== 0). The second operand will be the intrinsic's ID. Callers are expected to add the required definitions and uses afterwards.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1072

Parameters

Intrinsic::ID ID
ArrayRef<llvm::Register> Res
bool HasSideEffects

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildIntrinsic(
    Intrinsic::ID ID,
    ArrayRef<llvm::DstOp> Res,
    bool HasSideEffects)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1074

Parameters

Intrinsic::ID ID
ArrayRef<llvm::DstOp> Res
bool HasSideEffects

¶llvm::MachineInstrBuilder buildIntrinsicTrunc(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Dst = G_INTRINSIC_TRUNC \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1718

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildJumpTable(
    const llvm::LLT PtrTy,
    unsigned int JTI)

Description

Build and insert \p Res = G_JUMP_TABLE \p JTI G_JUMP_TABLE sets \p Res to the address of the jump table specified by the jump table index \p JTI.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1815

Parameters

const llvm::LLT PtrTy
unsigned int JTI

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildLShr(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1568

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildLoad(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Addr,
    llvm::MachinePointerInfo PtrInfo,
    llvm::Align Alignment,
    MachineMemOperand::Flags MMOFlags =
        MachineMemOperand::MONone,
    const llvm::AAMDNodes& AAInfo =
        llvm::AAMDNodes())

Description

Build and insert a G_LOAD instruction, while constructing the MachineMemOperand.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:903

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Addr
llvm::MachinePointerInfo PtrInfo
llvm::Align Alignment
MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone
const llvm::AAMDNodes& AAInfo = llvm::AAMDNodes()

¶llvm::MachineInstrBuilder buildLoad(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Addr,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `Res = G_LOAD Addr, MMO`. Loads the value stored at \p Addr. Puts the result in \p Res.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:895

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Addr
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildLoadFromOffset(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& BasePtr,
    llvm::MachineMemOperand& BaseMMO,
    int64_t Offset)

Description

Helper to create a load from a constant offset given a base address. Load the type of \p Dst from \p Offset from the given base address and memory operand.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:923

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& BasePtr
llvm::MachineMemOperand& BaseMMO
int64_t Offset

¶llvm::MachineInstrBuilder buildLoadInstr(
    unsigned int Opcode,
    const llvm::DstOp& Res,
    const llvm::SrcOp& Addr,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `Res = <opcode > Addr, MMO`. Loads the value stored at \p Addr. Puts the result in \p Res.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:917

Parameters

unsigned int Opcode
const llvm::DstOp& Res
const llvm::SrcOp& Addr
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildMaskLowPtrBits(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op0,
    uint32_t NumBits)

Description

Build and insert \p Res = G_PTRMASK \p Op0, \p G_CONSTANT (1 < < NumBits) - 1 This clears the low bits of a pointer operand without destroying its pointer properties. This has the effect of rounding the address *down* to a specified alignment in bits.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:504

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op0
uint32_t NumBits

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildMemCpy(
    const llvm::SrcOp& DstPtr,
    const llvm::SrcOp& SrcPtr,
    const llvm::SrcOp& Size,
    llvm::MachineMemOperand& DstMMO,
    llvm::MachineMemOperand& SrcMMO)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1926

Parameters

const llvm::SrcOp& DstPtr
const llvm::SrcOp& SrcPtr
const llvm::SrcOp& Size
llvm::MachineMemOperand& DstMMO
llvm::MachineMemOperand& SrcMMO

¶llvm::MachineInstrBuilder buildMemTransferInst(
    unsigned int Opcode,
    const llvm::SrcOp& DstPtr,
    const llvm::SrcOp& SrcPtr,
    const llvm::SrcOp& Size,
    llvm::MachineMemOperand& DstMMO,
    llvm::MachineMemOperand& SrcMMO)

Description

Build and insert G_MEMCPY or G_MEMMOVE

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1914

Parameters

unsigned int Opcode
const llvm::SrcOp& DstPtr
const llvm::SrcOp& SrcPtr
const llvm::SrcOp& Size
llvm::MachineMemOperand& DstMMO
llvm::MachineMemOperand& SrcMMO

¶llvm::MachineInstrBuilder buildMerge(
    const llvm::DstOp& Res,
    ArrayRef<llvm::Register> Ops)

Description

Build and insert \p Res = G_MERGE_VALUES \p Op0, ... G_MERGE_VALUES combines the input elements contiguously into a larger register.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:970

Parameters

const llvm::DstOp& Res
ArrayRef<llvm::Register> Ops

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildMerge(
    const llvm::DstOp& Res,
    std::initializer_list<SrcOp> Ops)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:971

Parameters

const llvm::DstOp& Res
std::initializer_list<SrcOp> Ops

¶llvm::MachineInstrBuilder buildMul(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_MUL \p Op0, \p Op1 G_MUL sets \p Res to the product of integer parameters \p Op0 and \p Op1, truncated to their width.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1507

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildNeg(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0)

Description

Build and insert integer negation\p Zero = G_CONSTANT 0\p Res = G_SUB Zero, \p Op0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1629

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0

¶llvm::MachineInstrBuilder buildNot(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0)

Description

Build and insert a bitwise not,\p NegOne = G_CONSTANT -1\p Res = G_OR \p Op0, NegOne

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1621

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0

¶llvm::MachineInstrBuilder buildOr(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_OR \p Op0, \p Op1 G_OR sets \p Res to the bitwise or of integer parameters \p Op0 and \p Op1.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1606

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder
buildPadVectorWithUndefElements(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op0)

Description

Build and insert a, b, ..., x = G_UNMERGE_VALUES \p Op0 \p Res = G_BUILD_VECTOR a, b, ..., x, undef, ..., undef Pad \p Op0 with undef elements to match number of elements in \p Res.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:518

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op0

Returns

a MachineInstrBuilder for the newly created build vector instr.

¶llvm::MachineInstrBuilder buildPtrAdd(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op0,
    const llvm::SrcOp& Op1)

Description

Build and insert \p Res = G_PTR_ADD \p Op0, \p Op1 G_PTR_ADD adds \p Op1 addressible units to the pointer specified by \p Op0, storing the resulting pointer in \p Res. Addressible units are typically bytes but this can vary between targets.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:462

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op0
const llvm::SrcOp& Op1

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildPtrMask(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op0,
    const llvm::SrcOp& Op1)

Description

Build and insert \p Res = G_PTRMASK \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:486

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op0
const llvm::SrcOp& Op1

¶llvm::MachineInstrBuilder buildPtrToInt(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert a G_PTRTOINT instruction.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:658

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildRotateLeft(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src,
    const llvm::SrcOp& Amt)

Description

Build and insert \p Dst = G_ROTL \p Src, \p Amt

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1952

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src
const llvm::SrcOp& Amt

¶llvm::MachineInstrBuilder buildRotateRight(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src,
    const llvm::SrcOp& Amt)

Description

Build and insert \p Dst = G_ROTR \p Src, \p Amt

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1946

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src
const llvm::SrcOp& Amt

¶llvm::MachineInstrBuilder buildSAdde(
    const llvm::DstOp& Res,
    const llvm::DstOp& CarryOut,
    const llvm::SrcOp& Op0,
    const llvm::SrcOp& Op1,
    const llvm::SrcOp& CarryIn)

Description

Build and insert \p Res, \p CarryOut = G_SADDE \p Op0, \p Op1, \p CarryInp

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:600

Parameters

const llvm::DstOp& Res
const llvm::DstOp& CarryOut
const llvm::SrcOp& Op0
const llvm::SrcOp& Op1
const llvm::SrcOp& CarryIn

¶llvm::MachineInstrBuilder buildSAddo(
    const llvm::DstOp& Res,
    const llvm::DstOp& CarryOut,
    const llvm::SrcOp& Op0,
    const llvm::SrcOp& Op1)

Description

Build and insert \p Res, \p CarryOut = G_SADDO \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:559

Parameters

const llvm::DstOp& Res
const llvm::DstOp& CarryOut
const llvm::SrcOp& Op0
const llvm::SrcOp& Op1

¶llvm::MachineInstrBuilder buildSExt(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op)

Description

Build and insert \p Res = G_SEXT \p Op G_SEXT produces a register of the specified width, with bits 0 to sizeof(\p Ty) * 8 set to \p Op. The remaining bits are duplicated from the high bit of \p Op (i.e. 2s-complement sign extended).

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:643

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildSExtInReg(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op,
    int64_t ImmOp)

Description

Build and insert \p Res = G_SEXT_INREG \p Op, ImmOp

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:646

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op
int64_t ImmOp

¶llvm::MachineInstrBuilder buildSExtOrTrunc(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op)

Description

Build and insert \p Res = G_SEXT \p Op, \p Res = G_TRUNC \p Op, or\p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op. ///

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:715

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildSITOFP(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0)

Description

Build and insert \p Res = G_SITOFP \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1766

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0

¶llvm::MachineInstrBuilder buildSMax(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1)

Description

Build and insert \p Res = G_SMAX \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1787

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1

¶llvm::MachineInstrBuilder buildSMin(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1)

Description

Build and insert \p Res = G_SMIN \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1781

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1

¶llvm::MachineInstrBuilder buildSMulH(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1519

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildSSube(
    const llvm::DstOp& Res,
    const llvm::DstOp& CarryOut,
    const llvm::SrcOp& Op0,
    const llvm::SrcOp& Op1,
    const llvm::SrcOp& CarryIn)

Description

Build and insert \p Res, \p CarryOut = G_SSUBE \p Op0, \p Op1, \p CarryInp

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:608

Parameters

const llvm::DstOp& Res
const llvm::DstOp& CarryOut
const llvm::SrcOp& Op0
const llvm::SrcOp& Op1
const llvm::SrcOp& CarryIn

¶llvm::MachineInstrBuilder buildSSubo(
    const llvm::DstOp& Res,
    const llvm::DstOp& CarryOut,
    const llvm::SrcOp& Op0,
    const llvm::SrcOp& Op1)

Description

Build and insert \p Res, \p CarryOut = G_SUBO \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:565

Parameters

const llvm::DstOp& Res
const llvm::DstOp& CarryOut
const llvm::SrcOp& Op0
const llvm::SrcOp& Op1

¶llvm::MachineInstrBuilder buildSbfx(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src,
    const llvm::SrcOp& LSB,
    const llvm::SrcOp& Width)

Description

Build and insert \p Dst = G_SBFX \p Src, \p LSB, \p Width.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1934

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src
const llvm::SrcOp& LSB
const llvm::SrcOp& Width

¶llvm::MachineInstrBuilder buildSelect(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Tst,
    const llvm::SrcOp& Op0,
    const llvm::SrcOp& Op1,
    Optional<unsigned int> Flags = None)

Description

Build and insert a \p Res = G_SELECT \p Tst, \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1144

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Tst
const llvm::SrcOp& Op0
const llvm::SrcOp& Op1
Optional<unsigned int> Flags = None

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildShl(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1562

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildShuffleSplat(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Src)

Description

Build and insert a vector splat of a scalar \p Src using a G_INSERT_VECTOR_ELT and G_SHUFFLE_VECTOR idiom.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1035

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Src

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildShuffleVector(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Src1,
    const llvm::SrcOp& Src2,
    ArrayRef<int> Mask)

Description

Build and insert \p Res = G_SHUFFLE_VECTOR \p Src1, \p Src2, \p Mask

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1042

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Src1
const llvm::SrcOp& Src2
ArrayRef<int> Mask

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildSplatVector(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Src)

Description

Build and insert \p Res = G_BUILD_VECTOR with \p Src replicated to fill the number of elements

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1009

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildStore(
    const llvm::SrcOp& Val,
    const llvm::SrcOp& Addr,
    llvm::MachineMemOperand& MMO)

Description

Build and insert `G_STORE Val, Addr, MMO`. Stores the value \p Val to \p Addr.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:937

Parameters

const llvm::SrcOp& Val
const llvm::SrcOp& Addr
llvm::MachineMemOperand& MMO

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildStore(
    const llvm::SrcOp& Val,
    const llvm::SrcOp& Addr,
    llvm::MachinePointerInfo PtrInfo,
    llvm::Align Alignment,
    MachineMemOperand::Flags MMOFlags =
        MachineMemOperand::MONone,
    const llvm::AAMDNodes& AAInfo =
        llvm::AAMDNodes())

Description

Build and insert a G_STORE instruction, while constructing the MachineMemOperand.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:943

Parameters

const llvm::SrcOp& Val
const llvm::SrcOp& Addr
llvm::MachinePointerInfo PtrInfo
llvm::Align Alignment
MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone
const llvm::AAMDNodes& AAInfo = llvm::AAMDNodes()

¶llvm::MachineInstrBuilder buildSub(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_SUB \p Op0, \p Op1 G_SUB sets \p Res to the difference of integer parameters \p Op0 and\p Op1, truncated to their width.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1491

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildTrunc(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op)

Description

Build and insert \p Res = G_TRUNC \p Op G_TRUNC extracts the low bits of a type. For a vector type each element is truncated independently before being packed into the destination.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1101

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildUAdde(
    const llvm::DstOp& Res,
    const llvm::DstOp& CarryOut,
    const llvm::SrcOp& Op0,
    const llvm::SrcOp& Op1,
    const llvm::SrcOp& CarryIn)

Description

Build and insert \p Res, \p CarryOut = G_UADDE \p Op0, \p Op1, \p CarryIn G_UADDE sets \p Res to \p Op0 + \p Op1 + \p CarryIn (truncated to the bit width) and sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:584

Parameters

const llvm::DstOp& Res
const llvm::DstOp& CarryOut
const llvm::SrcOp& Op0
const llvm::SrcOp& Op1
const llvm::SrcOp& CarryIn

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildUAddo(
    const llvm::DstOp& Res,
    const llvm::DstOp& CarryOut,
    const llvm::SrcOp& Op0,
    const llvm::SrcOp& Op1)

Description

Build and insert \p Res, \p CarryOut = G_UADDO \p Op0, \p Op1 G_UADDO sets \p Res to \p Op0 + \p Op1 (truncated to the bit width) and sets \p CarryOut to 1 if the result overflowed in unsigned arithmetic.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:547

Parameters

const llvm::DstOp& Res
const llvm::DstOp& CarryOut
const llvm::SrcOp& Op0
const llvm::SrcOp& Op1

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildUITOFP(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0)

Description

Build and insert \p Res = G_UITOFP \p Src0

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1761

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0

¶llvm::MachineInstrBuilder buildUMax(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1)

Description

Build and insert \p Res = G_UMAX \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1799

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1

¶llvm::MachineInstrBuilder buildUMin(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1)

Description

Build and insert \p Res = G_UMIN \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1793

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1

¶llvm::MachineInstrBuilder buildUMulH(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1513

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildURem(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1,
    Optional<unsigned int> Flags = None)

Description

Build and insert \p Res = G_UREM \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1526

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1
Optional<unsigned int> Flags = None

¶llvm::MachineInstrBuilder buildUSube(
    const llvm::DstOp& Res,
    const llvm::DstOp& CarryOut,
    const llvm::SrcOp& Op0,
    const llvm::SrcOp& Op1,
    const llvm::SrcOp& CarryIn)

Description

Build and insert \p Res, \p CarryOut = G_USUBE \p Op0, \p Op1, \p CarryInp

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:592

Parameters

const llvm::DstOp& Res
const llvm::DstOp& CarryOut
const llvm::SrcOp& Op0
const llvm::SrcOp& Op1
const llvm::SrcOp& CarryIn

¶llvm::MachineInstrBuilder buildUSubo(
    const llvm::DstOp& Res,
    const llvm::DstOp& CarryOut,
    const llvm::SrcOp& Op0,
    const llvm::SrcOp& Op1)

Description

Build and insert \p Res, \p CarryOut = G_USUBO \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:553

Parameters

const llvm::DstOp& Res
const llvm::DstOp& CarryOut
const llvm::SrcOp& Op0
const llvm::SrcOp& Op1

¶llvm::MachineInstrBuilder buildUbfx(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src,
    const llvm::SrcOp& LSB,
    const llvm::SrcOp& Width)

Description

Build and insert \p Dst = G_UBFX \p Src, \p LSB, \p Width.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1940

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src
const llvm::SrcOp& LSB
const llvm::SrcOp& Width

¶llvm::MachineInstrBuilder buildUndef(
    const llvm::DstOp& Res)

Description

Build and insert \p Res = IMPLICIT_DEF.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:957

Parameters

const llvm::DstOp& Res

¶llvm::MachineInstrBuilder buildUnmerge(
    llvm::LLT Res,
    const llvm::SrcOp& Op)

Description

Build and insert an unmerge of \p Res sized pieces to cover \p Op

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:988

Parameters

llvm::LLT Res
const llvm::SrcOp& Op

¶llvm::MachineInstrBuilder buildUnmerge(
    ArrayRef<llvm::Register> Res,
    const llvm::SrcOp& Op)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:985

Parameters

ArrayRef<llvm::Register> Res
const llvm::SrcOp& Op

¶llvm::MachineInstrBuilder buildUnmerge(
    ArrayRef<llvm::LLT> Res,
    const llvm::SrcOp& Op)

Description

Build and insert \p Res0, ... = G_UNMERGE_VALUES \p Op G_UNMERGE_VALUES splits contiguous bits of the input into multiple

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:984

Parameters

ArrayRef<llvm::LLT> Res
const llvm::SrcOp& Op

Returns

a MachineInstrBuilder for the newly created instruction.

¶llvm::MachineInstrBuilder buildVecReduceAdd(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert \p Res = G_VECREDUCE_ADD \p Src

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1869

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildVecReduceAnd(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert \p Res = G_VECREDUCE_AND \p Src

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1879

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildVecReduceFAdd(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& ScalarIn,
    const llvm::SrcOp& VecIn)

Description

Build and insert \p Res = G_VECREDUCE_FADD \p Src \p ScalarIn is the scalar accumulator input to the reduction operation of\p VecIn.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1843

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& ScalarIn
const llvm::SrcOp& VecIn

¶llvm::MachineInstrBuilder buildVecReduceFMax(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert \p Res = G_VECREDUCE_FMAX \p Src

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1860

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildVecReduceFMin(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert \p Res = G_VECREDUCE_FMIN \p Src

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1865

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildVecReduceFMul(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& ScalarIn,
    const llvm::SrcOp& VecIn)

Description

Build and insert \p Res = G_VECREDUCE_FMUL \p Src \p ScalarIn is the scalar accumulator input to the reduction operation of\p VecIn.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1853

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& ScalarIn
const llvm::SrcOp& VecIn

¶llvm::MachineInstrBuilder buildVecReduceMul(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert \p Res = G_VECREDUCE_MUL \p Src

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1874

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildVecReduceOr(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert \p Res = G_VECREDUCE_OR \p Src

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1884

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildVecReduceSMax(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert \p Res = G_VECREDUCE_SMAX \p Src

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1894

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildVecReduceSMin(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert \p Res = G_VECREDUCE_SMIN \p Src

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1899

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildVecReduceSeqFAdd(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& ScalarIn,
    const llvm::SrcOp& VecIn)

Description

Build and insert \p Res = G_VECREDUCE_SEQ_FADD \p ScalarIn, \p VecIn \p ScalarIn is the scalar accumulator input to start the sequential reduction operation of \p VecIn.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1821

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& ScalarIn
const llvm::SrcOp& VecIn

¶llvm::MachineInstrBuilder buildVecReduceSeqFMul(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& ScalarIn,
    const llvm::SrcOp& VecIn)

Description

Build and insert \p Res = G_VECREDUCE_SEQ_FMUL \p ScalarIn, \p VecIn \p ScalarIn is the scalar accumulator input to start the sequential reduction operation of \p VecIn.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1832

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& ScalarIn
const llvm::SrcOp& VecIn

¶llvm::MachineInstrBuilder buildVecReduceUMax(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert \p Res = G_VECREDUCE_UMAX \p Src

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1904

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildVecReduceUMin(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert \p Res = G_VECREDUCE_UMIN \p Src

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1909

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildVecReduceXor(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src)

Description

Build and insert \p Res = G_VECREDUCE_XOR \p Src

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1889

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src

¶llvm::MachineInstrBuilder buildXor(
    const llvm::DstOp& Dst,
    const llvm::SrcOp& Src0,
    const llvm::SrcOp& Src1)

Description

Build and insert \p Res = G_XOR \p Op0, \p Op1

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:1613

Parameters

const llvm::DstOp& Dst
const llvm::SrcOp& Src0
const llvm::SrcOp& Src1

¶llvm::MachineInstrBuilder buildZExt(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op)

Description

Build and insert \p Res = G_ZEXT \p Op G_ZEXT produces a register of the specified width, with bits 0 to sizeof(\p Ty) * 8 set to \p Op. The remaining bits are 0. For a vector register, each element is extended individually.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:705

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op

Returns

The newly created instruction.

¶llvm::MachineInstrBuilder buildZExtInReg(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op,
    int64_t ImmOp)

Description

Build and inserts \p Res = \p G_AND \p Op, \p LowBitsSet(ImmOp) Since there is no G_ZEXT_INREG like G_SEXT_INREG, the instruction is emulated using G_AND.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:752

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op
int64_t ImmOp

¶llvm::MachineInstrBuilder buildZExtOrTrunc(
    const llvm::DstOp& Res,
    const llvm::SrcOp& Op)

Description

Build and insert \p Res = G_ZEXT \p Op, \p Res = G_TRUNC \p Op, or\p Res = COPY \p Op depending on the differing sizes of \p Res and \p Op. ///

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:725

Parameters

const llvm::DstOp& Res
const llvm::SrcOp& Op

Returns

The newly created instruction.

¶unsigned int getBoolExtOp(bool IsVec,
                          bool IsFP) const

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:679

Parameters

bool IsVec
bool IsFP

Returns

The opcode of the extension the target wants to use for boolean values.

¶llvm::GISelCSEInfo* getCSEInfo()

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:304

¶const llvm::GISelCSEInfo* getCSEInfo() const

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:305

¶const llvm::DebugLoc& getDL()

Description

Getter for DebugLoc

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:284

¶const llvm::DataLayout& getDataLayout() const

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:279

¶const llvm::DebugLoc& getDebugLoc()

Description

Get the current instruction's debug location.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:365

¶MachineBasicBlock::iterator getInsertPt()

Description

Current insertion point for new instructions.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:308

¶llvm::MachineBasicBlock& getMBB()

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:299

¶const llvm::MachineBasicBlock& getMBB() const

Description

Getter for the basic block we currently build.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:294

¶llvm::MachineFunction& getMF()

Description

Getter for the function we currently build.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:269

¶const llvm::MachineFunction& getMF() const

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:274

¶llvm::MachineRegisterInfo* getMRI()

Description

Getter for MRI

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:287

¶const llvm::MachineRegisterInfo* getMRI() const

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:288

¶llvm::MachineIRBuilderState& getState()

Description

Getter for the State

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:291

¶const llvm::TargetInstrInfo& getTII()

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:263

¶llvm::MachineInstrBuilder insertInstr(
    llvm::MachineInstrBuilder MIB)

Description

Insert an existing instruction at the insertion point.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:386

Parameters

llvm::MachineInstrBuilder MIB

¶Optional<llvm::MachineInstrBuilder>
materializePtrAdd(llvm::Register& Res,
                  llvm::Register Op0,
                  const llvm::LLT ValueTy,
                  uint64_t Value)

Description

Materialize and insert \p Res = G_PTR_ADD \p Op0, (G_CONSTANT \p Value) G_PTR_ADD adds \p Value bytes to the pointer specified by \p Op0, storing the resulting pointer in \p Res. If \p Value is zero then no G_PTR_ADD or G_CONSTANT will be created and

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:481

Parameters

llvm::Register& Res
llvm::Register Op0
const llvm::LLT ValueTy
uint64_t Value

Returns

a MachineInstrBuilder for the newly created instruction.

¶void recordInsertion(
    llvm::MachineInstr* InsertedInstr) const

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:233

Parameters

llvm::MachineInstr* InsertedInstr

¶void setCSEInfo(llvm::GISelCSEInfo* Info)

Description

@ }

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:322

Parameters

llvm::GISelCSEInfo* Info

¶void setChangeObserver(
    llvm::GISelChangeObserver& Observer)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:354

Parameters

llvm::GISelChangeObserver& Observer

¶void setDebugLoc(const llvm::DebugLoc& DL)

Description

Set the debug location to \p DL for all the next build instructions.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:362

Parameters

const llvm::DebugLoc& DL

¶void setInsertPt(llvm::MachineBasicBlock& MBB,
                 MachineBasicBlock::iterator II)

Description

Set the insertion point before the specified position.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:313

Parameters

llvm::MachineBasicBlock& MBB
MachineBasicBlock::iterator II

¶void setInstr(llvm::MachineInstr& MI)

Description

Set the insertion point to before MI.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:340

Parameters

llvm::MachineInstr& MI

¶void setInstrAndDebugLoc(llvm::MachineInstr& MI)

Description

Set the insertion point to before MI, and set the debug loc to MI's loc.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:349

Parameters

llvm::MachineInstr& MI

¶void setMBB(llvm::MachineBasicBlock& MBB)

Description

Set the insertion point to the end of \p MBB.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:331

Parameters

llvm::MachineBasicBlock& MBB

¶void setMF(llvm::MachineFunction& MF)

Description

@ { Set the MachineFunction where to build instructions.

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:327

Parameters

llvm::MachineFunction& MF

¶void stopObservingChanges()

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:358

¶void validateBinaryOp(const llvm::LLT Res,
                      const llvm::LLT Op0,
                      const llvm::LLT Op1)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:227

Parameters

const llvm::LLT Res
const llvm::LLT Op0
const llvm::LLT Op1

¶void validateSelectOp(const llvm::LLT ResTy,
                      const llvm::LLT TstTy,
                      const llvm::LLT Op0Ty,
                      const llvm::LLT Op1Ty)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:230

Parameters

const llvm::LLT ResTy
const llvm::LLT TstTy
const llvm::LLT Op0Ty
const llvm::LLT Op1Ty

¶void validateShiftOp(const llvm::LLT Res,
                     const llvm::LLT Op0,
                     const llvm::LLT Op1)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:228

Parameters

const llvm::LLT Res
const llvm::LLT Op0
const llvm::LLT Op1

¶void validateTruncExt(const llvm::LLT Dst,
                      const llvm::LLT Src,
                      bool IsExtend)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:224

Parameters

const llvm::LLT Dst
const llvm::LLT Src
bool IsExtend

¶void validateUnaryOp(const llvm::LLT Res,
                     const llvm::LLT Op0)

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:226

Parameters

const llvm::LLT Res
const llvm::LLT Op0

¶virtual ~MachineIRBuilder()

Declared at: llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h:259

class MachineIRBuilder

Declaration

Description

Member Variables

Method Overview

Methods

¶MachineIRBuilder()

Description

¶MachineIRBuilder(llvm::MachineFunction& MF)

Parameters

¶MachineIRBuilder( llvm::MachineBasicBlock& MBB, MachineBasicBlock::iterator InsPt)

Parameters

¶MachineIRBuilder(llvm::MachineInstr& MI)

Parameters

¶MachineIRBuilder( llvm::MachineInstr& MI, llvm::GISelChangeObserver& Observer)

Parameters

¶MachineIRBuilder( const llvm::MachineIRBuilderState& BState)

Parameters

¶llvm::MachineInstrBuilder buildAShr( const llvm::DstOp& Dst, const llvm::SrcOp& Src0, const llvm::SrcOp& Src1, Optional<unsigned int> Flags = None)

Parameters

¶llvm::MachineInstrBuilder buildAbs( const llvm::DstOp& Dst, const llvm::SrcOp& Src)

Description

Parameters

¶llvm::MachineInstrBuilder buildAdd( const llvm::DstOp& Dst, const llvm::SrcOp& Src0, const llvm::SrcOp& Src1, Optional<unsigned int> Flags = None)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAddrSpaceCast( const llvm::DstOp& Dst, const llvm::SrcOp& Src)

Description

Parameters

¶llvm::MachineInstrBuilder buildAnd( const llvm::DstOp& Dst, const llvm::SrcOp& Src0, const llvm::SrcOp& Src1)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAnyExt( const llvm::DstOp& Res, const llvm::SrcOp& Op)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAnyExtOrTrunc( const llvm::DstOp& Res, const llvm::SrcOp& Op)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAssertAlign( const llvm::DstOp& Res, const llvm::SrcOp& Op, llvm::Align AlignVal)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAssertOp( unsigned int Opc, const llvm::DstOp& Res, const llvm::SrcOp& Op, unsigned int Val)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAssertSExt( const llvm::DstOp& Res, const llvm::SrcOp& Op, unsigned int Size)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAssertZExt( const llvm::DstOp& Res, const llvm::SrcOp& Op, unsigned int Size)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAtomicCmpXchg( llvm::Register OldValRes, llvm::Register Addr, llvm::Register CmpVal, llvm::Register NewVal, llvm::MachineMemOperand& MMO)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAtomicCmpXchgWithSuccess( llvm::Register OldValRes, llvm::Register SuccessRes, llvm::Register Addr, llvm::Register CmpVal, llvm::Register NewVal, llvm::MachineMemOperand& MMO)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAtomicRMW( unsigned int Opcode, const llvm::DstOp& OldValRes, const llvm::SrcOp& Addr, const llvm::SrcOp& Val, llvm::MachineMemOperand& MMO)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAtomicRMWAdd( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAtomicRMWAnd( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)

Description

Parameters

Returns

¶llvm::MachineInstrBuilder buildAtomicRMWFAdd( const llvm::DstOp& OldValRes, const llvm::SrcOp& Addr, const llvm::SrcOp& Val, llvm::MachineMemOperand& MMO)

Description

¶`MachineIRBuilder()`

¶`MachineIRBuilder(llvm::MachineFunction& MF)`

¶`MachineIRBuilder( llvm::MachineBasicBlock& MBB, MachineBasicBlock::iterator InsPt)`

¶`MachineIRBuilder(llvm::MachineInstr& MI)`

¶`MachineIRBuilder( llvm::MachineInstr& MI, llvm::GISelChangeObserver& Observer)`

¶`MachineIRBuilder( const llvm::MachineIRBuilderState& BState)`

¶`llvm::MachineInstrBuilder buildAShr( const llvm::DstOp& Dst, const llvm::SrcOp& Src0, const llvm::SrcOp& Src1, Optional<unsigned int> Flags = None)`

¶`llvm::MachineInstrBuilder buildAbs( const llvm::DstOp& Dst, const llvm::SrcOp& Src)`

¶`llvm::MachineInstrBuilder buildAdd( const llvm::DstOp& Dst, const llvm::SrcOp& Src0, const llvm::SrcOp& Src1, Optional<unsigned int> Flags = None)`

¶`llvm::MachineInstrBuilder buildAddrSpaceCast( const llvm::DstOp& Dst, const llvm::SrcOp& Src)`

¶`llvm::MachineInstrBuilder buildAnd( const llvm::DstOp& Dst, const llvm::SrcOp& Src0, const llvm::SrcOp& Src1)`

¶`llvm::MachineInstrBuilder buildAnyExt( const llvm::DstOp& Res, const llvm::SrcOp& Op)`

¶`llvm::MachineInstrBuilder buildAnyExtOrTrunc( const llvm::DstOp& Res, const llvm::SrcOp& Op)`

¶`llvm::MachineInstrBuilder buildAssertAlign( const llvm::DstOp& Res, const llvm::SrcOp& Op, llvm::Align AlignVal)`

¶`llvm::MachineInstrBuilder buildAssertOp( unsigned int Opc, const llvm::DstOp& Res, const llvm::SrcOp& Op, unsigned int Val)`

¶`llvm::MachineInstrBuilder buildAssertSExt( const llvm::DstOp& Res, const llvm::SrcOp& Op, unsigned int Size)`

¶`llvm::MachineInstrBuilder buildAssertZExt( const llvm::DstOp& Res, const llvm::SrcOp& Op, unsigned int Size)`

¶`llvm::MachineInstrBuilder buildAtomicCmpXchg( llvm::Register OldValRes, llvm::Register Addr, llvm::Register CmpVal, llvm::Register NewVal, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicCmpXchgWithSuccess( llvm::Register OldValRes, llvm::Register SuccessRes, llvm::Register Addr, llvm::Register CmpVal, llvm::Register NewVal, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMW( unsigned int Opcode, const llvm::DstOp& OldValRes, const llvm::SrcOp& Addr, const llvm::SrcOp& Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWAdd( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWAnd( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWFAdd( const llvm::DstOp& OldValRes, const llvm::SrcOp& Addr, const llvm::SrcOp& Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWFMax( const llvm::DstOp& OldValRes, const llvm::SrcOp& Addr, const llvm::SrcOp& Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWFMin( const llvm::DstOp& OldValRes, const llvm::SrcOp& Addr, const llvm::SrcOp& Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWFSub( const llvm::DstOp& OldValRes, const llvm::SrcOp& Addr, const llvm::SrcOp& Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWMax( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWMin( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWNand( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWOr( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWSub( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWUmax( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWUmin( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWXchg( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildAtomicRMWXor( llvm::Register OldValRes, llvm::Register Addr, llvm::Register Val, llvm::MachineMemOperand& MMO)`

¶`llvm::MachineInstrBuilder buildBSwap( const llvm::DstOp& Dst, const llvm::SrcOp& Src0)`

¶`llvm::MachineInstrBuilder buildBitReverse( const llvm::DstOp& Dst, const llvm::SrcOp& Src)`

¶`llvm::MachineInstrBuilder buildBitcast( const llvm::DstOp& Dst, const llvm::SrcOp& Src)`

¶`llvm::MachineInstrBuilder buildBlockAddress( llvm::Register Res, const llvm::BlockAddress* BA)`

¶`llvm::MachineInstrBuilder buildBoolExt( const llvm::DstOp& Res, const llvm::SrcOp& Op, bool IsFP)`

¶`llvm::MachineInstrBuilder buildBoolExtInReg( const llvm::DstOp& Res, const llvm::SrcOp& Op, bool IsVector, bool IsFP)`

¶`llvm::MachineInstrBuilder buildBr( llvm::MachineBasicBlock& Dest)`

¶`llvm::MachineInstrBuilder buildBrCond( const llvm::SrcOp& Tst, llvm::MachineBasicBlock& Dest)`