class SMSchedule

Declaration

class SMSchedule { /* full declaration omitted */ };

Description

This class represents the scheduled code. The main data structure is a map from scheduled cycle to instructions. During scheduling, the data structure explicitly represents all stages/iterations. When the algorithm finshes, the schedule is collapsed into a single stage, which represents instructions from different loop iterations. The SMS algorithm allows negative values for cycles, so the first cycle in the schedule is the smallest cycle value.

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:497

Member Variables

private DenseMap<int, std::deque<SUnit*>> ScheduledInstrs
Map from execution cycle to instructions.
private std::map<SUnit*, int> InstrToCycle
Map from instruction to execution cycle.
private int FirstCycle = 0
Keep track of the first cycle value in the schedule. It starts as zero, but the algorithm allows negative values.
private int LastCycle = 0
Keep track of the last cycle value in the schedule.
private int InitiationInterval = 0
The initiation interval (II) for the schedule.
private const llvm::TargetSubtargetInfo& ST
Target machine information.
private llvm::MachineRegisterInfo& MRI
Virtual register information.
private llvm::ResourceManager ProcItinResources

Method Overview

Methods

SMSchedule(llvm::MachineFunction* mf)

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:524

Parameters

llvm::MachineFunction* mf

void computeStart(llvm::SUnit* SU,
                  int* MaxEarlyStart,
                  int* MinLateStart,
                  int* MinEnd,
                  int* MaxStart,
                  int II,
                  llvm::SwingSchedulerDAG* DAG)

Description

Compute the scheduling start slot for the instruction. The start slot depends on any predecessor or successor nodes scheduled already.

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:556

Parameters

llvm::SUnit* SU
int* MaxEarlyStart
int* MinLateStart
int* MinEnd
int* MaxStart
int II
llvm::SwingSchedulerDAG* DAG

SmallSet<llvm::SUnit*, 8>
computeUnpipelineableNodes(
    llvm::SwingSchedulerDAG* SSD,
    TargetInstrInfo::PipelinerLoopInfo* PLI)

Description

Determine transitive dependences of unpipelineable instructions

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:598

Parameters

llvm::SwingSchedulerDAG* SSD
TargetInstrInfo::PipelinerLoopInfo* PLI

unsigned int cycleScheduled(llvm::SUnit* SU) const

Description

Return the cycle for a scheduled instruction. This function normalizes the first cycle to be 0.

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:581

Parameters

llvm::SUnit* SU

void dump() const

Description

Utility function used for debugging to print the schedule.

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:612

int earliestCycleInChain(const llvm::SDep& Dep)

Description

Return the cycle of the earliest scheduled instruction in the dependence chain.

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:550

Parameters

const llvm::SDep& Dep

void finalizeSchedule(
    llvm::SwingSchedulerDAG* SSD)

Description

After the schedule has been formed, call this function to combine the instructions from the different stages/cycles. That is, this function creates a schedule that represents a single iteration.

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:605

Parameters

llvm::SwingSchedulerDAG* SSD

int getFinalCycle() const

Description

Return the last cycle in the finalized schedule.

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:546

int getFirstCycle() const

Description

Return the first cycle in the completed schedule. This can be a negative value.

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:543

int getInitiationInterval() const

Description

Return the initiation interval for this schedule.

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:539

std::deque<SUnit*>& getInstructions(int cycle)

Description

Return the instructions that are scheduled at the specified cycle.

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:593

Parameters

int cycle

unsigned int getMaxStageCount()

Description

Return the maximum stage count needed for this schedule.

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:588

bool insert(llvm::SUnit* SU,
            int StartCycle,
            int EndCycle,
            int II)

Description

Try to schedule the node at the specified StartCycle and continue until the node is schedule or the EndCycle is reached. This function returns true if the node is scheduled. This routine may search either forward or backward for a place to insert the instruction based upon the relative values of StartCycle and EndCycle.

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:558

Parameters

llvm::SUnit* SU
int StartCycle
int EndCycle
int II

bool isLoopCarried(llvm::SwingSchedulerDAG* SSD,
                   llvm::MachineInstr& Phi)

Description

Return true if the scheduled Phi has a loop carried operand.

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:608

Parameters

llvm::SwingSchedulerDAG* SSD
llvm::MachineInstr& Phi

bool isLoopCarriedDefOfUse(
    llvm::SwingSchedulerDAG* SSD,
    llvm::MachineInstr* Def,
    llvm::MachineOperand& MO)

Description

Return true if the instruction is a definition that is loop carried and defines the use on the next iteration. v1 = phi(v2, v3) (Def) v3 = op v1 (MO) = v1 If MO appears before Def, then then v1 and v3 may get assigned to the same register.

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:609

Parameters

llvm::SwingSchedulerDAG* SSD
llvm::MachineInstr* Def
llvm::MachineOperand& MO

bool isScheduledAtStage(llvm::SUnit* SU,
                        unsigned int StageNum)

Description

Return true if the instruction is scheduled at the specified stage.

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:566

Parameters

llvm::SUnit* SU
unsigned int StageNum

bool isValidSchedule(llvm::SwingSchedulerDAG* SSD)

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:604

Parameters

llvm::SwingSchedulerDAG* SSD

int latestCycleInChain(const llvm::SDep& Dep)

Description

Return the cycle of the latest scheduled instruction in the dependence chain.

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:554

Parameters

const llvm::SDep& Dep

bool normalizeNonPipelinedInstructions(
    llvm::SwingSchedulerDAG* SSD,
    TargetInstrInfo::PipelinerLoopInfo* PLI)

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:602

Parameters

llvm::SwingSchedulerDAG* SSD
TargetInstrInfo::PipelinerLoopInfo* PLI

void orderDependence(llvm::SwingSchedulerDAG* SSD,
                     llvm::SUnit* SU,
                     std::deque<SUnit*>& Insts)

Description

Order the instructions within a cycle so that the definitions occur before the uses. Returns true if the instruction is added to the start of the list, or false if added to the end.

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:606

Parameters

llvm::SwingSchedulerDAG* SSD
llvm::SUnit* SU
std::deque<SUnit*>& Insts

void print(llvm::raw_ostream& os) const

Description

Print the schedule information to the given output.

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:611

Parameters

llvm::raw_ostream& os

void reset()

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:527

void setInitiationInterval(int ii)

Description

Set the initiation interval for this schedule.

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:536

Parameters

int ii

int stageScheduled(llvm::SUnit* SU) const

Description

Return the stage for a scheduled instruction. Return -1 if the instruction has not been scheduled.

Declared at: llvm/include/llvm/CodeGen/MachinePipeliner.h:572

Parameters

llvm::SUnit* SU