class InstrEmitter

Declaration

class InstrEmitter { /* full declaration omitted */ };

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:32

Member Variables

private llvm::MachineFunction* MF

private llvm::MachineRegisterInfo* MRI

private const llvm::TargetInstrInfo* TII

private const llvm::TargetRegisterInfo* TRI

private const llvm::TargetLowering* TLI

private llvm::MachineBasicBlock* MBB

private MachineBasicBlock::iterator InsertPos

private bool EmitDebugInstrRefs

Should we try to produce DBG_INSTR_REF instructions?

Method Overview

• public void AddDbgValueLocationOps(llvm::MachineInstrBuilder & MIB, const llvm::MCInstrDesc & DbgValDesc, ArrayRef<llvm::SDDbgOperand> Locations, DenseMap<llvm::SDValue, llvm::Register> & VRBaseMap)
• private void AddOperand(llvm::MachineInstrBuilder & MIB, llvm::SDValue Op, unsigned int IIOpNum, const llvm::MCInstrDesc * II, DenseMap<llvm::SDValue, llvm::Register> & VRBaseMap, bool IsDebug, bool IsClone, bool IsCloned)
• private void AddRegisterOperand(llvm::MachineInstrBuilder & MIB, llvm::SDValue Op, unsigned int IIOpNum, const llvm::MCInstrDesc * II, DenseMap<llvm::SDValue, llvm::Register> & VRBaseMap, bool IsDebug, bool IsClone, bool IsCloned)
• private llvm::Register ConstrainForSubReg(llvm::Register VReg, unsigned int SubIdx, llvm::MVT VT, bool isDivergent, const llvm::DebugLoc & DL)
• public static unsigned int CountResults(llvm::SDNode * Node)
• private void CreateVirtualRegisters(llvm::SDNode * Node, llvm::MachineInstrBuilder & MIB, const llvm::MCInstrDesc & II, bool IsClone, bool IsCloned, DenseMap<llvm::SDValue, llvm::Register> & VRBaseMap)
• private void EmitCopyFromReg(llvm::SDNode * Node, unsigned int ResNo, bool IsClone, bool IsCloned, llvm::Register SrcReg, DenseMap<llvm::SDValue, llvm::Register> & VRBaseMap)
• private void EmitCopyToRegClassNode(llvm::SDNode * Node, DenseMap<llvm::SDValue, llvm::Register> & VRBaseMap)
• public llvm::MachineInstr * EmitDbgInstrRef(llvm::SDDbgValue * SD, DenseMap<llvm::SDValue, llvm::Register> & VRBaseMap)
• public llvm::MachineInstr * EmitDbgLabel(llvm::SDDbgLabel * SD)
• public llvm::MachineInstr * EmitDbgNoLocation(llvm::SDDbgValue * SD)
• public llvm::MachineInstr * EmitDbgValue(llvm::SDDbgValue * SD, DenseMap<llvm::SDValue, llvm::Register> & VRBaseMap)
• public llvm::MachineInstr * EmitDbgValueFromSingleOp(llvm::SDDbgValue * SD, DenseMap<llvm::SDValue, llvm::Register> & VRBaseMap)
• private void EmitMachineNode(llvm::SDNode * Node, bool IsClone, bool IsCloned, DenseMap<llvm::SDValue, llvm::Register> & VRBaseMap)
• public void EmitNode(llvm::SDNode * Node, bool IsClone, bool IsCloned, DenseMap<llvm::SDValue, llvm::Register> & VRBaseMap)
• private void EmitRegSequence(llvm::SDNode * Node, DenseMap<llvm::SDValue, llvm::Register> & VRBaseMap, bool IsClone, bool IsCloned)
• private void EmitSpecialNode(llvm::SDNode * Node, bool IsClone, bool IsCloned, DenseMap<llvm::SDValue, llvm::Register> & VRBaseMap)
• private void EmitSubregNode(llvm::SDNode * Node, DenseMap<llvm::SDValue, llvm::Register> & VRBaseMap, bool IsClone, bool IsCloned)
• public InstrEmitter(const llvm::TargetMachine & TM, llvm::MachineBasicBlock * mbb, MachineBasicBlock::iterator insertpos, bool UseInstrRefDebugInfo)
• public llvm::MachineBasicBlock * getBlock()
• public MachineBasicBlock::iterator getInsertPos()
• private llvm::Register getVR(llvm::SDValue Op, DenseMap<llvm::SDValue, llvm::Register> & VRBaseMap)

Methods

¶void AddDbgValueLocationOps(
    llvm::MachineInstrBuilder& MIB,
    const llvm::MCInstrDesc& DbgValDesc,
    ArrayRef<llvm::SDDbgOperand> Locations,
    DenseMap<llvm::SDValue, llvm::Register>&
        VRBaseMap)

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:112

Parameters

llvm::MachineInstrBuilder& MIB

const llvm::MCInstrDesc& DbgValDesc

ArrayRef<llvm::SDDbgOperand> Locations

DenseMap<llvm::SDValue, llvm::Register>& VRBaseMap

¶void AddOperand(
    llvm::MachineInstrBuilder& MIB,
    llvm::SDValue Op,
    unsigned int IIOpNum,
    const llvm::MCInstrDesc* II,
    DenseMap<llvm::SDValue, llvm::Register>&
        VRBaseMap,
    bool IsDebug,
    bool IsClone,
    bool IsCloned)

Description

AddOperand - Add the specified operand to the specified machine instr. II specifies the instruction information for the node, and IIOpNum is the operand number (in the II) that we are adding. IIOpNum and II are used for assertions only.

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:77

Parameters

llvm::MachineInstrBuilder& MIB

llvm::SDValue Op

unsigned int IIOpNum

const llvm::MCInstrDesc* II

DenseMap<llvm::SDValue, llvm::Register>& VRBaseMap

bool IsDebug

bool IsClone

bool IsCloned

¶void AddRegisterOperand(
    llvm::MachineInstrBuilder& MIB,
    llvm::SDValue Op,
    unsigned int IIOpNum,
    const llvm::MCInstrDesc* II,
    DenseMap<llvm::SDValue, llvm::Register>&
        VRBaseMap,
    bool IsDebug,
    bool IsClone,
    bool IsCloned)

Description

AddRegisterOperand - Add the specified register as an operand to the specified machine instr. Insert register copies if the register is not in the required register class.

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:66

Parameters

llvm::MachineInstrBuilder& MIB

llvm::SDValue Op

unsigned int IIOpNum

const llvm::MCInstrDesc* II

DenseMap<llvm::SDValue, llvm::Register>& VRBaseMap

bool IsDebug

bool IsClone

bool IsCloned

¶llvm::Register ConstrainForSubReg(
    llvm::Register VReg,
    unsigned int SubIdx,
    llvm::MVT VT,
    bool isDivergent,
    const llvm::DebugLoc& DL)

Description

ConstrainForSubReg - Try to constrain VReg to a register class that supports SubIdx sub-registers. Emit a copy if that isn't possible. Return the virtual register to use.

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:87

Parameters

llvm::Register VReg

unsigned int SubIdx

llvm::MVT VT

bool isDivergent

const llvm::DebugLoc& DL

¶static unsigned int CountResults(
    llvm::SDNode* Node)

Description

CountResults - The results of target nodes have register or immediate operands first, then an optional chain, and optional flag operands (which do not go into the machine instrs.)

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:110

Parameters

llvm::SDNode* Node

¶void CreateVirtualRegisters(
    llvm::SDNode* Node,
    llvm::MachineInstrBuilder& MIB,
    const llvm::MCInstrDesc& II,
    bool IsClone,
    bool IsCloned,
    DenseMap<llvm::SDValue, llvm::Register>&
        VRBaseMap)

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:52

Parameters

llvm::SDNode* Node

llvm::MachineInstrBuilder& MIB

const llvm::MCInstrDesc& II

bool IsClone

bool IsCloned

DenseMap<llvm::SDValue, llvm::Register>& VRBaseMap

¶void EmitCopyFromReg(
    llvm::SDNode* Node,
    unsigned int ResNo,
    bool IsClone,
    bool IsCloned,
    llvm::Register SrcReg,
    DenseMap<llvm::SDValue, llvm::Register>&
        VRBaseMap)

Description

EmitCopyFromReg - Generate machine code for an CopyFromReg node or an implicit physical register output.

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:47

Parameters

llvm::SDNode* Node

unsigned int ResNo

bool IsClone

bool IsCloned

llvm::Register SrcReg

DenseMap<llvm::SDValue, llvm::Register>& VRBaseMap

¶void EmitCopyToRegClassNode(
    llvm::SDNode* Node,
    DenseMap<llvm::SDValue, llvm::Register>&
        VRBaseMap)

Description

EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. COPY_TO_REGCLASS is just a normal copy, except that the destination register is constrained to be in a particular register class.

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:99

Parameters

llvm::SDNode* Node

DenseMap<llvm::SDValue, llvm::Register>& VRBaseMap

¶llvm::MachineInstr* EmitDbgInstrRef(
    llvm::SDDbgValue* SD,
    DenseMap<llvm::SDValue, llvm::Register>&
        VRBaseMap)

Description

Emit a dbg_value as a DBG_INSTR_REF. May produce DBG_VALUE $noreg instead if there is no variable location; alternately a half-formed DBG_INSTR_REF that refers to a virtual register and is corrected later in isel.

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:125

Parameters

llvm::SDDbgValue* SD

DenseMap<llvm::SDValue, llvm::Register>& VRBaseMap

¶llvm::MachineInstr* EmitDbgLabel(
    llvm::SDDbgLabel* SD)

Description

Generate machine instruction for a dbg_label node.

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:136

Parameters

llvm::SDDbgLabel* SD

¶llvm::MachineInstr* EmitDbgNoLocation(
    llvm::SDDbgValue* SD)

Description

Emit a DBG_VALUE $noreg, indicating a variable has no location.

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:129

Parameters

llvm::SDDbgValue* SD

¶llvm::MachineInstr* EmitDbgValue(
    llvm::SDDbgValue* SD,
    DenseMap<llvm::SDValue, llvm::Register>&
        VRBaseMap)

Description

EmitDbgValue - Generate machine instruction for a dbg_value node.

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:119

Parameters

llvm::SDDbgValue* SD

DenseMap<llvm::SDValue, llvm::Register>& VRBaseMap

¶llvm::MachineInstr* EmitDbgValueFromSingleOp(
    llvm::SDDbgValue* SD,
    DenseMap<llvm::SDValue, llvm::Register>&
        VRBaseMap)

Description

Emit a DBG_VALUE from the operands to SDDbgValue.

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:132

Parameters

llvm::SDDbgValue* SD

DenseMap<llvm::SDValue, llvm::Register>& VRBaseMap

¶void EmitMachineNode(
    llvm::SDNode* Node,
    bool IsClone,
    bool IsCloned,
    DenseMap<llvm::SDValue, llvm::Register>&
        VRBaseMap)

Description

EmitMachineNode - Generate machine code for a target-specific node and needed dependencies.

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:161

Parameters

llvm::SDNode* Node

bool IsClone

bool IsCloned

DenseMap<llvm::SDValue, llvm::Register>& VRBaseMap

¶void EmitNode(llvm::SDNode* Node,
              bool IsClone,
              bool IsCloned,
              DenseMap<llvm::SDValue,
                       llvm::Register>& VRBaseMap)

Description

EmitNode - Generate machine code for a node and needed dependencies.

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:140

Parameters

llvm::SDNode* Node

bool IsClone

bool IsCloned

DenseMap<llvm::SDValue, llvm::Register>& VRBaseMap

¶void EmitRegSequence(
    llvm::SDNode* Node,
    DenseMap<llvm::SDValue, llvm::Register>&
        VRBaseMap,
    bool IsClone,
    bool IsCloned)

Description

EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:104

Parameters

llvm::SDNode* Node

DenseMap<llvm::SDValue, llvm::Register>& VRBaseMap

bool IsClone

bool IsCloned

¶void EmitSpecialNode(
    llvm::SDNode* Node,
    bool IsClone,
    bool IsCloned,
    DenseMap<llvm::SDValue, llvm::Register>&
        VRBaseMap)

Description

EmitSpecialNode - Generate machine code for a target-independent node and needed dependencies.

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:163

Parameters

llvm::SDNode* Node

bool IsClone

bool IsCloned

DenseMap<llvm::SDValue, llvm::Register>& VRBaseMap

¶void EmitSubregNode(
    llvm::SDNode* Node,
    DenseMap<llvm::SDValue, llvm::Register>&
        VRBaseMap,
    bool IsClone,
    bool IsCloned)

Description

EmitSubregNode - Generate machine code for subreg nodes.

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:92

Parameters

llvm::SDNode* Node

DenseMap<llvm::SDValue, llvm::Register>& VRBaseMap

bool IsClone

bool IsCloned

¶InstrEmitter(
    const llvm::TargetMachine& TM,
    llvm::MachineBasicBlock* mbb,
    MachineBasicBlock::iterator insertpos,
    bool UseInstrRefDebugInfo)

Description

InstrEmitter - Construct an InstrEmitter and set it to start inserting at the given position in the given block.

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:156

Parameters

const llvm::TargetMachine& TM

llvm::MachineBasicBlock* mbb

MachineBasicBlock::iterator insertpos

bool UseInstrRefDebugInfo

¶llvm::MachineBasicBlock* getBlock()

Description

getBlock - Return the current basic block.

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:149

¶MachineBasicBlock::iterator getInsertPos()

Description

getInsertPos - Return the current insertion position.

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:152

¶llvm::Register getVR(
    llvm::SDValue Op,
    DenseMap<llvm::SDValue, llvm::Register>&
        VRBaseMap)

Description

getVR - Return the virtual register corresponding to the specified result of the specified node.

Declared at: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h:60

Parameters

llvm::SDValue Op

DenseMap<llvm::SDValue, llvm::Register>& VRBaseMap