class X86InstrInfo

Declaration

class X86InstrInfo : public X86GenInstrInfo { /* full declaration omitted */ };

Description

TargetInstrInfo - Interface to description of machine instruction set

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:138

Inherits from: X86GenInstrInfo

Member Variables

private llvm::X86Subtarget& Subtarget

private const llvm::X86RegisterInfo RI

Inherited from TargetInstrInfo:

public static CommuteAnyOperandIndex = ~0U

Method Overview

• private bool AnalyzeBranchImpl(llvm::MachineBasicBlock & MBB, llvm::MachineBasicBlock *& TBB, llvm::MachineBasicBlock *& FBB, SmallVectorImpl<llvm::MachineOperand> & Cond, SmallVectorImpl<llvm::MachineInstr *> & CondBranches, bool AllowModify) const
• public X86InstrInfo(llvm::X86Subtarget & STI)
• public bool analyzeBranch(llvm::MachineBasicBlock & MBB, llvm::MachineBasicBlock *& TBB, llvm::MachineBasicBlock *& FBB, SmallVectorImpl<llvm::MachineOperand> & Cond, bool AllowModify) const
• public bool analyzeBranchPredicate(llvm::MachineBasicBlock & MBB, TargetInstrInfo::MachineBranchPredicate & MBP, bool AllowModify = false) const
• public bool analyzeCompare(const llvm::MachineInstr & MI, llvm::Register & SrcReg, llvm::Register & SrcReg2, int64_t & CmpMask, int64_t & CmpValue) const
• private virtual void anchor()
• public bool areLoadsFromSameBasePtr(llvm::SDNode * Load1, llvm::SDNode * Load2, int64_t & Offset1, int64_t & Offset2) const
• public void breakPartialRegDependency(llvm::MachineInstr & MI, unsigned int OpNum, const llvm::TargetRegisterInfo * TRI) const
• public void buildOutlinedFrame(llvm::MachineBasicBlock & MBB, llvm::MachineFunction & MF, const outliner::OutlinedFunction & OF) const
• public bool canInsertSelect(const llvm::MachineBasicBlock &, ArrayRef<llvm::MachineOperand> Cond, llvm::Register, llvm::Register, llvm::Register, int &, int &, int &) const
• public bool canMakeTailCallConditional(SmallVectorImpl<llvm::MachineOperand> & Cond, const llvm::MachineInstr & TailCall) const
• public bool classifyLEAReg(llvm::MachineInstr & MI, const llvm::MachineOperand & Src, unsigned int LEAOpcode, bool AllowSP, llvm::Register & NewSrc, bool & isKill, llvm::MachineOperand & ImplicitOp, llvm::LiveVariables * LV, llvm::LiveIntervals * LIS) const
• protected llvm::MachineInstr * commuteInstructionImpl(llvm::MachineInstr & MI, bool NewMI, unsigned int CommuteOpIdx1, unsigned int CommuteOpIdx2) const
• public llvm::MachineInstr * convertToThreeAddress(llvm::MachineInstr & MI, llvm::LiveVariables * LV, llvm::LiveIntervals * LIS) const
• private llvm::MachineInstr * convertToThreeAddressWithLEA(unsigned int MIOpc, llvm::MachineInstr & MI, llvm::LiveVariables * LV, llvm::LiveIntervals * LIS, bool Is8BitOp) const
• public void copyPhysReg(llvm::MachineBasicBlock & MBB, MachineBasicBlock::iterator MI, const llvm::DebugLoc & DL, llvm::MCRegister DestReg, llvm::MCRegister SrcReg, bool KillSrc) const
• public std::pair<unsigned int, unsigned int> decomposeMachineOperandsTargetFlags(unsigned int TF) const
• public Optional<llvm::ParamLoadedValue> describeLoadedValue(const llvm::MachineInstr & MI, llvm::Register Reg) const
• public bool expandPostRAPseudo(llvm::MachineInstr & MI) const
• public bool findCommutedOpIndices(const llvm::MachineInstr & MI, unsigned int & SrcOpIdx1, unsigned int & SrcOpIdx2) const
• private bool findThreeSrcCommutedOpIndices(const llvm::MachineInstr & MI, unsigned int & SrcOpIdx1, unsigned int & SrcOpIdx2, bool IsIntrinsic = false) const
• private llvm::MachineInstr * foldMemoryOperandCustom(llvm::MachineFunction & MF, llvm::MachineInstr & MI, unsigned int OpNum, ArrayRef<llvm::MachineOperand> MOs, MachineBasicBlock::iterator InsertPt, unsigned int Size, llvm::Align Alignment) const
• public llvm::MachineInstr * foldMemoryOperandImpl(llvm::MachineFunction & MF, llvm::MachineInstr & MI, unsigned int OpNum, ArrayRef<llvm::MachineOperand> MOs, MachineBasicBlock::iterator InsertPt, unsigned int Size, llvm::Align Alignment, bool AllowCommute) const
• public llvm::MachineInstr * foldMemoryOperandImpl(llvm::MachineFunction & MF, llvm::MachineInstr & MI, ArrayRef<unsigned int> Ops, MachineBasicBlock::iterator InsertPt, llvm::MachineInstr & LoadMI, llvm::LiveIntervals * LIS = nullptr) const
• public llvm::MachineInstr * foldMemoryOperandImpl(llvm::MachineFunction & MF, llvm::MachineInstr & MI, ArrayRef<unsigned int> Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, llvm::LiveIntervals * LIS = nullptr, llvm::VirtRegMap * VRM = nullptr) const
• public Optional<llvm::ExtAddrMode> getAddrModeFromMemoryOp(const llvm::MachineInstr & MemI, const llvm::TargetRegisterInfo * TRI) const
• public bool getConstValDefinedInReg(const llvm::MachineInstr & MI, const llvm::Register Reg, int64_t & ImmVal) const
• public std::pair<uint16_t, uint16_t> getExecutionDomain(const llvm::MachineInstr & MI) const
• public uint16_t getExecutionDomainCustom(const llvm::MachineInstr & MI) const
• public unsigned int getFMA3OpcodeToCommuteOperands(const llvm::MachineInstr & MI, unsigned int SrcOpIdx1, unsigned int SrcOpIdx2, const llvm::X86InstrFMA3Group & FMA3Group) const
• public int64_t getFrameAdjustment(const llvm::MachineInstr & I) const
• public unsigned int getGlobalBaseReg(llvm::MachineFunction * MF) const
• public bool getMemOperandsWithOffsetWidth(const llvm::MachineInstr & LdSt, SmallVectorImpl<const llvm::MachineOperand *> & BaseOps, int64_t & Offset, bool & OffsetIsScalable, unsigned int & Width, const llvm::TargetRegisterInfo * TRI) const
• public llvm::MCInst getNop() const
• public unsigned int getOpcodeAfterMemoryUnfold(unsigned int Opc, bool UnfoldLoad, bool UnfoldStore, unsigned int * LoadRegIndex = nullptr) const
• public outliner::OutlinedFunction getOutliningCandidateInfo(std::vector<outliner::Candidate> & RepeatedSequenceLocs) const
• public outliner::InstrType getOutliningType(MachineBasicBlock::iterator & MIT, unsigned int Flags) const
• public unsigned int getPartialRegUpdateClearance(const llvm::MachineInstr & MI, unsigned int OpNum, const llvm::TargetRegisterInfo * TRI) const
• public const llvm::X86RegisterInfo & getRegisterInfo() const
• public int getSPAdjust(const llvm::MachineInstr & MI) const
• public ArrayRef<std::pair<unsigned int, const char *>> getSerializableDirectMachineOperandTargetFlags() const
• public unsigned int getUndefRegClearance(const llvm::MachineInstr & MI, unsigned int OpNum, const llvm::TargetRegisterInfo * TRI) const
• public bool hasCommutePreference(llvm::MachineInstr & MI, bool & Commute) const
• public bool hasHighOperandLatency(const llvm::TargetSchedModel & SchedModel, const llvm::MachineRegisterInfo * MRI, const llvm::MachineInstr & DefMI, unsigned int DefIdx, const llvm::MachineInstr & UseMI, unsigned int UseIdx) const
• public bool hasLiveCondCodeDef(llvm::MachineInstr & MI) const
• public static bool hasLockPrefix(const llvm::MachineInstr & MI)
• public bool hasReassociableOperands(const llvm::MachineInstr & Inst, const llvm::MachineBasicBlock * MBB) const
• public unsigned int insertBranch(llvm::MachineBasicBlock & MBB, llvm::MachineBasicBlock * TBB, llvm::MachineBasicBlock * FBB, ArrayRef<llvm::MachineOperand> Cond, const llvm::DebugLoc & DL, int * BytesAdded = nullptr) const
• public MachineBasicBlock::iterator insertOutlinedCall(llvm::Module & M, llvm::MachineBasicBlock & MBB, MachineBasicBlock::iterator & It, llvm::MachineFunction & MF, outliner::Candidate & C) const
• public void insertSelect(llvm::MachineBasicBlock & MBB, MachineBasicBlock::iterator MI, const llvm::DebugLoc & DL, llvm::Register DstReg, ArrayRef<llvm::MachineOperand> Cond, llvm::Register TrueReg, llvm::Register FalseReg) const
• public bool isAssociativeAndCommutative(const llvm::MachineInstr & Inst) const
• public bool isCoalescableExtInstr(const llvm::MachineInstr & MI, llvm::Register & SrcReg, llvm::Register & DstReg, unsigned int & SubIdx) const
• protected Optional<llvm::DestSourcePair> isCopyInstrImpl(const llvm::MachineInstr & MI) const
• public static bool isDataInvariant(llvm::MachineInstr & MI)
• public static bool isDataInvariantLoad(llvm::MachineInstr & MI)
• private bool isFrameOperand(const llvm::MachineInstr & MI, unsigned int Op, int & FrameIndex) const
• public bool isFunctionSafeToOutlineFrom(llvm::MachineFunction & MF, bool OutlineFromLinkOnceODRs) const
• public bool isHighLatencyDef(int opc) const
• public unsigned int isLoadFromStackSlot(const llvm::MachineInstr & MI, int & FrameIndex, unsigned int & MemBytes) const
• public unsigned int isLoadFromStackSlot(const llvm::MachineInstr & MI, int & FrameIndex) const
• public unsigned int isLoadFromStackSlotPostFE(const llvm::MachineInstr & MI, int & FrameIndex) const
• public bool isReallyTriviallyReMaterializable(const llvm::MachineInstr & MI) const
• private bool isRedundantFlagInstr(const llvm::MachineInstr & FlagI, llvm::Register SrcReg, llvm::Register SrcReg2, int64_t ImmMask, int64_t ImmValue, const llvm::MachineInstr & OI, bool * IsSwapped, int64_t * ImmDelta) const
• public bool isSafeToMoveRegClassDefs(const llvm::TargetRegisterClass * RC) const
• public bool isSchedulingBoundary(const llvm::MachineInstr & MI, const llvm::MachineBasicBlock * MBB, const llvm::MachineFunction & MF) const
• public unsigned int isStoreToStackSlot(const llvm::MachineInstr & MI, int & FrameIndex) const
• public unsigned int isStoreToStackSlot(const llvm::MachineInstr & MI, int & FrameIndex, unsigned int & MemBytes) const
• public unsigned int isStoreToStackSlotPostFE(const llvm::MachineInstr & MI, int & FrameIndex) const
• public bool isSubregFoldable() const
• public static bool isThreeOperandsLEA(const llvm::MachineInstr & MI)
• public bool isUnconditionalTailCall(const llvm::MachineInstr & MI) const
• public void loadRegFromStackSlot(llvm::MachineBasicBlock & MBB, MachineBasicBlock::iterator MI, llvm::Register DestReg, int FrameIndex, const llvm::TargetRegisterClass * RC, const llvm::TargetRegisterInfo * TRI) const
• public bool optimizeCompareInstr(llvm::MachineInstr & CmpInstr, llvm::Register SrcReg, llvm::Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const llvm::MachineRegisterInfo * MRI) const
• public llvm::MachineInstr * optimizeLoadInstr(llvm::MachineInstr & MI, const llvm::MachineRegisterInfo * MRI, llvm::Register & FoldAsLoadDefReg, llvm::MachineInstr *& DefMI) const
• public bool preservesZeroValueInReg(const llvm::MachineInstr * MI, const llvm::Register NullValueReg, const llvm::TargetRegisterInfo * TRI) const
• public void reMaterialize(llvm::MachineBasicBlock & MBB, MachineBasicBlock::iterator MI, llvm::Register DestReg, unsigned int SubIdx, const llvm::MachineInstr & Orig, const llvm::TargetRegisterInfo & TRI) const
• public unsigned int removeBranch(llvm::MachineBasicBlock & MBB, int * BytesRemoved = nullptr) const
• public void replaceBranchWithTailCall(llvm::MachineBasicBlock & MBB, SmallVectorImpl<llvm::MachineOperand> & Cond, const llvm::MachineInstr & TailCall) const
• public bool reverseBranchCondition(SmallVectorImpl<llvm::MachineOperand> & Cond) const
• public void setExecutionDomain(llvm::MachineInstr & MI, unsigned int Domain) const
• public bool setExecutionDomainCustom(llvm::MachineInstr & MI, unsigned int Domain) const
• public void setFrameAdjustment(llvm::MachineInstr & I, int64_t V) const
• public void setSpecialOperandAttr(llvm::MachineInstr & OldMI1, llvm::MachineInstr & OldMI2, llvm::MachineInstr & NewMI1, llvm::MachineInstr & NewMI2) const
• public bool shouldScheduleLoadsNear(llvm::SDNode * Load1, llvm::SDNode * Load2, int64_t Offset1, int64_t Offset2, unsigned int NumLoads) const
• public void storeRegToStackSlot(llvm::MachineBasicBlock & MBB, MachineBasicBlock::iterator MI, llvm::Register SrcReg, bool isKill, int FrameIndex, const llvm::TargetRegisterClass * RC, const llvm::TargetRegisterInfo * TRI) const
• public bool unfoldMemoryOperand(llvm::MachineFunction & MF, llvm::MachineInstr & MI, unsigned int Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<llvm::MachineInstr *> & NewMIs) const
• public bool unfoldMemoryOperand(llvm::SelectionDAG & DAG, llvm::SDNode * N, SmallVectorImpl<llvm::SDNode *> & NewNodes) const
• public bool useMachineCombiner() const
• public bool verifyInstruction(const llvm::MachineInstr & MI, llvm::StringRef & ErrInfo) const

Inherited from X86GenInstrInfo:

Inherited from TargetInstrInfo:

• public ClobbersPredicate
• public CreateTargetHazardRecognizer
• public CreateTargetMIHazardRecognizer
• public CreateTargetPostRAHazardRecognizer
• public CreateTargetPostRAHazardRecognizer
• public CreateTargetScheduleState
• public FoldImmediate
• public PredicateInstruction
• public ReplaceTailWithBranchTo
• public SubsumesPredicate
• public analyzeBranch
• public analyzeBranchPredicate
• public analyzeCompare
• public analyzeLoop
• public analyzeLoopForPipelining
• public analyzeSelect
• public areLoadsFromSameBasePtr
• public areMemAccessesTriviallyDisjoint
• public breakPartialRegDependency
• public buildOutlinedFrame
• public canCopyGluedNodeDuringSchedule
• public canInsertSelect
• public canMakeTailCallConditional
• public commuteInstruction
• protected commuteInstructionImpl
• public convertToThreeAddress
• public copyPhysReg
• public createMIROperandComment
• public createPHIDestinationCopy
• public createPHISourceCopy
• public decomposeMachineOperandsTargetFlags
• public defaultDefLatency
• public describeLoadedValue
• public duplicate
• public expandPostRAPseudo
• public extraSizeToPredicateInstructions
• public finalizeInsInstrs
• public findCommutedOpIndices
• protected fixCommutedOpIndices
• public foldMemoryOperand
• public foldMemoryOperand
• protected foldMemoryOperandImpl
• protected foldMemoryOperandImpl
• public genAlternativeCodeSequence
• public getAddrModeFromMemoryOp
• public getBaseAndOffsetPosition
• public getBranchDestBlock
• public getCallFrameDestroyOpcode
• public getCallFrameSetupOpcode
• public getCalleeOperand
• public getCatchReturnOpcode
• public getConstValDefinedInReg
• public getExecutionDomain
• public getExtendResourceLenLimit
• public getExtractSubregInputs
• protected getExtractSubregLikeInputs
• public getFrameSize
• public getFrameTotalSize
• public getIncrementValue
• public getInlineAsmLength
• public getInsertSubregInputs
• protected getInsertSubregLikeInputs
• public getInstSizeInBytes
• public getInstrLatency
• public getInstrLatency
• public getMIRFormatter
• public getMachineCSELookAheadLimit
• public getMachineCombinerPatterns
• public getMemOperandAACheckLimit
• public getMemOperandWithOffset
• public getMemOperandsWithOffsetWidth
• public getNop
• public getNumMicroOps
• public getOpcodeAfterMemoryUnfold
• public getOperandLatency
• public getOperandLatency
• public getOutliningCandidateInfo
• public getOutliningType
• public getPartialRegUpdateClearance
• public getPatchpointUnfoldableRange
• public getPredicationCost
• public getRegClass
• public getRegSequenceInputs
• protected getRegSequenceLikeInputs
• public getReturnOpcode
• public getSPAdjust
• public getSerializableBitmaskMachineOperandTargetFlags
• public getSerializableDirectMachineOperandTargetFlags
• public getSerializableMachineMemOperandTargetFlags
• public getSerializableTargetIndices
• public getStackSlotRange
• public getTailDuplicateSize
• public getUndefRegClearance
• public hasCommutePreference
• public hasHighOperandLatency
• public hasLoadFromStackSlot
• public hasLowDefLatency
• public hasReassociableOperands
• public hasReassociableSibling
• public hasStoreToStackSlot
• public insertBranch
• public insertIndirectBranch
• public insertNoop
• public insertNoops
• public insertOutlinedCall
• public insertSelect
• public insertUnconditionalBranch
• public isAddImmediate
• public isAsCheapAsAMove
• public isAssociativeAndCommutative
• public isBasicBlockPrologue
• public isBranchOffsetInRange
• public isCoalescableExtInstr
• public isCopyInstr
• protected isCopyInstrImpl
• public isExtendLikelyToBeFolded
• public isFrameInstr
• public isFrameSetup
• public isFunctionSafeToOutlineFrom
• public isGenericOpcode
• public isHighLatencyDef
• public isIgnorableUse
• public isLegalToSplitMBBAt
• public isLoadFromStackSlot
• public isLoadFromStackSlot
• public isLoadFromStackSlotPostFE
• public isMBBSafeToOutlineFrom
• public isPCRelRegisterOperandLegal
• public isPostIncrement
• public isPredicable
• public isPredicated
• public isProfitableToDupForIfCvt
• public isProfitableToIfCvt
• public isProfitableToIfCvt
• public isProfitableToUnpredicate
• protected isReallyTriviallyReMaterializable
• public isReassociationCandidate
• public isSafeToMoveRegClassDefs
• public isSchedulingBoundary
• public isStackSlotCopy
• public isStoreToStackSlot
• public isStoreToStackSlot
• public isStoreToStackSlotPostFE
• public isSubregFoldable
• public isTailCall
• public isThroughputPattern
• public isTriviallyReMaterializable
• public isUnconditionalTailCall
• public isUnpredicatedTerminator
• public isUnspillableTerminator
• protected isUnspillableTerminatorImpl
• public isZeroCost
• public loadRegFromStackSlot
• public mergeOutliningCandidateAttributes
• public optimizeCompareInstr
• public optimizeCondBranch
• public optimizeLoadInstr
• public optimizeSelect
• public predictBranchSizeForIfCvt
• public preservesZeroValueInReg
• public produceSameValue
• public reMaterialize
• public reassociateOps
• public reduceLoopCount
• public removeBranch
• public replaceBranchWithTailCall
• public reverseBranchCondition
• public setExecutionDomain
• public setSpecialOperandAttr
• public shouldClusterMemOps
• public shouldHoist
• public shouldOutlineFromFunctionByDefault
• public shouldReduceRegisterPressure
• public shouldScheduleLoadsNear
• public shouldSink
• public storeRegToStackSlot
• public unfoldMemoryOperand
• public unfoldMemoryOperand
• public useMachineCombiner
• public usePreRAHazardRecognizer
• public verifyInstruction

Inherited from MCInstrInfo:

• public InitMCInstrInfo
• public get
• public getDeprecatedInfo
• public getName
• public getNumOpcodes

Methods

¶bool AnalyzeBranchImpl(
    llvm::MachineBasicBlock& MBB,
    llvm::MachineBasicBlock*& TBB,
    llvm::MachineBasicBlock*& FBB,
    SmallVectorImpl<llvm::MachineOperand>& Cond,
    SmallVectorImpl<llvm::MachineInstr*>&
        CondBranches,
    bool AllowModify) const

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:144

Parameters

llvm::MachineBasicBlock& MBB

llvm::MachineBasicBlock*& TBB

llvm::MachineBasicBlock*& FBB

SmallVectorImpl<llvm::MachineOperand>& Cond

SmallVectorImpl<llvm::MachineInstr*>& CondBranches

bool AllowModify

¶X86InstrInfo(llvm::X86Subtarget& STI)

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:151

Parameters

llvm::X86Subtarget& STI

¶bool analyzeBranch(
    llvm::MachineBasicBlock& MBB,
    llvm::MachineBasicBlock*& TBB,
    llvm::MachineBasicBlock*& FBB,
    SmallVectorImpl<llvm::MachineOperand>& Cond,
    bool AllowModify) const

Description

Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g. it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases: 1. If this block ends with no branches (it just falls through to its succ) just return false, leaving TBB/FBB null. 2. If this block ends with only an unconditional branch, it sets TBB to be the destination block. 3. If this block ends with a conditional branch and it falls through to a successor block, it sets TBB to be the branch destination block and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches. 4. If this block ends with a conditional branch followed by an unconditional branch, it returns the 'true' destination in TBB, the 'false' destination in FBB, and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches. Note that removeBranch and insertBranch must be implemented to support cases where this method returns success. If AllowModify is true, then this routine is allowed to modify the basic block (e.g. delete instructions after the unconditional branch). The CFG information in MBB.Predecessors and MBB.Successors must be valid before calling this function.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:325

Parameters

llvm::MachineBasicBlock& MBB

llvm::MachineBasicBlock*& TBB

llvm::MachineBasicBlock*& FBB

SmallVectorImpl<llvm::MachineOperand>& Cond

bool AllowModify

¶bool analyzeBranchPredicate(
    llvm::MachineBasicBlock& MBB,
    TargetInstrInfo::MachineBranchPredicate& MBP,
    bool AllowModify = false) const

Description

Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure if possible. Returns false on success and true on failure. If AllowModify is true, then this routine is allowed to modify the basic block (e.g. delete instructions after the unconditional branch).

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:346

Parameters

llvm::MachineBasicBlock& MBB

TargetInstrInfo::MachineBranchPredicate& MBP

bool AllowModify = false

¶bool analyzeCompare(const llvm::MachineInstr& MI,
                    llvm::Register& SrcReg,
                    llvm::Register& SrcReg2,
                    int64_t& CmpMask,
                    int64_t& CmpValue) const

Description

analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. Return true if the comparison instruction can be analyzed.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:518

Parameters

const llvm::MachineInstr& MI

llvm::Register& SrcReg

llvm::Register& SrcReg2

int64_t& CmpMask

int64_t& CmpValue

¶virtual void anchor()

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:142

¶bool areLoadsFromSameBasePtr(
    llvm::SDNode* Load1,
    llvm::SDNode* Load2,
    int64_t& Offset1,
    int64_t& Offset2) const

Description

areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address. It should only return true if the base pointers are the same and the only differences between the two addresses are the offset. It also returns the offsets by reference.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:430

Parameters

llvm::SDNode* Load1

llvm::SDNode* Load2

int64_t& Offset1

int64_t& Offset2

¶void breakPartialRegDependency(
    llvm::MachineInstr& MI,
    unsigned int OpNum,
    const llvm::TargetRegisterInfo* TRI) const

Description

Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum. If it wasn't possible to avoid a def in the last N instructions before MI (see getPartialRegUpdateClearance), this hook will be called to break the unwanted dependency. On x86, an xorps instruction can be used as a dependency breaker: addps %xmm1, %xmm0 movaps %xmm0, (%rax) xorps %xmm0, %xmm0 cvtsi2ss %rbx, %xmm0 An <imp -kill> operand should be added to MI if an instruction was inserted. This ties the instructions together in the post-ra scheduler.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:485

Parameters

llvm::MachineInstr& MI

unsigned int OpNum

const llvm::TargetRegisterInfo* TRI

¶void buildOutlinedFrame(
    llvm::MachineBasicBlock& MBB,
    llvm::MachineFunction& MF,
    const outliner::OutlinedFunction& OF) const

Description

Insert a custom frame for outlined functions.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:556

Parameters

llvm::MachineBasicBlock& MBB

llvm::MachineFunction& MF

const outliner::OutlinedFunction& OF

¶bool canInsertSelect(
    const llvm::MachineBasicBlock&,
    ArrayRef<llvm::MachineOperand> Cond,
    llvm::Register,
    llvm::Register,
    llvm::Register,
    int&,
    int&,
    int&) const

Description

Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond. When successful, also return the latency in cycles from TrueReg, FalseReg, and Cond to the destination register. In most cases, a select instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1 Some x86 implementations have 2-cycle cmov instructions.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:356

Parameters

const llvm::MachineBasicBlock&

ArrayRef<llvm::MachineOperand> Cond

Condition returned by analyzeBranch.

llvm::Register

llvm::Register

llvm::Register

int&

int&

int&

¶bool canMakeTailCallConditional(
    SmallVectorImpl<llvm::MachineOperand>& Cond,
    const llvm::MachineInstr& TailCall) const

Description

Returns true if the tail call can be made conditional on BranchCond.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:319

Parameters

SmallVectorImpl<llvm::MachineOperand>& Cond

const llvm::MachineInstr& TailCall

¶bool classifyLEAReg(
    llvm::MachineInstr& MI,
    const llvm::MachineOperand& Src,
    unsigned int LEAOpcode,
    bool AllowSP,
    llvm::Register& NewSrc,
    bool& isKill,
    llvm::MachineOperand& ImplicitOp,
    llvm::LiveVariables* LV,
    llvm::LiveIntervals* LIS) const

Description

Given an operand within a MachineInstr, insert preceding code to put it into the right format for a particular kind of LEA instruction. This may involve using an appropriate super-register instead (with an implicit use of the original) or creating a new virtual register and inserting COPY instructions to get the data into the right class. Reference parameters are set to indicate how caller should add this operand to the LEA instruction.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:257

Parameters

llvm::MachineInstr& MI

const llvm::MachineOperand& Src

unsigned int LEAOpcode

bool AllowSP

llvm::Register& NewSrc

bool& isKill

llvm::MachineOperand& ImplicitOp

llvm::LiveVariables* LV

llvm::LiveIntervals* LIS

¶llvm::MachineInstr* commuteInstructionImpl(
    llvm::MachineInstr& MI,
    bool NewMI,
    unsigned int CommuteOpIdx1,
    unsigned int CommuteOpIdx2) const

Description

Commutes the operands in the given instruction by changing the operands order and/or changing the instruction's opcode and/or the immediate value operand. The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands to be commuted. Do not call this method for a non-commutable instruction or non-commutable operands. Even though the instruction is commutable, the method may still fail to commute the operands, null pointer is returned in such cases.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:588

Parameters

llvm::MachineInstr& MI

bool NewMI

unsigned int CommuteOpIdx1

unsigned int CommuteOpIdx2

¶llvm::MachineInstr* convertToThreeAddress(
    llvm::MachineInstr& MI,
    llvm::LiveVariables* LV,
    llvm::LiveIntervals* LIS) const

Description

convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target may be able to convert a two-address instruction into a true three-address instruction on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two-addressness. This method returns a null pointer if the transformation cannot be performed, otherwise it returns the new instruction.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:272

Parameters

llvm::MachineInstr& MI

llvm::LiveVariables* LV

llvm::LiveIntervals* LIS

¶llvm::MachineInstr* convertToThreeAddressWithLEA(
    unsigned int MIOpc,
    llvm::MachineInstr& MI,
    llvm::LiveVariables* LV,
    llvm::LiveIntervals* LIS,
    bool Is8BitOp) const

Description

This is a helper for convertToThreeAddress for 8 and 16-bit instructions. We use 32-bit LEA to form 3-address code by promoting to a 32-bit super-register and then truncating back down to a 8/16-bit sub-register.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:602

Parameters

unsigned int MIOpc

llvm::MachineInstr& MI

llvm::LiveVariables* LV

llvm::LiveIntervals* LIS

bool Is8BitOp

¶void copyPhysReg(llvm::MachineBasicBlock& MBB,
                 MachineBasicBlock::iterator MI,
                 const llvm::DebugLoc& DL,
                 llvm::MCRegister DestReg,
                 llvm::MCRegister SrcReg,
                 bool KillSrc) const

Description

Emit instructions to copy a pair of physical registers. This function should support copies within any legal register class as well as any cross-class copies created during instruction selection. The source and destination registers may overlap, which may require a careful implementation when multiple copy instructions are required for large registers. See for example the ARM target.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:363

Parameters

llvm::MachineBasicBlock& MBB

MachineBasicBlock::iterator MI

const llvm::DebugLoc& DL

llvm::MCRegister DestReg

llvm::MCRegister SrcReg

bool KillSrc

¶std::pair<unsigned int, unsigned int>
decomposeMachineOperandsTargetFlags(
    unsigned int TF) const

Description

Decompose the machine operand's target flags into two values - the direct target flag value and any of bit flags that are applied.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:542

Parameters

unsigned int TF

¶Optional<llvm::ParamLoadedValue>
describeLoadedValue(const llvm::MachineInstr& MI,
                    llvm::Register Reg) const

Description

Produce the expression describing the \p MI loading a value into the physical register \p Reg. This hook should only be used with\p MIs belonging to VReg-less functions.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:573

Parameters

const llvm::MachineInstr& MI

llvm::Register Reg

¶bool expandPostRAPseudo(
    llvm::MachineInstr& MI) const

Description

This function is called for all pseudo instructions that remain after register allocation. Many pseudo instructions are created to help register allocation. This is the place to convert them into real instructions. The target can edit MI in place, or it can insert new instructions and erase MI. The function should return true if anything was changed.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:377

Parameters

llvm::MachineInstr& MI

¶bool findCommutedOpIndices(
    const llvm::MachineInstr& MI,
    unsigned int& SrcOpIdx1,
    unsigned int& SrcOpIdx2) const

Description

Returns true iff the routine could find two commutable operands in the given machine instruction. The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their input values can be re-defined in this method only if the input values are not pre-defined, which is designated by the special value 'CommuteAnyOperandIndex' assigned to it. If both of indices are pre-defined and refer to some operands, then the method simply returns true if the corresponding operands are commutable and returns false otherwise. For example, calling this method this way: unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; findCommutedOpIndices(MI, Op1, Op2); can be interpreted as a query asking to find an operand that would be commutable with the operand#1.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:290

Parameters

const llvm::MachineInstr& MI

unsigned int& SrcOpIdx1

unsigned int& SrcOpIdx2

¶bool findThreeSrcCommutedOpIndices(
    const llvm::MachineInstr& MI,
    unsigned int& SrcOpIdx1,
    unsigned int& SrcOpIdx2,
    bool IsIntrinsic = false) const

Description

Returns true iff the routine could find two commutable operands in the given machine instruction with 3 vector inputs. The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their input values can be re-defined in this method only if the input values are not pre-defined, which is designated by the special value 'CommuteAnyOperandIndex' assigned to it. If both of indices are pre-defined and refer to some operands, then the method simply returns true if the corresponding operands are commutable and returns false otherwise. For example, calling this method this way: unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; findThreeSrcCommutedOpIndices(MI, Op1, Op2); can be interpreted as a query asking to find an operand that would be commutable with the operand#1. If IsIntrinsic is set, operand 1 will be ignored for commuting.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:637

Parameters

const llvm::MachineInstr& MI

unsigned int& SrcOpIdx1

unsigned int& SrcOpIdx2

bool IsIntrinsic = false

¶llvm::MachineInstr* foldMemoryOperandCustom(
    llvm::MachineFunction& MF,
    llvm::MachineInstr& MI,
    unsigned int OpNum,
    ArrayRef<llvm::MachineOperand> MOs,
    MachineBasicBlock::iterator InsertPt,
    unsigned int Size,
    llvm::Align Alignment) const

Description

Handles memory folding for special case instructions, for instance those requiring custom manipulation of the address.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:609

Parameters

llvm::MachineFunction& MF

llvm::MachineInstr& MI

unsigned int OpNum

ArrayRef<llvm::MachineOperand> MOs

MachineBasicBlock::iterator InsertPt

unsigned int Size

llvm::Align Alignment

¶llvm::MachineInstr* foldMemoryOperandImpl(
    llvm::MachineFunction& MF,
    llvm::MachineInstr& MI,
    unsigned int OpNum,
    ArrayRef<llvm::MachineOperand> MOs,
    MachineBasicBlock::iterator InsertPt,
    unsigned int Size,
    llvm::Align Alignment,
    bool AllowCommute) const

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:488

Parameters

llvm::MachineFunction& MF

llvm::MachineInstr& MI

unsigned int OpNum

ArrayRef<llvm::MachineOperand> MOs

MachineBasicBlock::iterator InsertPt

unsigned int Size

llvm::Align Alignment

bool AllowCommute

¶llvm::MachineInstr* foldMemoryOperandImpl(
    llvm::MachineFunction& MF,
    llvm::MachineInstr& MI,
    ArrayRef<unsigned int> Ops,
    MachineBasicBlock::iterator InsertPt,
    llvm::MachineInstr& LoadMI,
    llvm::LiveIntervals* LIS = nullptr) const

Description

foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:399

Parameters

llvm::MachineFunction& MF

llvm::MachineInstr& MI

ArrayRef<unsigned int> Ops

MachineBasicBlock::iterator InsertPt

llvm::MachineInstr& LoadMI

llvm::LiveIntervals* LIS = nullptr

¶llvm::MachineInstr* foldMemoryOperandImpl(
    llvm::MachineFunction& MF,
    llvm::MachineInstr& MI,
    ArrayRef<unsigned int> Ops,
    MachineBasicBlock::iterator InsertPt,
    int FrameIndex,
    llvm::LiveIntervals* LIS = nullptr,
    llvm::VirtRegMap* VRM = nullptr) const

Description

foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s). If this is possible, the target should perform the folding and return true, otherwise it should return false. If it folds the instruction, it is likely that the MachineInstruction the iterator references has been changed.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:390

Parameters

llvm::MachineFunction& MF

llvm::MachineInstr& MI

ArrayRef<unsigned int> Ops

MachineBasicBlock::iterator InsertPt

int FrameIndex

llvm::LiveIntervals* LIS = nullptr

llvm::VirtRegMap* VRM = nullptr

¶Optional<llvm::ExtAddrMode>
getAddrModeFromMemoryOp(
    const llvm::MachineInstr& MemI,
    const llvm::TargetRegisterInfo* TRI) const

Description

Target dependent implementation to get the values constituting the address MachineInstr that is accessing memory. These values are returned as a struct ExtAddrMode which contains all relevant information to make up the address.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:331

Parameters

const llvm::MachineInstr& MemI

const llvm::TargetRegisterInfo* TRI

¶bool getConstValDefinedInReg(
    const llvm::MachineInstr& MI,
    const llvm::Register Reg,
    int64_t& ImmVal) const

Description

Returns true if MI is an instruction that defines Reg to have a constant value and the value is recorded in ImmVal. The ImmVal is a result that should be interpreted as modulo size of Reg.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:334

Parameters

const llvm::MachineInstr& MI

const llvm::Register Reg

int64_t& ImmVal

¶std::pair<uint16_t, uint16_t> getExecutionDomain(
    const llvm::MachineInstr& MI) const

Description

Return the current execution domain and bit mask of possible domains for instruction. Some micro-architectures have multiple execution domains, and multiple opcodes that perform the same operation in different domains. For example, the x86 architecture provides the por, orps, and orpd instructions that all do the same thing. There is a latency penalty if a register is written in one domain and read in another. This function returns a pair (domain, mask) containing the execution domain of MI, and a bit mask of possible domains. The setExecutionDomain function can be used to change the opcode to one of the domains in the bit mask. Instructions whose execution domain can't be changed should return a 0 mask. The execution domain numbers don't have any special meaning except domain 0 is used for instructions that are not associated with any interesting execution domain.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:472

Parameters

const llvm::MachineInstr& MI

¶uint16_t getExecutionDomainCustom(
    const llvm::MachineInstr& MI) const

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:474

Parameters

const llvm::MachineInstr& MI

¶unsigned int getFMA3OpcodeToCommuteOperands(
    const llvm::MachineInstr& MI,
    unsigned int SrcOpIdx1,
    unsigned int SrcOpIdx2,
    const llvm::X86InstrFMA3Group& FMA3Group)
    const

Description

Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computations as the given \p MI but which has the operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted. It may return 0 if it is unsafe to commute the operands. Note that a machine instruction (instead of its opcode) is passed as the first parameter to make it possible to analyze the instruction's uses and commute the first operand of FMA even when it seems unsafe when you look at the opcode. For example, it is Ok to commute the first operand of VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used. The returned FMA opcode may differ from the opcode in the given \p MI. For example, commuting the operands #1 and #3 in the following FMA FMA213 #1, #2, #3 results into instruction with adjusted opcode: FMA231 #3, #2, #1

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:313

Parameters

const llvm::MachineInstr& MI

unsigned int SrcOpIdx1

unsigned int SrcOpIdx2

const llvm::X86InstrFMA3Group& FMA3Group

¶int64_t getFrameAdjustment(
    const llvm::MachineInstr& I) const

Description

Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e.g. by pushes, or inside the callee).

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:161

Parameters

const llvm::MachineInstr& I

¶unsigned int getGlobalBaseReg(
    llvm::MachineFunction* MF) const

Description

getGlobalBaseReg - Return a virtual register initialized with the the global base register value. Output instructions required to initialize the register in the function entry block, if necessary.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:469

Parameters

llvm::MachineFunction* MF

¶bool getMemOperandsWithOffsetWidth(
    const llvm::MachineInstr& LdSt,
    SmallVectorImpl<const llvm::MachineOperand*>&
        BaseOps,
    int64_t& Offset,
    bool& OffsetIsScalable,
    unsigned int& Width,
    const llvm::TargetRegisterInfo* TRI) const

Description

Get zero or more base operands and the byte offset of an instruction that reads/writes memory. Note that there may be zero base operands if the instruction accesses a constant address. It returns false if MI does not read/write memory. It returns false if base operands and offset could not be determined. It is not guaranteed to always recognize base operands and offsets in all cases.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:341

Parameters

const llvm::MachineInstr& LdSt

SmallVectorImpl<const llvm::MachineOperand*>& BaseOps

int64_t& Offset

bool& OffsetIsScalable

unsigned int& Width

const llvm::TargetRegisterInfo* TRI

¶llvm::MCInst getNop() const

Description

Return the noop instruction to use for a noop.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:452

¶unsigned int getOpcodeAfterMemoryUnfold(
    unsigned int Opc,
    bool UnfoldLoad,
    bool UnfoldStore,
    unsigned int* LoadRegIndex = nullptr) const

Description

getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode. It returns zero if the specified unfolding is not possible. If LoadRegIndex is non-null, it is filled in with the operand index of the operand which will hold the register holding the loaded value.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:422

Parameters

unsigned int Opc

bool UnfoldLoad

bool UnfoldStore

unsigned int* LoadRegIndex = nullptr

¶outliner::OutlinedFunction
getOutliningCandidateInfo(
    std::vector<outliner::Candidate>&
        RepeatedSequenceLocs) const

Description

Returns a \p outliner::OutlinedFunction struct containing target-specific information for a set of outlining candidates.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:547

Parameters

std::vector<outliner::Candidate>& RepeatedSequenceLocs

¶outliner::InstrType getOutliningType(
    MachineBasicBlock::iterator& MIT,
    unsigned int Flags) const

Description

Returns how or if \p MI should be outlined.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:554

Parameters

MachineBasicBlock::iterator& MIT

unsigned int Flags

¶unsigned int getPartialRegUpdateClearance(
    const llvm::MachineInstr& MI,
    unsigned int OpNum,
    const llvm::TargetRegisterInfo* TRI) const

Description

Returns the preferred minimum clearance before an instruction with an unwanted partial register update. Some instructions only write part of a register, and implicitly need to read the other parts of the register. This may cause unwanted stalls preventing otherwise unrelated instructions from executing in parallel in an out-of-order CPU. For example, the x86 instruction cvtsi2ss writes its result to bits [31:0] of the destination xmm register. Bits [127:32] are unaffected, so the instruction needs to wait for the old value of the register to become available: addps %xmm1, %xmm0 movaps %xmm0, (%rax) cvtsi2ss %rbx, %xmm0 In the code above, the cvtsi2ss instruction needs to wait for the addps instruction before it can issue, even though the high bits of %xmm0 probably aren't needed. This hook returns the preferred clearance before MI, measured in instructions. Other defs of MI's operand OpNum are avoided in the last N instructions before MI. It should only return a positive value for unwanted dependencies. If the old bits of the defined register have useful values, or if MI is determined to otherwise read the dependency, the hook should return 0. The unwanted dependency may be handled by: 1. Allocating the same register for an MI def and use. That makes the unwanted dependency identical to a required dependency. 2. Allocating a register for the def that has no defs in the previous N instructions. 3. Calling breakPartialRegDependency() with the same arguments. This allows the target to insert a dependency breaking instruction.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:481

Parameters

const llvm::MachineInstr& MI

unsigned int OpNum

const llvm::TargetRegisterInfo* TRI

¶const llvm::X86RegisterInfo& getRegisterInfo()
    const

Description

getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:157

¶int getSPAdjust(
    const llvm::MachineInstr& MI) const

Description

getSPAdjust - This returns the stack pointer adjustment made by this instruction. For x86, we need to handle more complex call sequences involving PUSHes.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:181

Parameters

const llvm::MachineInstr& MI

¶ArrayRef<std::pair<unsigned int, const char*>>
getSerializableDirectMachineOperandTargetFlags()
    const

Description

Return an array that contains the direct target flag values and their names. MIR Serialization is able to serialize only the target flags that are defined by this method.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:545

¶unsigned int getUndefRegClearance(
    const llvm::MachineInstr& MI,
    unsigned int OpNum,
    const llvm::TargetRegisterInfo* TRI) const

Description

Return the minimum clearance before an instruction that reads an unused register. For example, AVX instructions may copy part of a register operand into the unused high bits of the destination register. vcvtsi2sdq %rax, undef %xmm0, %xmm14 In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a false dependence on any previous write to %xmm0. This hook works similarly to getPartialRegUpdateClearance, except that it does not take an operand index. Instead sets \p OpNum to the index of the unused register.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:483

Parameters

const llvm::MachineInstr& MI

unsigned int OpNum

const llvm::TargetRegisterInfo* TRI

¶bool hasCommutePreference(llvm::MachineInstr& MI,
                          bool& Commute) const

Description

Returns true if we have preference on the operands order in MI, the commute decision is returned in Commute.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:295

Parameters

llvm::MachineInstr& MI

bool& Commute

¶bool hasHighOperandLatency(
    const llvm::TargetSchedModel& SchedModel,
    const llvm::MachineRegisterInfo* MRI,
    const llvm::MachineInstr& DefMI,
    unsigned int DefIdx,
    const llvm::MachineInstr& UseMI,
    unsigned int UseIdx) const

Description

Compute operand latency between a def of 'Reg' and a use in the current loop. Return true if the target considered it 'high'. This is used by optimization passes such as machine LICM to determine whether it makes sense to hoist an instruction out even in a high register pressure situation.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:497

Parameters

const llvm::TargetSchedModel& SchedModel

const llvm::MachineRegisterInfo* MRI

const llvm::MachineInstr& DefMI

unsigned int DefIdx

const llvm::MachineInstr& UseMI

unsigned int UseIdx

¶bool hasLiveCondCodeDef(
    llvm::MachineInstr& MI) const

Description

True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:463

Parameters

llvm::MachineInstr& MI

¶static bool hasLockPrefix(
    const llvm::MachineInstr& MI)

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:569

Parameters

const llvm::MachineInstr& MI

¶bool hasReassociableOperands(
    const llvm::MachineInstr& Inst,
    const llvm::MachineBasicBlock* MBB) const

Description

Return true when \PInst has reassociable operands in the same \PMBB.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:507

Parameters

const llvm::MachineInstr& Inst

const llvm::MachineBasicBlock* MBB

¶unsigned int insertBranch(
    llvm::MachineBasicBlock& MBB,
    llvm::MachineBasicBlock* TBB,
    llvm::MachineBasicBlock* FBB,
    ArrayRef<llvm::MachineOperand> Cond,
    const llvm::DebugLoc& DL,
    int* BytesAdded = nullptr) const

Description

Insert branch code into the end of the specified MachineBasicBlock. The operands to this method are the same as those returned by analyzeBranch. This is only invoked in cases where analyzeBranch returns success. It returns the number of instructions inserted. If \p BytesAdded is non-null, report the change in code size from the added instructions. It is also invoked by tail merging to add unconditional branches in cases where analyzeBranch doesn't apply because there was no original branch to analyze. At least this much must be implemented, else tail merging needs to be disabled. The CFG information in MBB.Predecessors and MBB.Successors must be valid before calling this function.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:352

Parameters

llvm::MachineBasicBlock& MBB

llvm::MachineBasicBlock* TBB

llvm::MachineBasicBlock* FBB

ArrayRef<llvm::MachineOperand> Cond

const llvm::DebugLoc& DL

int* BytesAdded = nullptr

¶MachineBasicBlock::iterator insertOutlinedCall(
    llvm::Module& M,
    llvm::MachineBasicBlock& MBB,
    MachineBasicBlock::iterator& It,
    llvm::MachineFunction& MF,
    outliner::Candidate& C) const

Description

Insert a call to an outlined function into the program. Returns an iterator to the spot where we inserted the call. This must be implemented by the target.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:560

Parameters

llvm::Module& M

llvm::MachineBasicBlock& MBB

MachineBasicBlock::iterator& It

llvm::MachineFunction& MF

outliner::Candidate& C

¶void insertSelect(
    llvm::MachineBasicBlock& MBB,
    MachineBasicBlock::iterator MI,
    const llvm::DebugLoc& DL,
    llvm::Register DstReg,
    ArrayRef<llvm::MachineOperand> Cond,
    llvm::Register TrueReg,
    llvm::Register FalseReg) const

Description

Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when Cond is false. This function can only be called after canInsertSelect() returned true. The condition in Cond comes from analyzeBranch, and it can be assumed that the same flags or registers required by Cond are available at the insertion point.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:359

Parameters

llvm::MachineBasicBlock& MBB

Block where select instruction should be inserted.

MachineBasicBlock::iterator MI

const llvm::DebugLoc& DL

Source location for debugging.

llvm::Register DstReg

Virtual register to be defined by select instruction.

ArrayRef<llvm::MachineOperand> Cond

Condition as computed by analyzeBranch.

llvm::Register TrueReg

Virtual register to copy when Cond is true.

llvm::Register FalseReg

Virtual register to copy when Cons is false.

¶bool isAssociativeAndCommutative(
    const llvm::MachineInstr& Inst) const

Description

Return true when \PInst is both associative and commutative.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:505

Parameters

const llvm::MachineInstr& Inst

¶bool isCoalescableExtInstr(
    const llvm::MachineInstr& MI,
    llvm::Register& SrcReg,
    llvm::Register& DstReg,
    unsigned int& SubIdx) const

Description

isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction. That is, it's like a copy where it's legal for the source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns true, then it's expected the pre-extension value is available as a subreg of the result register. This also returns the sub-register index in SubIdx.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:189

Parameters

const llvm::MachineInstr& MI

llvm::Register& SrcReg

llvm::Register& DstReg

unsigned int& SubIdx

¶Optional<llvm::DestSourcePair> isCopyInstrImpl(
    const llvm::MachineInstr& MI) const

Description

If the specific machine instruction is a instruction that moves/copies value from one register to another register return destination and source registers as machine operands.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:596

Parameters

const llvm::MachineInstr& MI

¶static bool isDataInvariant(
    llvm::MachineInstr& MI)

Description

Returns true if the instruction has no behavior (specified or otherwise) that is based on the value of any of its register operands Instructions are considered data invariant even if they set EFLAGS. A classical example of something that is inherently not data invariant is an indirect jump -- the destination is loaded into icache based on the bits set in the jump destination register. FIXME: This should become part of our instruction tables.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:202

Parameters

llvm::MachineInstr& MI

¶static bool isDataInvariantLoad(
    llvm::MachineInstr& MI)

Description

Returns true if the instruction has no behavior (specified or otherwise) that is based on the value loaded from memory or the value of any non-address register operands. For example, if the latency of the instruction is dependent on the particular bits set in any of the registers *or* any of the bits loaded from memory. Instructions are considered data invariant even if they set EFLAGS. A classical example of something that is inherently not data invariant is an indirect jump -- the destination is loaded into icache based on the bits set in the jump destination register. FIXME: This should become part of our instruction tables.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:219

Parameters

llvm::MachineInstr& MI

¶bool isFrameOperand(const llvm::MachineInstr& MI,
                    unsigned int Op,
                    int& FrameIndex) const

Description

isFrameOperand - Return true and the FrameIndex if the specified operand and follow operands form a reference to the stack frame.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:617

Parameters

const llvm::MachineInstr& MI

unsigned int Op

int& FrameIndex

¶bool isFunctionSafeToOutlineFrom(
    llvm::MachineFunction& MF,
    bool OutlineFromLinkOnceODRs) const

Description

Return true if the function can safely be outlined from. A function \p MF is considered safe for outlining if an outlined function produced from instructions in F will produce a program which produces the same output for any set of given inputs.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:550

Parameters

llvm::MachineFunction& MF

bool OutlineFromLinkOnceODRs

¶bool isHighLatencyDef(int opc) const

Description

Return true if this opcode has high latency to its result.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:495

Parameters

int opc

¶unsigned int isLoadFromStackSlot(
    const llvm::MachineInstr& MI,
    int& FrameIndex,
    unsigned int& MemBytes) const

Description

Optional extension of isLoadFromStackSlot that returns the number of bytes loaded from the stack. This must be implemented if a backend supports partial stack slot spills/loads to further disambiguate what the load does.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:223

Parameters

const llvm::MachineInstr& MI

int& FrameIndex

unsigned int& MemBytes

¶unsigned int isLoadFromStackSlot(
    const llvm::MachineInstr& MI,
    int& FrameIndex) const

Description

If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:221

Parameters

const llvm::MachineInstr& MI

int& FrameIndex

¶unsigned int isLoadFromStackSlotPostFE(
    const llvm::MachineInstr& MI,
    int& FrameIndex) const

Description

isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well. This uses a heuristic so it isn't reliable for correctness.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:229

Parameters

const llvm::MachineInstr& MI

int& FrameIndex

¶bool isReallyTriviallyReMaterializable(
    const llvm::MachineInstr& MI) const

Description

For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target specify whether the instruction is actually trivially rematerializable, taking into consideration its operands. This predicate must return false if the instruction has any side effects other than producing a value, or if it requres any address registers that are not always available. Requirements must be check as stated in isTriviallyReMaterializable() .

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:243

Parameters

const llvm::MachineInstr& MI

¶bool isRedundantFlagInstr(
    const llvm::MachineInstr& FlagI,
    llvm::Register SrcReg,
    llvm::Register SrcReg2,
    int64_t ImmMask,
    int64_t ImmValue,
    const llvm::MachineInstr& OI,
    bool* IsSwapped,
    int64_t* ImmDelta) const

Description

Returns true when instruction \p FlagI produces the same flags as \p OI. The caller should pass in the results of calling analyzeCompare on \p OI: \p SrcReg, \p SrcReg2, \p ImmMask, \p ImmValue. If the flags match \p OI as if it had the input operands swapped then the function succeeds and sets \p IsSwapped to true. Examples of OI, FlagI pairs returning true: CMP %1, 42 and CMP %1, 42 CMP %1, %2 and %3 = SUB %1, %2 TEST %1, %1 and %2 = SUB %1, 0 CMP %1, %2 and %3 = SUB %2, %1 ; IsSwapped=true

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:653

Parameters

const llvm::MachineInstr& FlagI

llvm::Register SrcReg

llvm::Register SrcReg2

int64_t ImmMask

int64_t ImmValue

const llvm::MachineInstr& OI

bool* IsSwapped

int64_t* ImmDelta

¶bool isSafeToMoveRegClassDefs(
    const llvm::TargetRegisterClass* RC) const

Description

isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the specified register class.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:459

Parameters

const llvm::TargetRegisterClass* RC

¶bool isSchedulingBoundary(
    const llvm::MachineInstr& MI,
    const llvm::MachineBasicBlock* MBB,
    const llvm::MachineFunction& MF) const

Description

isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR intructions and prevent it from being re-scheduled.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:436

Parameters

const llvm::MachineInstr& MI

const llvm::MachineBasicBlock* MBB

const llvm::MachineFunction& MF

¶unsigned int isStoreToStackSlot(
    const llvm::MachineInstr& MI,
    int& FrameIndex) const

Description

If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:232

Parameters

const llvm::MachineInstr& MI

int& FrameIndex

¶unsigned int isStoreToStackSlot(
    const llvm::MachineInstr& MI,
    int& FrameIndex,
    unsigned int& MemBytes) const

Description

Optional extension of isStoreToStackSlot that returns the number of bytes stored to the stack. This must be implemented if a backend supports partial stack slot spills/loads to further disambiguate what the store does.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:234

Parameters

const llvm::MachineInstr& MI

int& FrameIndex

unsigned int& MemBytes

¶unsigned int isStoreToStackSlotPostFE(
    const llvm::MachineInstr& MI,
    int& FrameIndex) const

Description

isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well. This uses a heuristic so it isn't reliable for correctness.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:240

Parameters

const llvm::MachineInstr& MI

int& FrameIndex

¶bool isSubregFoldable() const

Description

Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds a store).

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:381

¶static bool isThreeOperandsLEA(
    const llvm::MachineInstr& MI)

Declared at: build/lib/Target/X86/X86GenInstrInfo.inc:57259

Parameters

const llvm::MachineInstr& MI

¶bool isUnconditionalTailCall(
    const llvm::MachineInstr& MI) const

Description

Returns true if MI is an unconditional tail call.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:318

Parameters

const llvm::MachineInstr& MI

¶void loadRegFromStackSlot(
    llvm::MachineBasicBlock& MBB,
    MachineBasicBlock::iterator MI,
    llvm::Register DestReg,
    int FrameIndex,
    const llvm::TargetRegisterClass* RC,
    const llvm::TargetRegisterInfo* TRI) const

Description

Load the specified register of the given register class from the specified stack frame index. The load instruction is to be added to the given machine basic block before the specified machine instruction.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:372

Parameters

llvm::MachineBasicBlock& MBB

MachineBasicBlock::iterator MI

llvm::Register DestReg

int FrameIndex

const llvm::TargetRegisterClass* RC

const llvm::TargetRegisterInfo* TRI

¶bool optimizeCompareInstr(
    llvm::MachineInstr& CmpInstr,
    llvm::Register SrcReg,
    llvm::Register SrcReg2,
    int64_t CmpMask,
    int64_t CmpValue,
    const llvm::MachineRegisterInfo* MRI) const

Description

optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source operands and sets flags in the same way as Compare; remove Compare if possible.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:525

Parameters

llvm::MachineInstr& CmpInstr

llvm::Register SrcReg

llvm::Register SrcReg2

int64_t CmpMask

int64_t CmpValue

const llvm::MachineRegisterInfo* MRI

¶llvm::MachineInstr* optimizeLoadInstr(
    llvm::MachineInstr& MI,
    const llvm::MachineRegisterInfo* MRI,
    llvm::Register& FoldAsLoadDefReg,
    llvm::MachineInstr*& DefMI) const

Description

optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use. We fold the load instructions if and only if the def and use are in the same BB. We only look at one load and see whether it can be folded into MI. FoldAsLoadDefReg is the virtual register defined by the load we are trying to fold. DefMI returns the machine instruction that defines FoldAsLoadDefReg, and the function returns the machine instruction generated due to folding.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:536

Parameters

llvm::MachineInstr& MI

const llvm::MachineRegisterInfo* MRI

llvm::Register& FoldAsLoadDefReg

llvm::MachineInstr*& DefMI

¶bool preservesZeroValueInReg(
    const llvm::MachineInstr* MI,
    const llvm::Register NullValueReg,
    const llvm::TargetRegisterInfo* TRI) const

Description

Returns true if MI's Def is NullValueReg, and the MI does not change the Zero value. i.e. cases such as rax = shr rax, X where NullValueReg = rax. Note that if the NullValueReg is non-zero, this function can return true even if becomes zero. Specifically cases such as NullValueReg = shl NullValueReg, 63.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:337

Parameters

const llvm::MachineInstr* MI

const llvm::Register NullValueReg

const llvm::TargetRegisterInfo* TRI

¶void reMaterialize(
    llvm::MachineBasicBlock& MBB,
    MachineBasicBlock::iterator MI,
    llvm::Register DestReg,
    unsigned int SubIdx,
    const llvm::MachineInstr& Orig,
    const llvm::TargetRegisterInfo& TRI) const

Description

Re-issue the specified 'original' instruction at the specific location targeting a new destination register. The register in Orig->getOperand(0).getReg() will be substituted by DestReg:SubIdx. Any existing subreg index is preserved or composed with SubIdx.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:244

Parameters

llvm::MachineBasicBlock& MBB

MachineBasicBlock::iterator MI

llvm::Register DestReg

unsigned int SubIdx

const llvm::MachineInstr& Orig

const llvm::TargetRegisterInfo& TRI

¶unsigned int removeBranch(
    llvm::MachineBasicBlock& MBB,
    int* BytesRemoved = nullptr) const

Description

Remove the branching code at the end of the specific MBB. This is only invoked in cases where analyzeBranch returns success. It returns the number of instructions that were removed. If \p BytesRemoved is non-null, report the change in code size from the removed instructions.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:350

Parameters

llvm::MachineBasicBlock& MBB

int* BytesRemoved = nullptr

¶void replaceBranchWithTailCall(
    llvm::MachineBasicBlock& MBB,
    SmallVectorImpl<llvm::MachineOperand>& Cond,
    const llvm::MachineInstr& TailCall) const

Description

Replace the conditional branch in MBB with a conditional tail call.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:321

Parameters

llvm::MachineBasicBlock& MBB

SmallVectorImpl<llvm::MachineOperand>& Cond

const llvm::MachineInstr& TailCall

¶bool reverseBranchCondition(
    SmallVectorImpl<llvm::MachineOperand>& Cond)
    const

Description

Reverses the branch condition of the specified condition list, returning false on success and true if it cannot be reversed.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:455

Parameters

SmallVectorImpl<llvm::MachineOperand>& Cond

¶void setExecutionDomain(llvm::MachineInstr& MI,
                        unsigned int Domain) const

Description

Change the opcode of MI to execute in Domain. The bit (1 < < Domain) must be set in the mask returned from getExecutionDomain(MI).

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:476

Parameters

llvm::MachineInstr& MI

unsigned int Domain

¶bool setExecutionDomainCustom(
    llvm::MachineInstr& MI,
    unsigned int Domain) const

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:478

Parameters

llvm::MachineInstr& MI

unsigned int Domain

¶void setFrameAdjustment(llvm::MachineInstr& I,
                        int64_t V) const

Description

Sets the stack pointer adjustment made inside the frame made up by this instruction.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:170

Parameters

llvm::MachineInstr& I

int64_t V

¶void setSpecialOperandAttr(
    llvm::MachineInstr& OldMI1,
    llvm::MachineInstr& OldMI2,
    llvm::MachineInstr& NewMI1,
    llvm::MachineInstr& NewMI2) const

Description

This is an architecture-specific helper function of reassociateOps. Set special operand attributes for new instructions after reassociation.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:510

Parameters

llvm::MachineInstr& OldMI1

llvm::MachineInstr& OldMI2

llvm::MachineInstr& NewMI1

llvm::MachineInstr& NewMI2

¶bool shouldScheduleLoadsNear(
    llvm::SDNode* Load1,
    llvm::SDNode* Load2,
    int64_t Offset1,
    int64_t Offset2,
    unsigned int NumLoads) const

Description

shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther. On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:448

Parameters

llvm::SDNode* Load1

llvm::SDNode* Load2

int64_t Offset1

int64_t Offset2

unsigned int NumLoads

¶void storeRegToStackSlot(
    llvm::MachineBasicBlock& MBB,
    MachineBasicBlock::iterator MI,
    llvm::Register SrcReg,
    bool isKill,
    int FrameIndex,
    const llvm::TargetRegisterClass* RC,
    const llvm::TargetRegisterInfo* TRI) const

Description

Store the specified register of the given register class to the specified stack frame index. The store instruction is to be added to the given machine basic block before the specified machine instruction. If isKill is true, the register operand is the last use and must be marked kill.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:366

Parameters

llvm::MachineBasicBlock& MBB

MachineBasicBlock::iterator MI

llvm::Register SrcReg

bool isKill

int FrameIndex

const llvm::TargetRegisterClass* RC

const llvm::TargetRegisterInfo* TRI

¶bool unfoldMemoryOperand(
    llvm::MachineFunction& MF,
    llvm::MachineInstr& MI,
    unsigned int Reg,
    bool UnfoldLoad,
    bool UnfoldStore,
    SmallVectorImpl<llvm::MachineInstr*>& NewMIs)
    const

Description

unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction. If this is possible, returns true as well as the new instructions by reference.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:408

Parameters

llvm::MachineFunction& MF

llvm::MachineInstr& MI

unsigned int Reg

bool UnfoldLoad

bool UnfoldStore

SmallVectorImpl<llvm::MachineInstr*>& NewMIs

¶bool unfoldMemoryOperand(
    llvm::SelectionDAG& DAG,
    llvm::SDNode* N,
    SmallVectorImpl<llvm::SDNode*>& NewNodes)
    const

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:412

Parameters

llvm::SelectionDAG& DAG

llvm::SDNode* N

SmallVectorImpl<llvm::SDNode*>& NewNodes

¶bool useMachineCombiner() const

Description

Return true when a target supports MachineCombiner.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:503

¶bool verifyInstruction(
    const llvm::MachineInstr& MI,
    llvm::StringRef& ErrInfo) const

Description

Perform target-specific instruction verification.

Declared at: llvm/lib/Target/X86/X86InstrInfo.h:564

Parameters

const llvm::MachineInstr& MI

llvm::StringRef& ErrInfo